Patent application number | Description | Published |
20080200001 | METHOD OF PRODUCING A TRANSISTOR - Method of producing a transistor, comprising in particular the steps of: | 08-21-2008 |
20080283877 | Strained-channel transistor device - Semiconductor device comprising at least:
| 11-20-2008 |
20080290384 | Microelectronic Device Provided with Transistors Coated with a Piezoelectric Layer - An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels. | 11-27-2008 |
20080297180 | DEVICE FOR MEASURING METAL/SEMICONDUCTOR CONTACT RESISTIVITY - A device for measuring the resistivity ρ | 12-04-2008 |
20090014769 | SUSPENDED-GATE MOS TRANSISTOR WITH NON-VOLATILE OPERATION - A transistor device with a mobile suspended gate, the device comprising means for piezoelectric actuation of the gate, and a method for producing such a device. | 01-15-2009 |
20090016095 | NON-VOLATILE SRAM MEMORY CELL EQUIPPED WITH MOBILE GATE TRANSISTORS AND PIEZOELECTRIC OPERATION - The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate. | 01-15-2009 |
20090079004 | METHOD FOR MAKING A TRANSISTOR WITH SELF-ALIGNED DOUBLE GATES BY REDUCING GATE PATTERNS - This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns ( | 03-26-2009 |
20090127584 | Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor - Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone. | 05-21-2009 |
20090286363 | METHOD FOR MAKING A TRANSISTOR WITH METALLIC SOURCE AND DRAIN - Method for making a field effect transistor comprising the following steps:
| 11-19-2009 |
20090294822 | CIRCUIT WITH TRANSISTORS INTEGRATED IN THREE DIMENSIONS AND HAVING A DYNAMICALLY ADJUSTABLE THRESHOLD VOLTAGE VT - A microelectronic device comprising:
| 12-03-2009 |
20090294861 | SRAM MEMORY CELL HAVING TRANSISTORS INTEGRATED AT SEVERAL LEVELS AND THE THRESHOLD VOLTAGE VT OF WHICH IS DYNAMICALLY ADJUSTABLE - A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises: | 12-03-2009 |
20100096700 | METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate. | 04-22-2010 |
20100178743 | METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS - A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted. | 07-15-2010 |
20100317167 | METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block. | 12-16-2010 |
20100320541 | METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block. | 12-23-2010 |
20110003443 | METHOD FOR PRODUCING A TRANSISTOR WITH METALLIC SOURCE AND DRAIN - A method for producing a transistor with metallic source and drain including the steps of:
| 01-06-2011 |
20110147849 | INTEGRATED CIRCUIT WITH ELECTROSTATICALLY COUPLED MOS TRANSISTORS AND METHOD FOR PRODUCING SUCH AN INTEGRATED CIRCUIT - An integrated circuit including:
| 06-23-2011 |
20120187488 | FIELD EFFECT DEVICE PROVIDED WITH A THINNED COUNTER-ELECTRODE AND METHOD FOR FABRICATING - A field effect device comprises a substrate of semiconductor on insulator type successively provided with a support substrate, an electrically insulating layer and a semiconductor material film. First and second source/drain electrodes are formed in the semiconductor material layer. A conduction channel is formed in the semiconductor material layer and separates the first and second source/drain electrodes. A counter-electrode is formed in the support substrate and faces the first and second source/drain electrodes and the conduction channel. The counter-electrode is formed by a doped area of the support substrate having a first doping impurity concentration which decreases from an interface between the electrically insulating layer and the support substrate. | 07-26-2012 |
20120187489 | FIELD EFFECT DEVICE PROVIDED WITH A LOCALIZED DOPANT DIFFUSION BARRIER AREA AND FABRICATION METHOD - The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes. | 07-26-2012 |
20120190214 | METHOD FOR FABRICATING A FIELD EFFECT DEVICE WITH WEAK JUNCTION CAPACITANCE - The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes. | 07-26-2012 |
20120256262 | FIELD EFFECT TRANSISTOR WITH OFFSET COUNTER-ELECTRODE CONTACT - The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode. | 10-11-2012 |
20130109191 | METHOD TO PREPARE SEMI-CONDUCTOR DEVICE COMPRISING A SELECTIVE ETCHING OF A SILICIUM-GERMANIUM LAYER | 05-02-2013 |
20130113004 | LIGHT-EMITTING DEVICE WITH HEAD-TO-TAIL P-TYPE AND N-TYPE TRANSISTORS - A light-emitting microelectronic device including a first N-type transistor (T | 05-09-2013 |
20130113066 | UTBB CMOS IMAGER - An image sensor device comprising at least one transistor lying on a semiconductor-on-insulator substrate, the substrate comprising a thin semi-conducting layer wherein a channel area of said transistor is made, an insulating layer separating the thin semi-conducting layer with a semi-conducting support layer, the device being characterized in that the semi-conducting support layer comprises at least one photosensitive area including at least one P-doped region and at least one N-doped region forming a junction provided facing the channel area of said transistor. | 05-09-2013 |
20130161746 | TRANSISTOR AND METHOD OF FABRICATION - A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned toward an upper face of the active layer and a source and a drain disposed on both sides of the gate. At least one among the source and the drain extends at least partly through the active layer and into the insulating layer. | 06-27-2013 |
20130189825 | METHOD OF PRODUCING INSULATION TRENCHES IN A SEMICONDUCTOR ON INSULATOR SUBSTRATE - A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of:
| 07-25-2013 |
20130193494 | TRANSISTOR WITH COUNTER-ELECTRODE CONNECTION AMALGAMATED WITH THE SOURCE/DRAIN CONTACT - The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern. | 08-01-2013 |
20130302955 | METHOD FOR PRODUCING A TRANSISTOR STRUCTURE WITH SUPERIMPOSED NANOWIRES AND WITH A SURROUNDING GATE - The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. | 11-14-2013 |
20130309449 | METHOD FOR TREATING THE SURFACE OF A SILICON SUBSTRATE - The present invention relates to a method for chemically treating the surface condition of a silicon substrate for the roughness contrast characterized in that it comprises at least two successive treatment cycles, with each treatment cycle comprising a first step including placing in contact the silicon substrate with a first solution containing water diluted hydrofluoric (HF) acid and then a second step carried out at a temperature of less than 40° C., comprising placing in contact the silicon layer with a second solution containing water (H | 11-21-2013 |
20140054699 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM OXIDE LINER AND UPPER NITRIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 02-27-2014 |
20140087524 | METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION THROUGH THE SPACERS - The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free. | 03-27-2014 |
20140127871 | METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH A SiGe CHANNEL BY ION IMPLANTATION - The semiconductor-on-insulator substrate includes a support, an electrically insulating film, a crystalline film made from semiconductor material, and a protection layer. Germanium ions are implanted in the semiconductor material film through the protection layer so as to form an amorphized area in contact with the protection layer and a crystalline area in contact with the electrically insulating film. The semiconductor material film is annealed so as to recrystallize the amorphized area from the crystalline area. | 05-08-2014 |
20140246723 | METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR - A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide. | 09-04-2014 |
20140335663 | METHOD OF MAKING A TRANSITOR - A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy. | 11-13-2014 |
20140370666 | METHOD OF MAKING A SEMICONDUCTOR LAYER HAVING AT LEAST TWO DIFFERENT THICKNESSES - A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions. | 12-18-2014 |
20140370668 | METHOD OF MAKING A TRANSITOR - The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack. | 12-18-2014 |