Patent application number | Description | Published |
20090081563 | Integrated Circuits and Methods of Design and Manufacture Thereof - Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features. | 03-26-2009 |
20090081579 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
20090081585 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
20090081597 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
20090081598 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
20090104566 | Process of multiple exposures with spin castable film - Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures. | 04-23-2009 |
20090203200 | GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH - A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation. | 08-13-2009 |
20090233236 | METHOD FOR FABRICATING SELF-ALIGNED NANOSTRUCTURE USING SELF-ASSEMBLY BLOCK COPOLYMERS, AND STRUCTURES FABRICATED THEREFROM - In one embodiment, the present invention provides a method for patterning a surface that includes forming a block copolymer atop a heterogeneous reflectivity surface, wherein the block copolymer is segregated into first and second units; applying a radiation to the first units and second units, wherein the heterogeneous reflectivity surface produces an exposed portion of the first units and the second units; and applying a development cycle to selectively remove at least one of the exposed first and second units of the segregated copolymer film to provide a pattern. | 09-17-2009 |
20090246958 | METHOD FOR REMOVING RESIDUES FROM A PATTERNED SUBSTRATE - The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer. | 10-01-2009 |
20090311490 | CHEMICAL TRIM OF PHOTORESIST LINES BY MEANS OF A TUNED OVERCOAT MATERIAL - A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line. The invention also comprises a product produced by this process. | 12-17-2009 |
20110045407 | Functionalized Carbosilane Polymers and Photoresist Compositions Containing the Same - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 02-24-2011 |
20110147984 | METHODS OF DIRECTED SELF-ASSEMBLY, AND LAYERED STRUCTURES FORMED THEREFROM - A method of forming a layered structure comprising a self-assembled material comprises: disposing a non-crosslinking photoresist layer on a substrate; pattern-wise exposing the photoresist layer to first radiation; optionally heating the exposed photoresist layer; developing the exposed photoresist layer in a first development process with an aqueous alkaline developer, forming an initial patterned photoresist layer; treating the initial patterned photoresist layer photochemically, thermally and/or chemically, thereby forming a treated patterned photoresist layer comprising non-crosslinked treated photoresist disposed on a first substrate surface; casting a solution of an orientation control material in a first solvent on the treated patterned photoresist layer, and removing the first solvent, forming an orientation control layer; heating the orientation control layer to effectively bind a portion of the orientation control material to a second substrate surface; removing at least a portion of the treated photoresist and, optionally, any non-bound orientation control material in a second development process, thereby forming a pre-pattern for self-assembly; optionally heating the pre-pattern; casting a solution of a material capable of self-assembly dissolved in a second solvent on the pre-pattern and removing the second solvent; and allowing the casted material to self-assemble with optional heating and/or annealing, thereby forming the layered structure comprising the self-assembled material. | 06-23-2011 |
20110204523 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 08-25-2011 |
20110256359 | METHOD AND MATERIAL FOR A THERMALLY CROSSLINKABLE RANDOM COPOLYMER - A structure that comprises a substrate; a cross-linked random free radical copolymer on the substrate; and a self-assembled patterned diblock copolymer film on the random copolymer; wherein the random copolymer is energy neutral with respect to each block of the diblock copolymer film. A method of making the structure is provided. | 10-20-2011 |
20120126294 | WAFER FILL PATTERNS AND USES - A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements. | 05-24-2012 |
20120126358 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH - A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 05-24-2012 |
20120282779 | SIDEWALL IMAGE TRANSFER PROCESS EMPLOYING A CAP MATERIAL LAYER FOR A METAL NITRIDE LAYER - A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer. | 11-08-2012 |
20130026639 | Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 01-31-2013 |
20130175658 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH FOR SEMICONDUCTOR DEVICE FORMATION - A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 07-11-2013 |
20130181267 | WAFER FILL PATTERNS AND USES - A semiconductor device includes an active region including an element formed in a double etch, double exposure method and an inactive region including one or more fills, at least one of the one or more fills including a cut-away hole formed therein, where the cut-away holes expose a layer in the inactive region used for an endpoint detection. | 07-18-2013 |
20140099583 | SIMULTANEOUS PHOTORESIST DEVELOPMENT AND NEUTRAL POLYMER LAYER FORMATION - A photoresist layer is lithographically exposed to form lithographically exposed photoresist regions and lithographically unexposed photoresist regions. The photoresist layer is developed with a non-polar or weakly polar solvent including a dissolved neutral polymer material. A neutral polymer layer is selectively formed on physically exposed surfaces of a hard mask layer underlying the photoresist layer. The neutral polymer layer has a pattern corresponding to the complement of the area of remaining portions of the photoresist layer. The remaining portions of the photoresist layer are then removed with a polar solvent without removing the neutral polymer layer on the hard mask layer. A block copolymer material can be subsequently applied over the neutral polymer, and the neutral polymer layer can guide the alignment of a phase-separated block copolymer material in a directed self-assembly. | 04-10-2014 |
20140138863 | METHODS OF FORMING NANOPARTICLES USING SEMICONDUCTOR MANUFACTURING INFRASTRUCTURE - A method of preparing particles comprises forming by optical lithography a topographic template layer disposed on a surface of a substrate, which is suitable for spin casting. The template layer comprises a non-crosslinked template polymer having a pattern of independent wells therein for molding independent particles. Spin casting a particle-forming composition onto the template layer forms a composite layer comprising the template polymer and the particles disposed in the wells. The composite layer is removed from the substrate using a stripping agent that dissolves the template polymer without dissolving the particles. The particles are then isolated. | 05-22-2014 |
20140256145 | DSA GRAPHO-EPITAXY PROCESS WITH ETCH STOP MATERIAL - A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials. | 09-11-2014 |
20140315390 | GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN - A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern. | 10-23-2014 |
20140322917 | GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN - A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern. | 10-30-2014 |
20150041812 | INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES - Semiconductor devices include a first set of fins having a uniform fin pitch that is less than half a minimum fin pitch for an associated lithography process; and a second set of fins having a variable fin pitch that is less the minimum fin pitch for the associated lithography process but greater than half the minimum fin pitch for the associated lithography process. | 02-12-2015 |
20150041958 | INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES - Semiconductor devices and method for forming the same. Methods for forming fin structures include forming a protective layer over a set of mandrels in a variable fin pitch region; forming first sidewalls around a set of mandrels in a uniform fin pitch region; removing the set of mandrels in the uniform fin pitch region; removing the protective layer; forming second sidewalls around the first sidewalls in the uniform fin pitch region and the mandrels in the variable fin pitch region; removing the first sidewalls and the mandrels; and etching an underlying layer around the second sidewalls. | 02-12-2015 |