Patent application number | Description | Published |
20110108999 | Microelectronic package and method of manufacturing same - A microelectronic package comprises a die ( | 05-12-2011 |
20110241195 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure. | 10-06-2011 |
20110316140 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a substrate ( | 12-29-2011 |
20120074580 | METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C | 03-29-2012 |
20120139095 | LOW-PROFILE MICROELECTRONIC PACKAGE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC ASSEMBLY CONTAINING SAME - A low-profile microelectronic package includes a die ( | 06-07-2012 |
20120139116 | BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND METHODS OF ASSEMBLING SAME - A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure. | 06-07-2012 |
20130001794 | IN SITU-BUILT PIN-GRID ARRAYS FOR CORELESS SUBSTRATES, AND METHODS OF MAKING SAME - A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins. | 01-03-2013 |
20130119544 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a substrate ( | 05-16-2013 |
20130214403 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure. | 08-22-2013 |
20130228911 | LOW-PROFILE MICROELECTRONIC PACKAGE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC ASSEMBLY CONTAINING SAME - A low-profile microelectronic package includes a die ( | 09-05-2013 |
20130270691 | PACKAGE FOR A MICROELECTRONIC DIE, MICROELECTRONIC ASSEMBLY CONTAINING SAME, MICROELECTRONIC SYSTEM, AND METHOD OF REDUCING DIE STRESS IN A MICROELECTRONIC PACKAGE - A package for a microelectronic die ( | 10-17-2013 |
20130341772 | SUBSTRATE CONDUCTOR STRUCTURE AND METHOD - Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components. | 12-26-2013 |
20130344662 | BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND METHODS OF ASSEMBLING SAME - A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure. | 12-26-2013 |
20140070380 | BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY - Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed. | 03-13-2014 |
20140159850 | INDUCTOR FORMED IN SUBSTRATE - A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate. | 06-12-2014 |
20140160675 | LANDSIDE STIFFENING CAPACITORS TO ENABLE ULTRATHIN AND OTHER LOW-Z PRODUCTS - Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described herein. In some embodiments, an apparatus includes an IC mounted on a package substrate, and a capacitive stiffener subassembly mounted on the package substrate. The capacitive stiffener subassembly includes a plurality of capacitive elements electrically connected to contacts of the IC. | 06-12-2014 |
20140166353 | ELECTRICAL INTERCONNECT FORMED THROUGH BUILDUP PROCESS - This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface. | 06-19-2014 |
20140175636 | HIGH DENSITY INTERCONNECT DEVICE AND METHOD - Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards. | 06-26-2014 |
20140179060 | IN SITU-BUILT PIN-GRID ARRAYS FOR CORELESS SUBSTRATES, AND METHODS OF MAKING SAME - A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins. | 06-26-2014 |
20140197545 | NON-CYLINDRICAL CONDUCTING SHAPES IN MULTILAYER LAMINATED SUBSTRATE CORES - Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern on a top surface of the multilayer core. At least one elongated via extends through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias. | 07-17-2014 |
20140251669 | SUSPENDED INDUCTOR MICROELECTRONIC STRUCTURES - The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface. | 09-11-2014 |
20140264791 | DIRECT EXTERNAL INTERCONNECT FOR EMBEDDED INTERCONNECT BRIDGE PACKAGE - An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions. | 09-18-2014 |
20140367843 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure. | 12-18-2014 |
20150035144 | HIGH DENSITY INTERCONNECT DEVICE AND METHOD - Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards. | 02-05-2015 |
20150092378 | DIRECT CHIP ATTACH USING EMBEDDED TRACES - A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices. | 04-02-2015 |
Patent application number | Description | Published |
20090182320 | Cryosurgical System - A cryosurgical system using a low-pressure liquid nitrogen supply, which requires only 0.5 to 15 bar of pressure to provide adequate cooling power for treatment of typical breast lesions. The pressure may be provided by supplying lightly pressurized air into the dewar, by heating a small portion of the nitrogen in the dewar, or with a small low pressure pump. | 07-16-2009 |
20100198205 | Low Pressure Liquid Nitrogen Cryosurgical System - A cryosurgical system using a low-pressure liquid nitrogen supply, which requires only 0.5 to 1 bar of pressure to provide adequate cooling power for treatment of typical breast lesions. The pressure may be provided by supplying lightly pressurized air into the dewar, by heating a small portion of the nitrogen in the dewar, or with a small low pressure pump. | 08-05-2010 |
20110082454 | Cryosurgical System - A cryosurgical system using a low-pressure liquid nitrogen supply, which requires only 0.5 to 15 bar of pressure to provide adequate cooling power for treatment of typical breast lesions. The pressure may be provided by supplying lightly pressurized air into the dewar, by heating a small portion of the nitrogen in the dewar, or with a small low pressure pump. | 04-07-2011 |
20110112521 | Cryoprobe for Low Pressure Systems - A cryoprobe for use in cryosurgery and other applications comprising a rigid outer tube, an inner coolant inlet tube. a short rigid penetrating segment extending distally from the distal end of the outer tube and a helical-shaped baffle having a heating element disposed about the outer surface of the inlet tube. The baffle is adapted to produce turbulent fluid flow improving heat transfer and is able to warm target tissue during rapid freezing and thawing cycles. | 05-12-2011 |
20140163539 | Cryoprobe for Low Pressure Systems - A cryoprobe for use in cryosurgery and other applications comprising a rigid outer tube, an inner coolant inlet tube. a short rigid penetrating segment extending distally from the distal end of the outer tube and a helical-shaped baffle having a heating element disposed about the outer surface of the inlet tube. The baffle is adapted to produce turbulent fluid flow improving heat transfer and is able to warm target tissue during rapid freezing and thawing cycles. | 06-12-2014 |