Patent application number | Description | Published |
20150076439 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode. | 03-19-2015 |
20150102399 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction. | 04-16-2015 |
20150206590 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group. | 07-23-2015 |
20150213887 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: first lines; second lines; memory cells; a first and second select gate transistor; and a control circuit. The first lines are arranged with a certain pitch in a first direction perpendicular to a substrate and are extending in a second direction parallel to the substrate. The second lines are arranged with a certain pitch in the second direction, are extending in the first direction, and intersect the plurality of first lines. The memory cells are disposed at intersections of the first lines and the second lines. The first and second select gate transistors each include a first or second channel line that are connected to a lower end or an upper end of the second line and a first or second gate line. The control circuit controls the first and second select gate transistors independently. | 07-30-2015 |
20150236072 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory cell array comprising first wiring lines, second wiring lines extending crossing the first wiring lines, and memory cells at intersections of the first and second wiring lines, the memory cells being stacked perpendicularly to a substrate, each memory cell comprising a variable resistance element; a first select transistor layer comprising a first select transistor operative to select one of the first wiring lines; a second select transistor layer comprising a second select transistor operative to select one of the second wiring lines; and a peripheral circuit layer on the substrate, the peripheral circuit layer comprising a peripheral circuit that controls a voltage applied to one of the memory cells. The first select transistor layer is provided below the memory cell array perpendicularly to the substrate. The second select transistor layer is provided above the memory cell array perpendicularly to the substrate. | 08-20-2015 |
20150243887 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a memory cell array. The memory cell array comprises a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines. The memory cells are stacked in a direction perpendicular to a substrate, and each memory cell comprises a variable resistance element. The semiconductor memory device also includes a select transistor layer comprising a plurality of select transistors, each select transistor being operative to select any one of the first wiring lines or one of the second wiring lines. Two select transistors are connected to two different respective first wiring lines, stacked in a direction perpendicular to the substrate, and configured to share one gate electrode. | 08-27-2015 |
20150262671 | NON-VOLATILE MEMORY DEVICE - A nonvolatile memory device according to an embodiment includes: a semiconductor substrate; a memory cell array unit provided on an upper side of the semiconductor substrate; an integrated circuit unit provided between the memory cell array unit and the semiconductor substrate; and a peripheral circuit unit provided on the semiconductor substrate. The integrated circuit unit includes: a first contact electrode electrically connected to one of plurality of first interconnection layers; a second contact electrode connected to the peripheral circuit unit; and a first switching element connected between the first contact electrode and the second contact electrode, and conduction between the first contact electrode and the second contact electrode being controlled by a control circuit unit provided in the peripheral circuit unit. | 09-17-2015 |
20160043311 | MEMORY DEVICE - According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode. | 02-11-2016 |