Patent application number | Description | Published |
20130329494 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device has memory cell arrays, with the memory cells arranged in a matrix configuration and divided into p areas in the column direction, a column redundancy area arranged in a portion of the memory cell array and having redundancy columns that can substitute for defective user data columns, and a column substituting register that holds the column substituting information for substituting the defective user data columns of the selected area with the redundancy columns. | 12-12-2013 |
20140043913 | NON-VOLATILE SEMICONDUCTOR DEVICE - A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated. | 02-13-2014 |
20140085982 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor. | 03-27-2014 |
20140258614 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array having a plurality of memory cells, each memory cell configured to store plural bits of data, and a controller. The controller is configured to execute a write operation on the memory cells such that user data are written in at least one of the plural bits of data and prescribed data are written in the remaining bits of the plural bits of data. As a result, the number of bits of user data stored in the memory cells is less than the number of plural bits of data that each memory cell is configured to store. | 09-11-2014 |
20140286099 | SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND MEMORY SYSTEM - A semiconductor memory device includes a memory cell array that is capable of storing data in a nonvolatile manner, and a control section that controls data access to the memory cell array. The memory cell array stores the same data redundantly in a plurality of pages. The control section executes a reading operation on the plurality of pages that store the same data redundantly to read the data. The data that is stored redundantly may be management data or user data. | 09-25-2014 |
20140355351 | CONTROLLER - A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update first and second values for each string when read and write operations are carried out on the strings, the first value for a first string being updated when a read or write operation is carried out on a memory cell transistor of the first string and the second value being updated when a read or write operation is carried out on a memory cell transistor of a second string that is different from the first string. | 12-04-2014 |
20150124528 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor. | 05-07-2015 |
20150138883 | NON-VOLATILE SEMICONDUCTOR DEVICE - A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated. | 05-21-2015 |