Patent application number | Description | Published |
20080239796 | MAGNETIC MEMORY DEVICE AND METHOD OF WRITING INTO THE SAME - A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ | 10-02-2008 |
20090059651 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO THE SAME - A method of writing into a semiconductor memory device, which includes a resistance memory element | 03-05-2009 |
20090168495 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO SEMICONDUCTOR MEMORY DEVICE - In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than a reset voltage and less than a set voltage by applying to a gate terminal of the second transistor a voltage which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage. | 07-02-2009 |
20100157655 | RESISTIVE MEMORY AND DATA WRITE-IN METHOD - An ReRAM of the present invention includes a high speed write-in region and a main memory region, only memory cells designated to have the storage state out of the memory cells corresponded to data are set to the storage state in the high speed write-in region. The data written in the memory cell array are transferred to the main memory region, the memory cells of the memory cell array corresponded to the data transferred from the high speed write-in region are reset to the no-storage state in the main memory region, only the memory cells designated to have the storage state out of the memory cells are set, and all memory cells are reset to the no-storage state, or the initial state, in the high speed write-in region. | 06-24-2010 |
20100208515 | MAGNETIC RANDOM ACCESS MEMORY - The spin torque transfer magnetic random access memory includes a magnetic tunnel junction element including a pinned layer, a free layer, and a tunnel insulating film formed between the pinned layer and the free layer, and a memory cell select transistor having one diffused region electrically connected to a side of the fee layer of the magnetic tunnel junction element. | 08-19-2010 |
20110222334 | SPIN TRANSFER TORQUE MRAM, AND WRITE METHOD AND READ METHOD THEREFOR - A method of writing data into a memory cell of spin transfer torque magnetoresistive random access memory includes writing a first data into a first memory cell that includes a first magnetic-tunnel-junction element and a first selection transistor wherein an end of the first memory cell is connected to a first signal line and a different end of the first memory cell is connected to a common signal line during a first period, and writing a second data which is an opposite of the first data into the second memory cell that includes a second magnetic-tunnel-junction element and a second selection transistor wherein an end of the second memory cell is connected to a second signal line and a different end of the second memory cell is connected to the common signal line during a second period following the first period. | 09-15-2011 |
20120087172 | SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line, and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor, and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof. | 04-12-2012 |
20130155761 | MAGNETIC MEMORY DEVICE AND READING METHOD OF MAGNETIC MEMORY DEVICE - A magnetic memory device including a multivalued magnetic memory cell whose electric resistances become first to fourth resistance value when first to fourth information are respectively stored, a first reference cell larger than the first resistance value and smaller than the second resistance value, a second reference cell larger than the second resistance value and smaller than the third resistance value, a third reference cell larger than the third resistance value and smaller than the fourth resistance value, and a read circuit including first to third comparators comparing a signal corresponding to the resistance of the magnetic memory cell and respective signals corresponding to the resistances of the first to third reference cells. | 06-20-2013 |
20130182498 | MAGNETIC MEMORY DEVICE AND DATA WRITING METHOD FOR MAGNETIC MEMORY DEVICE - A magnetic memory device including a plurality of memory cells, each of which stores therein 2 | 07-18-2013 |
20140347919 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source line provided on a first end side; a plurality of bit line switches provided between the plurality of bit lines and the global bit line; a plurality of source line switches provided between the plurality of source lines and the global source line; a column decoder; a row decoder; a plurality of bit line ground switches provided between the plurality of bit lines and a ground line on a second end side; and a plurality of source line ground switches provided between the plurality of source lines and a ground line on the second end side. | 11-27-2014 |