Patent application number | Description | Published |
20080225591 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers. | 09-18-2008 |
20080291743 | SEMICONDUCTOR STORAGE DEVICE - This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node. | 11-27-2008 |
20090161436 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state. | 06-25-2009 |
20090244978 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes. | 10-01-2009 |
20100188913 | SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair. | 07-29-2010 |
20110103152 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes. | 05-05-2011 |
20110205806 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border. | 08-25-2011 |
20110305089 | THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS - According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant. | 12-15-2011 |
20120063234 | MEMORY SYSTEM HAVING NONVOLATILE SEMICONDUCTOR MEMORIES - According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory. | 03-15-2012 |
20120250409 | SEMICONDUCTOR MEMORY AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal. | 10-04-2012 |
20120250411 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write. | 10-04-2012 |
20120250424 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer. | 10-04-2012 |
20120250425 | SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY CONTROL METHOD - According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches. | 10-04-2012 |
20140241072 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array. The second latch circuit temporarily holds a control signal. A control circuit controls the memory cell array, the first latch circuit and the second latch circuit. The control circuit limits an operation of the first latch circuit in a state after an operation on the memory cell array has been finished, and limits an operation of the second latch circuit based on a command supplied from external. | 08-28-2014 |
20150071006 | SEMICONDUCTOR STORAGE DEVICE - The semiconductor storage device of the embodiment includes memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A sense amplifier unit is connected to the bit lines. A data write operation includes a first write loop and a second write loop. The first write loop includes a first program operation and a first verify operation. The second write loop includes a second program operation and a second verify operation. A maximum value of a consumed current in the first verify operation is substantially equal to a maximum value of the consumed current in the second verify operation. The consumed current in the first verify operation is substantially same as the consumed current in the second verify operation if data input in the data write operation is all equal to first data corresponding to an erasure state. | 03-12-2015 |
Patent application number | Description | Published |
20100309733 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory. | 12-09-2010 |
20130314990 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, the control circuit applies a pass potential to a first word line and a preliminary read-out potential to a second word line. The control circuit reads the data from the first memory cell transistor at a first condition when the second memory cell transistor has been switched to the ON state and at a second condition when the second memory cell transistor has been switched to an OFF state, by the applying of the preliminary read-out potential. The first condition enables the discrimination of the value of the first memory cell transistor in the case where a threshold distribution of the first memory cell transistor is relatively low. The second condition enables the discrimination of the value of the first memory cell transistor in the case where the threshold distribution of the first memory cell transistor is relatively high. | 11-28-2013 |
20130343124 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD FOR SAME - According to one embodiment, a control circuit is configured to perform a first read operation and a second read operation. The control circuit is configured to perform the plurality of first sense operations when applying a first reading voltage to the word line in the first read operation. The control circuit is configured to perform a second sense operation when applying a second reading voltage to the word line in the second read operation. The control circuit is configured to select one of informations read out by the plurality of sense operations based on data stored in adjacent memory cells. | 12-26-2013 |
20140003154 | SEMICONDUCTOR MEMORY DEVICE | 01-02-2014 |
20140269097 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a sense amplifier. The memory cell array includes a plurality of memory cell transistors. The sense amplifier reads data held in the memory cell transistors. The sense amplifier writes data to the memory cell transistors. The sense amplifier includes a first sense unit, a first operational unit, a second sense unit, and a second operational unit. The first sense unit includes a first sub-amplifier group and a first switch group. The second sense unit includes a second sub-amplifier group and a second switch group. The first sub-amplifier group is electrically connected to a first data bus. The second sub-amplifier group is electrically connected to a second data bus. The first operational unit is electrically connected to the first data bus and the second data bus. | 09-18-2014 |
20140286093 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a NAND string and a sense amplifier. The NAND string includes a memory cell transistor to be capable of holding any of three or more levels of values. The NAND string includes one end connected to a bit line and the other end connected to a source line. The sense amplifier connects the bit line. A first voltage is applied to the source line when a first read voltage is applied to a selected word line connected to a selected memory cell transistor. A second voltage is applied to the source line when a second read voltage is applied to the selected word line. The first voltage is higher than the second voltage. The first read voltage is the lowest voltage of a plurality of read voltage. The second read voltage is higher than the first read voltage. | 09-25-2014 |