Patent application number | Description | Published |
20130141165 | PERFORMANCE OF OFF-CHIP CONNECTION FOR POWER AMPLIFIER - There is provided an integrated circuit comprising a main push-pull amplifier ( | 06-06-2013 |
20130193943 | SWITCHED ARRANGEMENT FOR SWITCHED MODE SUPPLY - There is disclosed a switching stage comprising: a first switching path having at least one switching element for selectively connecting an input of the switching stage to an output of the switching stage; and a second switching path having at least one switching element for selectively connecting the input of the switching stage to the output of the switching stage, wherein the first and second switching paths are controlled such that a signal is selectively routed from the input of the switching stage to the output of the switching stage via the first and second switching paths in dependence on the current of the signal to be routed. | 08-01-2013 |
20130200949 | TIMING ALIGNMENT FOR MODULATED SUPPLY - There is disclosed a method, in an amplifier stage comprising an amplifier and a modulated supply, the amplifier being arranged to amplify an input signal and the modulated supply being arranged to generate a supply voltage for the amplifier by tracking an envelope of the signal to be amplified, the method comprising: comparing the relative timing of a signal representing the current drawn by the amplifier from the modulated supply and a signal representing the voltage generated at the output of the modulated supply; and in dependence upon a difference in the relative timing, adjusting the timing of either the input signal to be amplified or the generated supply voltage to reduce the difference in the relative timing. | 08-08-2013 |
20130207724 | CROSSOVER PERFORMANCE OF POWER AMPLIFIER - There is provided an amplifier arrangement comprising a main push pull amplifier ( | 08-15-2013 |
20130293205 | Control of cross-over point - There is provided an output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; and a combiner for combining the first and second output signals to generate a phase combined output signal. | 11-07-2013 |
20140022012 | INTERFERENCE SUPPRESSION FOR SWITCHED MODE POWER SUPPLY - The invention relates to a switched mode power supply comprising at least one switch and at least one inductor, the at least one switch being arranged to connect one terminal of the at least one inductor to one of a plurality of supply voltages, the other terminal of the at least one inductor providing a supply output, and further comprising a capacitor connected in parallel with the at least one inductor. | 01-23-2014 |
20140077881 | Power Amplifier with Stabilising Network - A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies. | 03-20-2014 |
20150200594 | Control of Multi-Level Supply Stage - A buck-boost converter comprising: a voltage source; an inductor, wherein a first terminal of the inductor is switchably connected to the voltage source; and a plurality of capacitors switchably connected to a second terminal of the inductor, wherein a respective plurality of output voltages are formed across the plurality of capacitors, further comprising: an error determination means, for determining an error in each of the plurality of voltages, an inner control loop adapted to switchably connect one of the plurality of capacitors to the second terminal of the inductor in dependence on the determined errors; and an outer control loop adapted to control switching between buck mode and boost mode in dependence upon the determined errors. | 07-16-2015 |