Patent application number | Description | Published |
20100161914 | AUTONOMOUS MEMORY SUBSYSTEMS IN COMPUTING PLATFORMS - Embodiments of the invention are generally directed to systems, methods, and apparatuses for autonomous memory subsystems in computing platforms. In some embodiments, the autonomous memory mechanism includes one or more autonomous memory logic instances (AMLs) and a transaction protocol to control the AMLs. The autonomous memory mechanism can be employed to accelerate bulk memory operations. Other embodiments are described and claimed. | 06-24-2010 |
20100318718 | MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE - A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. | 12-16-2010 |
20100332895 | NON-VOLATILE MEMORY TO STORE MEMORY REMAP INFORMATION - Subject matter disclosed herein relates to remapping memory devices. | 12-30-2010 |
20110066796 | AUTONOMOUS SUBSYSTEM ARCHITECTURE - An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance. | 03-17-2011 |
20110067039 | AUTONOMOUS MEMORY ARCHITECTURE - An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller. | 03-17-2011 |
20110167197 | Nonvolatile Storage with Disparate Memory Types - Disparate nonvolatile memory types are included in a system. Writes are performed in a first type of nonvolatile memory when the size of the write is below a threshold, and are performed in a second type of nonvolatile memory when the size of the write is above the threshold. The threshold may be a number of sectors. The disparate memory types may include FLASH memory and phase change memory (PCM). | 07-07-2011 |
20130305123 | SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE - Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die. | 11-14-2013 |
20140337688 | SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE - Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die. | 11-13-2014 |
20150081998 | BLOCK-BASED STORAGE DEVICE WITH A MEMORY-MAPPED INTERFACE - Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array. | 03-19-2015 |