Patent application number | Description | Published |
20110148501 | VARIABLE ATTENUATOR HAVING STACKED TRANSISTORS - In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator. | 06-23-2011 |
20110148502 | TEMPERATURE COMPENSATION ATTENUATOR - In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change. | 06-23-2011 |
20110148503 | TEMPERATURE CONTROLLED ATTENUATOR - In one embodiment, a temperature controlled attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. Furthermore, the temperature controlled attenuator includes a temperature controlled circuit that adjusts the attenuation level of the attenuation circuit in accordance to an operating temperature. In this manner, the attenuation level of the temperature controlled attenuator is temperature dependent. | 06-23-2011 |
20110260773 | HIGH POWER FET SWITCH - Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state. | 10-27-2011 |
20110260774 | HIGH POWER FET SWITCH - Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path and a second decoupling path are provided for the first FET device and the last FET device in the FET device stack. Both decoupling paths are configured to pass a time-variant input signal during the open state. The first decoupling path may be coupled from the drain contact of the first FET device to the gate contact or the source contact. The second decoupling path may be coupled from the source contact of the last FET device to the gate contact or drain contact. The time-variant input signal bypasses the FET device stack through the first and second decoupling paths during the open state. | 10-27-2011 |
20110260780 | HIGH POWER FET SWITCH - Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. A control circuit provides biasing voltages to the gate, source, and drain contacts of each of the plurality of FET devices to switch the FET device stack to and from a closed state and an open state. In the open state, the gate contacts of each of the plurality of FET devices are biased by the control circuit at the second voltage. To prevent activation in the open state, the control circuit biases the drain contacts and source contacts of each of the plurality of FET devices at the first voltage. The first voltage is positive relative to a reference voltage, such as ground, while the second voltage is non-negative relative to the reference voltage but less than the first voltage. | 10-27-2011 |
20120094623 | BROADBAND RECEIVE ONLY TUNER COMBINED WITH RECEIVE SWITCH - An antenna tuner unit (ATU) that provides broadband tuning is disclosed. The disclosed ATU includes a radio frequency (RF) switch circuit having an N number of switch inputs, wherein N is a natural number equal to 2 or greater. An N number of reactance elements are coupled in series between an RF input and one of the N number of switch inputs. Taps between adjacent pairs of the N number of reactance elements, wherein each of the taps is coupled to a corresponding one of the N number of switch inputs. The ATU further includes a capacitive element for each of the taps, wherein each capacitive element is coupled between a corresponding one of the taps and a voltage node. In at least one embodiment, each of the capacitive elements is made up of a programmable capacitor array. | 04-19-2012 |
20120201172 | FEMTOCELL TUNABLE RECEIVER FILTERING SYSTEM - A tunable receiver system uses programmable notch filters to identify available channel pairs for transmitting and receiving data via a femtocell base station. In addition, one of the programmable notch filters may be used to suppress infiltration of the transmit path signal into the receiver path of the receiver device. The other programmable notch filter may be used to suppress a blocker signal identified by the receiver device. | 08-09-2012 |
20120235750 | AMPLIFICATION DEVICE HAVING COMPENSATION FOR A LOCAL THERMAL MEMORY EFFECT - In one embodiment, an amplification device has a temperature differential sensing circuit that reduces a local thermal memory effect. The amplification device may include an amplification circuit and biasing circuitry. The amplification device is operable to receive an input signal and generate and amplified output signal. The biasing circuitry generates a biasing signal that sets the quiescent operating level of the amplified output signal. The temperature differential sensing circuit provides a bias level adjustment signal that adjusts the biasing signal to maintain the quiescent operating level of the amplified output signal at a desired level. | 09-20-2012 |
20120256702 | TUNABLE DUPLEXER METHOD USING HYBRID TRANSFORMER WITH DUAL ANTENNA - The present disclosure relates to a hybrid transformer duplexer apparatus. The hybrid transformer duplexer apparatus includes an autotransformer having a first port, a second port and a tap coupled to a first antenna port. A step-down transformer has a primary winding with a first terminal coupled to the first port of the autotransformer and a second terminal coupled to the second port of the autotransformer, and a secondary winding having a third terminal coupled to a second antenna port and a fourth terminal coupled to a common node. | 10-11-2012 |
20120280738 | VARIABLE ATTENUATOR HAVING STACKED TRANSISTORS - In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator. | 11-08-2012 |
20130043962 | DIGITAL STEP ATTENUATOR UTILIZING THERMOMETER ENCODED MULTI-BIT ATTENUATOR STAGES - A digital step attenuator with thermometer encoded attenuator stages is disclosed. In one embodiment, Embodiments disclosed in the detailed description may include a digital step attenuator, programmable thermometer encoded attenuator stages, the digital step attenuator may include a cascade of programmable thermometer encoded attenuator stages. Each stage may be provided by a programmable impedance array including a plurality of impedances arranged in parallel. The impedance of each of the plurality of each stage may change monotonically by switchably inserting or removing one of the plurality of impedances in the arrays. The control circuit may govern the attenuation level of each of the thermometer encoded accumulator stages as a function of a thermometric codeword, which controls the switches in the arrays. | 02-21-2013 |
20130083703 | TUNABLE DUPLEXER ARCHITECTURE - A tunable radio frequency (RF) duplexer and duplexing methods are disclosed. The tunable RF duplexer includes a first hybrid coupler, a second hybrid coupler, and an RF filter circuit. The first hybrid coupler is operable to split the RF transmission input signal into first and second RF quadrature hybrid transmission signals (QHTSs). The second hybrid coupler is operable to split the RF receive input signal into first and second RF quadrature hybrid receive signals (QHRSs). The RF filter circuit is operable to pass the first and second RF QHTSs to the second hybrid coupler and to reflect the first and second RF QHRSs back to the second hybrid coupler. Additionally, the second hybrid coupler is configured to combine the first and second RF QHTSs into an RF transmission output signal and to combine the first and second RF QHRSs into an RF receive output signal. | 04-04-2013 |
20130113300 | COMBINED BALUN TRANSFORMER AND HARMONIC FILTER - In one embodiment, a balanced to unbalanced transformer utilizes a crossover configuration such that some portion of the secondary coil (inductor) is shared between two resonators (capacitors). Adding a first capacitor in parallel with a portion of the secondary inductor creates a first harmonic trap (filter), and also efficiently uses the secondary coil (inductor) as a resonating element. | 05-09-2013 |
20130127513 | TEMPERATURE COMPENSATION ATTENUATOR - In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change. | 05-23-2013 |
20130201880 | TUNABLE DUPLEXER ARCHITECTURE - A tunable radio frequency (RF) duplexer is disclosed. The tunable RF duplexer includes a first hybrid coupler, a second hybrid coupler, and an RF filter circuit. The first hybrid coupler is operable to split an RF receive input signal into first and second RF quadrature hybrid receive signals (QHRSs). The first hybrid coupler is also operable to split an RF transmission input signal into first and second RF quadrature hybrid transmission signals (QHTSs). The RF filter circuit is operable to pass the first and second RF QHRSs to the second hybrid coupler and to reflect the first and second RF QHTSs back to the first hybrid coupler. Additionally, the second hybrid coupler is configured to combine the first and second RF QHRSs into an RF receive output signal, while the first hybrid coupler is configured to combine the first and second RF QHTSs into an RF transmission output signal. | 08-08-2013 |
20130201881 | RF TRANSCEIVER WITH DISTRIBUTED FILTERING TOPOLOGY - This disclosure includes embodiments of a radio frequency (RF) transceiver having a distributed duplex filtering topology. The RF transceiver includes a power amplifier and a tunable RF duplexer. The tunable RF duplexer is configured to input an RF transmission input signal from the power amplifier, generate an RF transmission output signal that operates within an RF transmission band in response to the RF transmission input signal from the power amplifier, and simultaneously output the RF transmission output signal to an antenna and input an RF receive input signal that operates within an RF receive band from the antenna. The power amplifier includes a plurality of RF amplifier stages coupled in cascode and an RF filter coupled between a first one of the RF amplifier stages and a second one of the RF amplifier stages. Accordingly, the RF filter is configured to provide tuning within the RF receive band. | 08-08-2013 |
20130201882 | TUNABLE HYBRID COUPLER - This disclosure includes embodiments of a tunable hybrid coupler. The tunable hybrid coupler includes a first inductive element having a first inductance, a second inductive element having a second inductance and mutually coupled to the first inductive element, a first variable capacitive element having a first variable capacitance, and a second variable capacitance having a second variable capacitance. The first variable capacitive element is coupled between a first port and a second port. The second variable capacitive element is coupled between a third port and a fourth port. The first inductive element is coupled from the first port to the third port, while the second inductive element is coupled from the second port to the fourth port. Accordingly, the tunable hybrid coupler may form an impedance matching network that is tunable to different RF communication bands. The tunable hybrid coupler may thus be included in a tunable RF duplexer. | 08-08-2013 |
20130241666 | BAND SWITCH WITH SWITCHABLE NOTCH FOR RECEIVE CARRIER AGGREGATION - A band switch with a switchable notch for receive carrier aggregation is disclosed. The band switch has at least one input and an output with at least one series switch coupled between the at least one input and the output. The at least one series switch is adapted to selectively couple the input to the output in response to a first control signal. The band switch also includes at least one shunt switch coupled between the at least one input and a voltage node. The at least one shunt switch is adapted to selectively couple the at least one input to the voltage node in response to a second control signal. In addition, at least one notch filter is selectively coupled to the output in a shunt configuration, wherein the at least one notch filter is configured to attenuate signals within a stop band to attenuate harmonics and distortion. | 09-19-2013 |
20130249619 | SOI SWITCH ENHANCEMENT - The described FET switch topology greatly reduces the off state loading experienced by the gate biasing resistors in a stacked FET structure. The FET switch topology evenly distributes the voltage across the FET switch topology which reduces the voltage across the gate biasing resistors when the stacked FET structure is in an off state. Because the off state loading is reduced, there is a corresponding reduction of the current through bias resistors, which permits a reduction in the size of the bias resistors. This permits a substantial reduction in the area attributed to the bias resistors in an integrated solution. | 09-26-2013 |
20130250819 | CARRIER AGGREGATION FRONT END ARCHITECTURE - Radio frequency (RF) front end circuitry includes a notch diplexer. The notch diplexer includes a high pass filter coupled between a high band port and an antenna port, and a low pass notch filter coupled between a low band port and the antenna port. The high pass filter is adapted to receive a high band receive signal having a high band carrier frequency at the antenna port, and pass the high band receive signal to the high band port. The low pass notch filter is adapted to receive a low band transmit signal having a low band carrier frequency at the low band port, and attenuate distortion in the low band transmit signal about a notch stop band before passing the low band transmit signal to the antenna port. According to one embodiment, the notch stop band includes the high band carrier frequency. | 09-26-2013 |
20130278317 | SWITCHABLE CAPACITIVE ELEMENTS FOR PROGRAMMABLE CAPACITOR ARRAYS - Switchable capacitive elements are disclosed, along with programmable capacitor arrays (PCAs). One embodiment of the switchable capacitive element includes a field effect transistor (FET) device stack, a first capacitor, and a second capacitor. The FET device stack is operable in an open state and in a closed state and has a plurality of FET devices coupled in series to form the FET device stack. The first capacitor and the second capacitor are both coupled in series with the FET device stack. However, the first capacitor is coupled to a first end of the FET device stack while the second capacitor is coupled to a second end opposite the first end of the FET device stack. In this manner, the switchable capacitive element can be operated without a negative charge pump, with decreased bias swings, and with a better power performance. | 10-24-2013 |
20130285763 | HYBRID COUPLER - This disclosure relates to hybrid couplers for radio frequency (RF) signals. The hybrid coupler includes a first port, a second port, a third port, a fourth port, a first inductive element connected from the first port to the third port, and a second inductive element connected from the second port to the fourth port. The hybrid coupler further includes a first capacitive element and a second capacitive element. The first capacitive element is connected between an intermediary node of the first inductive element and either the first port or the third port, while the second capacitive element is coupled between an intermediary node of the second inductive element and either the second port or the fourth port. Accordingly, the first capacitive element and a portion of the first inductive element and the second capacitive element and a portion of the second capacitive element each form a harmonic trap. | 10-31-2013 |
20130321097 | VSWR TOLERANT TUNABLE HYBRID DUPLEXER - The disclosure describes a dual hybrid duplexer including two hybrid couplers, two intra-filters, a tunable isolation load, and a phase shifter. The phase shifter may be located at the isolation port. The phase shifter may be located at the antenna port. In one embodiment, a dual hybrid duplexer includes two hybrid couplers, two intra-filters, a tunable isolation load, a first phase shifter located at the isolation port, and a second phase shifter located at the antenna port. The first and second phase shifters have a difference of 90 degrees (plus or minus 10 degrees). | 12-05-2013 |
20130336181 | DUAL ANTENNA INTEGRATED CARRIER AGGREGATION FRONT END SOLUTION - Radio frequency front end circuitry comprises a first antenna port, a second antenna port, antenna switching circuitry, a first diplexer, and a second diplexer. The antenna switching circuitry is coupled to each of the first antenna port and the second antenna port through the first diplexer and the second diplexer, respectively. The antenna switching circuitry is adapted to selectively couple one or more of a plurality of transmit and receive ports to the first antenna port and the second antenna port. | 12-19-2013 |
20140092795 | TUNABLE DIPLEXER FOR CARRIER AGGREGATION APPLICATIONS - A tunable diplexer includes a high pass filter, a low pass filter, a high band port, a low band port, and an antenna port. The high pass filter is adapted to pass high band signals falling within a high pass band between the high band port and the antenna port, while attenuating signals outside of the high pass band. The low pass filter is adapted to pass low band signals falling within a low pass band between the low band port and the antenna port, while attenuating signals outside of the low pass band. The low pass filter includes a low stop band zero, which is adapted to attenuate signals within a low stop band. The low stop band zero is tunable, such that the low stop band can be adjusted to selectively attenuate signals within a given frequency band in the low pass band. | 04-03-2014 |
20140169243 | MOBILE COMMUNICATION CIRCUITRY FOR THREE OR MORE ANTENNAS - Communication circuitry is disclosed that is capable of switching between three or more antennas while providing low harmonic interference during carrier aggregation. In one embodiment, a communication system includes a first switch with two poles and four throws, a second switch with two poles and four throws, and four diplexers associated with four antennas. In a second embodiment, the communication system includes a first switch with three poles and three throws, a second switch with three poles and three throws, and three diplexers associated with three antennas. In the second embodiment, the second switch may have a third pole associated with non-cellular signals such as GPS and WiFi, and one or more of the diplexers may be tunable, for example to efficiently pass 1.575 GHz for GPS signals. | 06-19-2014 |
20140328220 | CARRIER AGGREGATION ARRANGEMENTS FOR MOBILE DEVICES - Front end circuitry for a wireless communication system includes a first antenna node, a second antenna node, a first triplexer, a second triplexer, and front end switching circuitry coupled between the first triplexer, the second triplexer, the first antenna node, and the second antenna node. The front end switching circuitry is configured to selectively couple the first triplexer to one of the first antenna node and the second antenna node and couple the second triplexer to a different one of the first antenna node and the second antenna node. By using a first triplexer and a second triplexer in the mobile front end circuitry, the mobile front end circuitry may operate in one or more carrier aggregation configurations while reducing the maximum load presented to the first antenna node and the second antenna node, thereby improving the performance of the front end circuitry. | 11-06-2014 |
20140334362 | TUNABLE DIPLEXER - A tunable diplexer includes a high band port, a low band port, an antenna port, a high pass filter, and a low pass filter. The high pass filter is coupled between the high band port and the antenna port, and is configured to pass signals within a high pass band between the high band port and the antenna port. The high pass filter includes a high band path stop band zero, which is configured to selectively attenuate signals within a high band path stop band. The low pass filter is coupled between the low band port and the antenna port, and is configured to pass signals within a low pass band between the low band port and the antenna port. The low pass filter includes a low band path stop band zero, which is configured to selectively attenuate signals within a low band path stop band. | 11-13-2014 |
20140335801 | TECHNIQUE TO REDUCE THE THIRD HARMONIC OF AN ON-STATE RF SWITCH - RF switching circuitry includes an RF switch coupled between an input node and an output node. Distortion compensation circuitry is coupled in parallel with the RF switch between the input node and the output node. The RF switch is configured to selectively pass an RF signal from the input node to the output node based on a first switching control signal. The distortion compensation circuitry is configured to boost a portion of the RF signal that is being compressed by the RF switch when the amplitude of the RF signal is above a predetermined threshold by selectively injecting current into one of the input node or the output node. Boosting a portion of the RF signal that is being compressed by the RF switch allows a signal passing through the RF switch to remain substantially linear, thereby improving the performance of the RF switching circuitry. | 11-13-2014 |