Patent application number | Description | Published |
20080246504 | APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR MEMORY TESTING WITH SERIAL INTERFACE - A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers. | 10-09-2008 |
20080250191 | FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY - A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface. | 10-09-2008 |
20080310232 | ERASE VERIFY FOR MEMORY DEVICES - Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation. | 12-18-2008 |
20100074030 | ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE - An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node. | 03-25-2010 |
20120287723 | METHOD AND CIRCUIT TO DISCHARGE BIT LINES AFTER AN ERASE PULSE - Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path. | 11-15-2012 |
20130069715 | PSRR IN A VOLTAGE REFERENCE CIRCUIT - Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node. | 03-21-2013 |
20130193590 | SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad. | 08-01-2013 |
20130223152 | CLOCK GENERATOR - A clock generator or oscillating circuit is provided to generate a clock signal with high Power Supply Rejection Ratio (PSSR), or a stable clock signal that is resistant to variations in the power supply. The clock generator or oscillating circuit may also adjust the clock period (T) of the clock signal, either or both upwards and downwards, around its central value to compensate fabrication process variations. | 08-29-2013 |