Patent application number | Description | Published |
20140077380 | BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge. | 03-20-2014 |
20140097892 | DOUBLE PATTERNING COMPATIBLE COLORLESS M1 ROUTE - A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone. | 04-10-2014 |
20140131816 | CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES - An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a gate cut region across the first gate structure, the second gate structure, or a combination thereof; providing a first gate contact over the first gate structure; providing a second gate contact over the second gate structure; and providing a diffusion contact structure coupling the first gate contact to the second gate contact, the diffusion contact structure having vertices within the gate cut region. | 05-15-2014 |
20140183638 | METHODS OF USING A TRENCH SALICIDE ROUTING LAYER - Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure. | 07-03-2014 |
20140258960 | INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS - An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system. | 09-11-2014 |
20140282323 | PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN - A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions. | 09-18-2014 |
20140327146 | METHODS FOR IMPROVING DOUBLE PATTERNING ROUTE EFFICIENCY - A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs. | 11-06-2014 |
20140327153 | STANDARD CELL CONNECTION FOR CIRCUIT ROUTING - Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M | 11-06-2014 |
20140332967 | BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES - An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge. | 11-13-2014 |
20140339610 | FINFET DEVICE AND METHOD OF FABRICATION - Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency. | 11-20-2014 |
20140339647 | DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME - One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively | 11-20-2014 |
20140346662 | FORMING MODIFIED CELL ARCHITECTURE FOR FINFET TECHNOLOGY AND RESULTING DEVICE - Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder. | 11-27-2014 |
20140353842 | WIDE PIN FOR IMPROVED CIRCUIT ROUTING - Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size. | 12-04-2014 |
20150052494 | POWER RAIL LAYOUT FOR DENSE STANDARD CELL LIBRARY - A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area. | 02-19-2015 |