Patent application number | Description | Published |
20140320205 | AUTOTRANSFORMER-BASED IMPEDANCE MATCHING CIRCUITS AND METHODS FOR RADIO-FREQUENCY APPLICATIONS - Disclosed are devices and methods related to autotransformer-based impedance matching for radio-frequency (RF) applications. In some embodiments, an impedance matching device can include a primary metal trace and a secondary metal trace, each having a respective number of turns. Such metal traces can be interconnected to form an autotransformer with the primary metal trace and the secondary metal trace being in respective planes separated by a selected distance. Such an autotransformer can be utilized to, for example, facilitate impedance matching of an amplified RF signal from a power amplifier (PA). In some embodiments, the impedance matching device can be implemented as an integrated passive device (IPD) mountable on a packaging substrate. Such an IPD can be configured to allow stacking of another component on the IPD to yield a number of desirable features in products such as RF modules. | 10-30-2014 |
20140320252 | LOW LOSS IMPEDANCE TRANSFORMERS IMPLEMENTED AS INTEGRATED PASSIVE DEVICES AND RELATED METHODS THEREOF - Disclosed are apparatus and methods related to low loss impedance transformers implemented as integrated passive devices (IPDs). In some embodiments, an IPD can include an autotransformer implemented within a body. The autotransformer can include primary and secondary metal traces implemented in respective planes separated by a distance. The autotransformer can be configured to, for example, facilitate impedance matching of radio-frequency (RF) signals. In some embodiments, the IPD can include a surface that allows mounting of one or more components thereon to provide space savings in RF modules. Examples of fabrication methods as well as products that can benefit from such IPDs are disclosed. | 10-30-2014 |
20150303971 | SYSTEMS, DEVICES AND METHODS RELATED TO IMPROVED RADIO-FREQUENCY MODULES - Systems, devices and methods related to improved radio-frequency (RF) modules. In some embodiments, an RF module can include a packaging substrate, a power amplifier (PA) assembly implemented on a first die mounted on the packaging substrate, and a controller circuit implemented on a second die mounted on the first die. The controller circuit can be configured to provide at least some control of the PA assembly. The RF module can further include one or more output matching network (OMN) devices mounted on the packaging substrate and configured to provide output matching functionality for the PA assembly. The RF module can further include a band selection switch device mounted on each OMN device. | 10-22-2015 |
20150365112 | BAND-GAP REFERENCE CIRCUIT FOR BIASING AN RF DEVICE - A voltage reference circuit implemented in GaAs to provide an output voltage component proportional to absolute temperature is described herein. The various embodiments of the voltage reference circuit described here can be used to provide precision voltage to bias a RF device. The voltage reference circuit can be provided on the same die as the RF device. The various embodiments described herein can be implemented in a GaAs material system. | 12-17-2015 |
Patent application number | Description | Published |
20090187873 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist. | 07-23-2009 |
20110258587 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist. | 10-20-2011 |
20120278783 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path. | 11-01-2012 |
Patent application number | Description | Published |
20110033037 | ADAPTIVE FILTERING WITH FLEXIBLE SELECTION OF ALGORITHM COMPLEXITY AND PERFORMANCE - An adaptive filter configured to use multiple algorithm species that differ in the quality of echo suppression and respective burdens imposed on the computational resources of the host communication device. Depending on the available computational budget, the adaptive filter selects an algorithm species that, while supporting a relatively high quality of echo suppression, involves a relatively low risk of overwhelming the computational resources. The adaptive filter monitors changes in the available computational budget and, if appropriate or necessary, can change the algorithm species to maintain a quality of echo suppression that is optimal for the current computational budget. If a change of the algorithm species is initiated, then at least a portion of internal algorithm data from the previously running algorithm species might be transferred for use in the subsequent algorithm species. | 02-10-2011 |
20110200147 | HIGH-PERFORMANCE TONE DETECTION USING A DIGITAL SIGNAL PROCESSOR (DSP) HAVING MULTIPLE ARITHMETIC LOGIC UNITS (ALUS) - In one embodiment, a DSP having four arithmetic logic units (ALUs) and able to have two read/write operations per clock cycle performs silence detection and tone detection for data frames containing samples of an audio signal. The ALUs are used together in parallel to process the samples in the data frames received by the DSP. A received data frame is filtered by the silence detection so that substantially silent frames are dropped and non-silent frames are further processed. In the tone detection, a filtered data frame is processed, four samples at a time, to determine the power of the signal at a given frequency, where the power determination is used to determine whether a given tone (i.e., a signal at a given frequency) is present in the data frame. | 08-18-2011 |
20120166773 | HASH PROCESSING USING A PROCESSOR - In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M | 06-28-2012 |
Patent application number | Description | Published |
20090326880 | Parallel physics solver - A parallel physics solver may solve an equation to determine the characteristics of motion after a collision. In some embodiments, the physics solver solves the equation AX=B, where A is a sparse constrained matrix and B is the right hand vector. The sparse constrained matrix may be formed of 6×K blocks, where K is a tuning parameter that divides into the width of a single instruction multiple data processor used to implement the physics solver, without residue. | 12-31-2009 |
20090326888 | Vectorized parallel collision detection pipeline - A parallel collision detection pipeline may perform a physics simulation using multicore processors. Potentially colliding objects may be grouped based on object type in a narrow phase collision detection phase. Parallel spatial hashing may be used in the broad phase collision detection in some embodiments. | 12-31-2009 |
20140025717 | SIMD INTEGER ADDITION INCLUDING MATHEMATICAL OPERATION ON MASKS - Methods, apparatuses, and articles associated with SIMD adding two integers are disclosed. In embodiments, a method may include element-wise SIMD adding corresponding elements of a first SIMD-sized integer (A) and a second SIMD-sized integer (B) to generate a SIMD-sized integer result (R) and a carry bit. A may have an integer size (SizeA), while B may have an integer size (SizeB). The addition, in response to SizeA greater than SizeB, may further include updating R and the carry bit in view of one or more elements of A that do not have corresponding element or elements of B. Further, element-wise SIMD adding may include performing one or more mathematical operations on first one or more masks, with the first one or more masks interpreted as integers, and interpreting one or more integer results of the one or more mathematical operations as second one or more masks. | 01-23-2014 |