Patent application number | Description | Published |
20090323392 | SMART DETECTION CIRCUIT FOR WRITING TO NON-VOLATILE STORAGE - A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. | 12-31-2009 |
20090323393 | CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY - A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells. | 12-31-2009 |
20110019495 | DECODER CIRCUITRY PROVIDING FORWARD AND REVERSE MODES OF MEMORY ARRAY OPERATION AND METHOD FOR BIASING SAME - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 01-27-2011 |
20110096588 | NON-VOLATILE MEMORY ARRAY ARCHITECTURE INCORPORATING 1T-1R NEAR 4F2 MEMORY CELL - A nonvolatile memory array architecture includes a resistive element between each common source/drain (intermediate) node and data line (or bit line), in an otherwise virtual ground-like memory array having serially-connected transistors coupled to the same word line. However, every N+1 transistors the corresponding resistive element is omitted (or generally kept in a low resistance state) to form transistor strings. This achieves an array density of 4F | 04-28-2011 |
20120008373 | CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY - A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells. | 01-12-2012 |
20120224409 | THREE DIMENSIONAL MEMORY SYSTEM WITH PAGE OF DATA ACROSS WORD LINES - A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit. | 09-06-2012 |
Patent application number | Description | Published |
20080238522 | METHOD FOR INCORPORATING TRANSISTOR SNAP-BACK PROTECTION IN A LEVEL SHIFTER CIRCUIT - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail. | 10-02-2008 |
20080238523 | LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION - Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail. | 10-02-2008 |
20080238541 | SPATIALLY DISTRIBUTED AMPLIFIER CIRCUIT - An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array. | 10-02-2008 |
20080239839 | METHOD FOR USING A SPATIALLY DISTRIBUTED AMPLIFIER CIRCUIT - An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array. | 10-02-2008 |
20080247213 | Memory Device for Protecting Memory Cells during Programming - Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card. | 10-09-2008 |
20090161474 | REVERSIBLE-POLARITY DECODER CIRCUIT AND METHOD - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 06-25-2009 |
20110299354 | MEMORY ARRAY CIRCUIT INCORPORATING MULTIPLE ARRAY BLOCK SELECTION AND RELATED METHOD - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 12-08-2011 |