Liyang
Liyang Lai, Wilsonville, OR US
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20080235544 | Built-in self-test of integrated circuits using selectable weighting of test patterns - A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains. | 09-25-2008 |
20110191643 | Detection And Diagnosis Of Scan Cell Internal Defects - A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models. | 08-04-2011 |
20120210184 | Compound Hold-Time Fault Diagnosis - Aspects of the invention relate to techniques for diagnosing compound hold-time faults. A profiling-based scan chain diagnosis may be performed on a faulty scan chain to determine observed scan cell failing probability information and one or more faulty segments based on scan pattern test information. Calculated scan cell failing probability information may then be derived. Based on the calculated scan cell failing probability information and the observed scan cell failing probability information, one or more validated faulty segments are verified to have one or more compound hold-time faults. Finally, one or more clock defect suspects may be identified based on information of the one or more validated faulty segments. | 08-16-2012 |
20120233512 | Two-Dimensional Scan Architecture - Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined. | 09-13-2012 |
20130166976 | Diagnosis-Aware Scan Chain Stitching - Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design. | 06-27-2013 |
20140237310 | Test Architecture for Characterizing Interconnects in Stacked Designs - Aspects of the invention relate to ring-oscillator-based test architecture for characterizing interconnects in stacked designs. The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by control circuitry. | 08-21-2014 |
Liyang Wang, Shenzhen CN
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20090240804 | METHOD AND APPARATUS FOR PREVENTING IGMP PACKET ATTACK - A method for preventing IGMP packet attacks includes two levels of anti-attack steps: anti-attacking on the basis of the source IP address of an IGMP packet; and anti-attacking on the basis of the multicast group IP address of the IGMP packet. Moreover, an apparatus for preventing IGMP packet attacks is disclosed herein. In the embodiments of the present disclosure, the attacks are prevented hierarchically in light of the source address and multicast group IP of the IGMP packet, thus effectively solving network exceptions caused by malicious IGMP packets which surge in a short time. | 09-24-2009 |
20090268607 | METHOD AND DEVICE FOR MULTICAST TRAFFIC REDUNDANCY PROTECTION - A method and apparatus of multicast traffic redundancy protection is provided. After a fault occurs, the VRRP selects a new active router and notifies the PIM routing protocol, and the PIM uses the new active router as its DR. | 10-29-2009 |
Liyang Zhang, West Hills, CA US
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20090302830 | INTEGRATED POWER DETECTOR WITH TEMPERATURE COMPENSATION FOR FULLY-CLOSED LOOP CONTROL - An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal. | 12-10-2009 |
20100271136 | Digital Control Interface In Heterogeneous Multi-Chip Module - A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process. The second functional block may be a power amplifier formed by a heterojunction bipolar transistor process. In another aspect, the first functional block may be a power amplifier formed by a heterojunction bipolar transistor process. The second functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process. | 10-28-2010 |
20110018624 | INTEGRATED POWER DETECTOR WITH TEMPERATURE COMPENSATION FOR FULLY-CLOSED LOOP CONTROL - An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal. | 01-27-2011 |
Liyang Zhang, Shenzhen CN
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20130307628 | Radio Frequency Power Amplifier and Packaging and Fabrication Method Thereof - A radio frequency (RF) power amplifier includes: a pre-stage amplifier configured to amplify an input power to the RF power amplifier; and a post-stage amplifier configured to amplify an output power of the pre-stage amplifier; wherein the pre-stage amplifier comprises a CMOS (Complementary Metal Oxide Semiconductor) amplifier, and the post-stage amplifier comprises a GaAs (Gallium Arsenide) amplifier or a SiGe (Silicon Germanium) amplifier. | 11-21-2013 |
Liyang Zhang, Shanghai CN
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20160108492 | HIGH-FORMABILITY AND SUPER-STRENGTH HOT GALVANIZING STEEL PLATE AND MANUFACTURING METHOD THEREOF - A high-formability, super-high-strength, hot-dip galvanized steel plate, the chemical composition of which comprises, based on weight percentage, C: 0.15-0.25 wt %, Si: 1.00-2.00 wt %, Mn: 1.50-3.00 wt %, P≦0.015 wt %, S≦0.012 wt %, Al: 0.03-0.06 wt %, N≦0.008 wt %, and the balance of iron and unavoidable impurities. The room temperature structure of the steel plate comprises 10-30% ferrite, 60-80% martensite and 5-15% residual austenite. The steel plate has a yield strength of 600-900 MPa, a tensile strength of 980-1200 MPa, and an elongation of 15-22%. Through an appropriate composition design, a super-high-strength, cold rolled, hot-dip galvanized steel plate is manufactured by continuous annealing, wherein no expensive alloy elements are added; instead, remarkable increase of strength along with good plasticity can be realized just by appropriate augment of Si, Mn contents in combination with suitable processes of annealing and furnace atmosphere control. In addition, the steel plate possesses good galvanization quality that meets the requirement of a super-high-strength, cold rolled, hot-dip galvanized steel plate for automobiles. | 04-21-2016 |
Liyang Zhao, Shenzhen CN
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20150324423 | Report creation method, device and system - A report creation method, system, and device are described, and the method includes that: abstraction processing is performed on a data table in a database, and an Abstract Data Record (ADR) model is created; a report template is created according to the ADR model, and the report template is stored; and the created report template is called, a report query operation is executed, and report data obtained by querying is displayed. Through the disclosure, a user can create a complicated report template quickly, without involving a complicated secondary development process and writing a secondary development script. | 11-12-2015 |