| Patent application number | Description | Published |
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| 20120248573 | TUNABLE SEMICONDUCTOR DEVICE - Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern. | 10-04-2012 |
| 20120313146 | TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE - Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance R | 12-13-2012 |
| 20130119434 | BIPOLAR TRANSISTOR WITH A COLLECTOR HAVING A PROTECTED OUTER EDGE PORTION FOR REDUCED BASED-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance C | 05-16-2013 |
| 20130119436 | INTERFACE CONTROL IN A BIPOLAR JUNCTION TRANSISTOR - Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer. | 05-16-2013 |
| 20130119442 | JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY - Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate. | 05-16-2013 |
| 20130119505 | Schottky Barrier Diodes With a Guard Ring Formed by Selective Epitaxy - Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process. | 05-16-2013 |
| 20130119508 | BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS - Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process. | 05-16-2013 |
| 20130119516 | PNP BIPOLAR JUNCTION TRANSISTOR FABRICATION USING SELECTIVE EPITAXY - Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base. | 05-16-2013 |
| 20130126944 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH EPITAXIAL EMITTER STACK TO IMPROVE VERTICAL SCALING - A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p | 05-23-2013 |
| 20130130462 | TUNABLE SEMICONDUCTOR DEVICE - Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector. | 05-23-2013 |
| 20130134483 | BIPOLAR TRANSISTOR WITH A RAISED COLLECTOR PEDASTAL FOR REDUCED CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased. | 05-30-2013 |
| 20130146947 | SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY - A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot. | 06-13-2013 |
| 20130168783 | MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) CAPACITIVE OHMIC SWITCH AND DESIGN STRUCTURES - A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material. | 07-04-2013 |
| 20130168820 | POWER SIGE HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH IMPROVED DRIVE CURRENT BY STRAIN COMPENSATION - A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer. | 07-04-2013 |
| 20130187198 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer. | 07-25-2013 |
| 20130207235 | SELF-ALIGNED EMITTER-BASE REGION - Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch. | 08-15-2013 |
| 20130214275 | TRANSISTOR HAVING A NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region. | 08-22-2013 |
| 20130277804 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Methods for fabricating a device structure such as a bipolar junction transistor, device structures for a bipolar junction transistor, and design structures for a bipolar junction transistor. The device structure includes a collector region formed in a substrate, an intrinsic base coextensive with the collector region, an emitter coupled with the intrinsic base, a first isolation region surrounding the collector region, and a second isolation region formed at least partially within the collector region. The first isolation region has a first sidewall and the second isolation region having a second sidewall peripherally inside the first sidewall. A portion of the collector region is disposed between the first sidewall of the first isolation region and the second sidewall of the second isolation region. | 10-24-2013 |
| 20130334664 | INTERFACE CONTROL IN A BIPOLAR JUNCTION TRANSISTOR - Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer. | 12-19-2013 |
| 20140021547 | INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE - An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region. | 01-23-2014 |
| 20140021587 | LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION - Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing. | 01-23-2014 |
| 20140035064 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 02-06-2014 |
| 20140084420 | METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY - A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening. | 03-27-2014 |
| 20140113426 | TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE - Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance R | 04-24-2014 |
| 20140117493 | ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY - Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures. | 05-01-2014 |
| 20140131773 | SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY - A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, filling the respective slot. | 05-15-2014 |
| 20140151852 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates. | 06-05-2014 |
| 20140217551 | TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures. | 08-07-2014 |
| 20140231236 | MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) CAPACITIVE OHMIC SWITCH AND DESIGN STRUCTURES - A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method includes forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method includes forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method includes forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method includes forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material. | 08-21-2014 |
| 20140231877 | COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region. | 08-21-2014 |
| 20140231878 | COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region. | 08-21-2014 |
| 20140284758 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials. | 09-25-2014 |
| 20140312453 | SCHOTTKY BARRIER DIODES WITH A GUARD RING FORMED BY SELECTIVE EPITAXY - Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process. | 10-23-2014 |
| 20140327106 | BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference. | 11-06-2014 |
| 20140332927 | SELF-ALIGNED BIPOLAR JUNCTION TRANSISTOR HAVING SELF-PLANARIZING ISOLATION RAISED BASE STRUCTURES - A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures. | 11-13-2014 |
| 20140353725 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE BY FORMING MONOCRYSTALLINE SEMICONDUCTOR LAYERS ON A DIELECTRIC LAYER OVER ISOLATION REGIONS - Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g., a bipolar device) is formed incorporating the resulting monocrystalline second and third semiconductor layers. | 12-04-2014 |
| 20140374802 | BIPOLAR TRANSISTOR WITH MASKLESS SELF-ALIGNED EMITTER - Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes. | 12-25-2014 |
| 20150014747 | METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY - A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening. | 01-15-2015 |
| 20150041895 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 02-12-2015 |
| 20150041956 | ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY - Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures. | 02-12-2015 |
| 20150048478 | TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures. | 02-19-2015 |
| 20150054123 | SELF-ALIGNED EMITTER-BASE REGION - Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch. | 02-26-2015 |
| 20150056777 | DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY - A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core. | 02-26-2015 |
| 20150069571 | HEAT DISSIPATION THROUGH DEVICE ISOLATION - According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide. | 03-12-2015 |
| 20150084128 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES WITH LOCAL HEAT DISSIPATER(S) AND METHODS - Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures. | 03-26-2015 |
