Patent application number | Description | Published |
20090146191 | LOW LEAKAGE SCHOTTKY CONTACT DEVICES AND METHOD - Method and apparatus are described for semiconductor devices. The method ( | 06-11-2009 |
20100059860 | COUNTER-DOPED VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 03-11-2010 |
20110156051 | SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTTKY CONTACTS - Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced. | 06-30-2011 |
20140087550 | METHODS OF MAKING SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTKYCONTACTS - Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced. | 03-27-2014 |
20140264449 | METHOD OF FORMING HEMT SEMICONDUCTOR DEVICES AND STRUCTURE THEREFOR - In one embodiment, a HEMT semiconductor device includes an isolation region that may include oxygen wherein the isolation region may extend thorough an ALGaN and GaN layer into an underlying layer. | 09-18-2014 |
20140264452 | METHOD OF FORMING A HEMT SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors. | 09-18-2014 |
20160043178 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface, forming an epitaxial layer of carbon doped semiconductor material on the semiconductor substrate, the epitaxial layer having a surface, forming a nucleation layer on the epitaxial layer; and forming a layer of III-nitride material on the nucleation layer. In accordance with another embodiment, the semiconductor component includes a silicon semiconductor substrate of a first conductivity type; a carbon doped epitaxial layer on the silicon semiconductor substrate; a buffer layer over the carbon doped buffer layer; and a channel layer on the buffer layer. | 02-11-2016 |
20160043181 | ELECTRONIC DEVICE INCLUDING A CHANNEL LAYER INCLUDING A COMPOUND SEMICONDUCTOR MATERIAL - An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof. | 02-11-2016 |
20160043185 | SEMICONDUCTOR COMPONENT AND METHOD - In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity. | 02-11-2016 |
20160043218 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench. | 02-11-2016 |
20160043219 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench. | 02-11-2016 |
20160064325 | SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors. | 03-03-2016 |
20160099314 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value. | 04-07-2016 |
Patent application number | Description | Published |
20080246638 | APPARATUS AND METHOD TO ENCODE BINARY DATA INTO TRINARY DATA - An apparatus and method are disclosed to encode binary data into trinary data. Applicants' method provides binary data, and encodes that binary data into trinary data. By “binary data,” Applicants mean a plurality of bits, wherein each of those bits comprises a value selected from the group consisting of a first value and a second value. By “trinary data,” Applicants mean a plurality of bits, wherein each of those bits comprises a value selected from the group consisting of a first value, a second value, and a third value. The trinary data may be stored in ROM optical disks, nano-sized indentations in a thin-film, or multi-level magnetic storage. The trinary data may be also transmitted via three light levels in an optical communications network. | 10-09-2008 |
20090086299 | APPARATUS AND METHOD TO ENCODE INFORMATION HOLOGRAPHICALLY - A method to encode information holographically, wherein the method provides information, and generates a plurality of data images, wherein each data image comprises a portion of the information. The method holographically encodes each of the plurality of data images in a holographic data storage medium, generates a plurality of identifiers, and associates a different one of the plurality of identifiers with a different one of the plurality of data images. The method forms a directory image reciting each of plurality of identifiers, encodes the directory image in a non-holographic data storage medium, and holographically encodes the directory image in the holographic data storage medium. | 04-02-2009 |
20100027401 | RUN LENGTH LIMITED ENCODING OF DATA INTO A 5X5 MATRIX FOR RECORDING INTO A HOLOGRAPHIC MEDIUM - Holographic recording drives encode data for recording into a holographic medium. The steps comprise run length limited encoding three bytes of data into 5×5 matrix information, the data subject to a 4-byte error correction code; and providing the 5×5 matrix information to a spatial light modulator (SLM), as a portion of a two-dimensional pixel matrix of the spatial light modulator, for recording into a holographic image on the holographic medium. | 02-04-2010 |
Patent application number | Description | Published |
20100329846 | TURBINE ENGINE COMPONENTS - A turbine engine component includes a wall, a main opening, and two clusters of two or more auxiliary openings. The wall includes cool and hot air sides. The main opening extends between the cool air side and the hot air side and has an inlet and an outlet. The inlet is formed on the cool air side, and the outlet is formed on the hot air side. The first cluster of two or more auxiliary openings extends from the main opening to the hot air side. The second cluster of two or more auxiliary openings extends from the main opening to the hot air side. The main opening may be cylindrical or conical with a converging passage extending from the cool air side to the hot air side. The converging main opening may enhance flow through the auxiliary openings especially at high blowing ratios. | 12-30-2010 |
20110123312 | GAS TURBINE ENGINE COMPONENTS WITH IMPROVED FILM COOLING - An engine component includes a body; and a plurality of cooling holes formed in the body. At least one of the cooling holes has cross-sectional shape with a first concave portion and a first convex portion. | 05-26-2011 |
20110311369 | GAS TURBINE ENGINE COMPONENTS WITH COOLING HOLE TRENCHES - An engine component includes a body having an interior surface and an exterior surface; a cooling hole formed in the body and extending from the interior surface to the exterior surface; and a concave trench extending from the cooling hole at the exterior surface of the body in a downstream direction. | 12-22-2011 |
20130294889 | GAS TURBINE ENGINE COMPONENTS WITH FILM COOLING HOLES HAVING CYLINDRICAL TO MULTI-LOBE CONFIGURATIONS - An engine component includes a body; and a plurality of cooling holes formed in the body, at least one of the cooling holes having a multi-lobed shape with at least a first lobe, a second lobe, and a third lobe. | 11-07-2013 |
20130315710 | GAS TURBINE ENGINE COMPONENTS WITH COOLING HOLE TRENCHES - An engine component includes a body having an interior surface and an exterior surface; a cooling hole formed in the body and extending from the interior surface; and a nonconcave trench extending from the cooling hole to the exterior surface of the body in a downstream direction such that cooling air flow from within the body flow through the cooling hole, through the trench, and onto the exterior surface. | 11-28-2013 |
20140154096 | TURBINE BLADE AIRFOILS INCLUDING SHOWERHEAD FILM COOLING SYSTEMS, AND METHODS FOR FORMING AN IMPROVED SHOWERHEAD FILM COOLED AIRFOIL OF A TURBINE BLADE - Turbine blade airfoils, showerhead film cooling systems thereof, and methods for cooling the turbine blade airfoils using the same are provided. The airfoil has a leading edge and a trailing edge, a pressure sidewall and a suction sidewall both extending between the leading and the trailing edges, and an internal cavity for supplying cooling air. A showerhead of film cooling holes is connected to the internal cavity. Each film cooling hole has an inlet connected to the internal cavity and an outlet opening onto an external wall surface at the leading edge of the airfoil. A plurality of surface connectors is formed in the external wall surface. Each surface connector of the plurality of surface connectors interconnects the outlets of at least one selected pair of the film cooling holes. | 06-05-2014 |
20140356188 | TURBINE BLADE AIRFOILS INCLUDING FILM COOLING SYSTEMS, AND METHODS FOR FORMING AN IMPROVED FILM COOLED AIRFOIL OF A TURBINE BLADE - Turbine blade airfoils, film cooling systems thereof, and methods for forming improved film cooled components are provided. The turbine blade airfoil has an external wall surface and comprises leading and trailing edges, pressure and suction sidewalls both extending between the leading and the trailing edges, an internal cavity, one or more isolation trenches in the external wall surface, a plurality of film cooling holes arranged in cooling rows, and a plurality of span-wise surface connectors interconnecting the outlets of the film cooling holes in the same cooling row to form a plurality of rows of interconnected film cooling holes. Each film cooling hole has an inlet connected to the internal cavity and an outlet opening onto the external wall surface. The span-wise surface connectors in at least one selected row of interconnected film cooling holes are disposed in the one or more isolation trenches. | 12-04-2014 |
20160069194 | TURBINE BLADES AND METHODS OF FORMING TURBINE BLADES HAVING LIFTED RIB TURBULATOR STRUCTURES - The present disclosure provides various embodiments of cooling circuits, turbine blades with cooling circuits, and methods of forming such turbine blades, having raised rib turbulator structures, which may be used in gas turbine engines. In one exemplary embodiment, a cooling circuit for directing a flow of fluid is disclosed, the cooling circuit includes a cooling circuit wall and a plurality of raised turbulator ribs, each turbulator rib of the plurality of raised turbulator ribs being spaced apart from the cooling circuit wall to allow the fluid to flow between the cooling circuit wall and the plurality of turbulator ribs. | 03-10-2016 |
Patent application number | Description | Published |
20160079150 | TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH A PACKAGE LOAD ASSEMBLY - Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate. | 03-17-2016 |
20160087361 | TECHNIQUES AND CONFIGURATIONS TO CONTROL MOVEMENT AND POSITION OF SURFACE MOUNTED ELECTRICAL DEVICES - Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices. In one embodiment, an electrical contact includes a leg portion configured to extend in a first direction, a foot portion coupled with the leg portion, the foot portion having a surface that extends in a second direction that is substantially perpendicular to the first direction, the surface being configured to directly couple with solderable material to form a solder joint, a heel portion adjoining the leg portion and the foot portion, the heel portion having a profile shape, and a toe portion extending from the foot portion and disposed opposite to the heel portion, the toe portion having a profile shape that is symmetric with the profile shape of the heel portion. Other embodiments may be described and/or claimed. | 03-24-2016 |
Patent application number | Description | Published |
20090287402 | VIRTUAL TRAFFIC SENSORS - Techniques are described for virtual traffic sensors (VTS). In an implementation, an electronic device provides a variety of functionality including at least functionality to determine position. The electronic device may be further configured to ascertain locations of one or more virtual traffic sensors. In at least some embodiments, locations of virtual traffic sensors are determined by the electronic device using a variety of VTS criteria. Using a determined position, the electronic device may detect proximity to the virtual traffic sensors. The electronic device may collect traffic related data when in proximity to the one or more virtual traffic sensors. The electronic device may then communicate the collected traffic data over a suitable network connection to a service provider. | 11-19-2009 |
20090287405 | TRAFFIC DATA QUALITY - Techniques are described for traffic data quality. In an implementation, an electronic device provides a variety of functionality including functionality to determine position. The device may use determined position to ascertain geographic locations as collection points where traffic related data may be collected. In at least some embodiments, traffic data quality techniques combining both device side and server side technique are applied to data collected at the collections points. In an embodiment, communication of collected data by the device may be delayed to enable additional observations of vehicle movement, routing, position, and so forth. The additional observations during the delay enable the device to determine the validity of the collected data. | 11-19-2009 |
20100049397 | FUEL EFFICIENT ROUTING - Techniques are described to determine a fuel-efficient route for a vehicle. In an implementation, a determination is made, based on the one or more characteristics of the vehicle, as to a route between an identified location and a designated location that would cause the vehicle to consume a lesser amount of fuel when traveling between the identified and designated locations. Accordingly, the route may be represented, such as for use in navigating to the designated location. | 02-25-2010 |
20110153189 | HISTORICAL TRAFFIC DATA COMPRESSION - A device and method for calculating information regarding a route to a destination. The device may include a computer-readable memory element on which is stored a plurality of templates comprising historical speed values for a quantity of time segments and a map database including data for a plurality of road segments associated with template codes identifying one or more of the templates. The device may also include a processing device for accessing the map database to determine a historical speed value for one or more selected road segments. The historical speed value may be used for calculating an estimated amount of time to complete a selected route, a route to the destination that takes the least amount of time, and/or a predicted time of arrival at the destination. | 06-23-2011 |
20110207455 | METHOD AND APPARATUS FOR ESTIMATING CELLULAR TOWER LOCATION - A method and apparatus for collecting and analyzing cellular identification (ID) numbers at various geographic locations to estimate cellular tower locations. The method may include collecting cellular ID numbers obtained by collection mobile devices at a plurality of geographic locations then calculating minimum bounding circles encompassing a set of geographic location points with the same cellular identification numbers. If the cellular ID number of a set of location points indicates that the cellular tower is omni-directional, a center of the minimum bounding circle is an estimated cellular tower location. If the cellular ID number indicates that the cellular tower is multi-sector, the apparatus may calculate the estimated cellular tower location as the location at which lines that extend from the centers of a plurality of related minimum bounding circles intersect with each other to form equal angles. | 08-25-2011 |
20120124125 | AUTOMATIC JOURNAL CREATION - Techniques are described that facilitate the automatic creation of journals that may include a variety of related content. Journal creation functionality may be furnished by a server to one or more client devices to create journals of content that include content from one or more content sources. The content provided by the content sources includes tags (e.g., metadata) describing the content. Thus, a client device may furnish a request to a server to create a journal of content. The request includes an attribute to relate the content of the journal. The server causes content to be associated with the journal from one or more computer-readable content sources accessible by the server by associating one or more of the content tags with the attribute for one or more existing journals and thereafter creating the journal using the processor by causing content from the one or more existing journals to be associated with the journal, the associated content having tags associated with the attribute. | 05-17-2012 |
Patent application number | Description | Published |
20080219188 | Home Media Switch - A media switch includes a backplane. A controller module is connected to the backplane for transferring a user command to a media device. A set of audio/video signal busses are connected to the backplane for transferring signals. A power bus is connected to the backplane for supplying power. A bus interface is connected to the bus to provide a connection point for the media device. A bus switch is positioned between the interface and the bus for transferring signals to the bus. The switch is operated by the controller module. A command bus is connected to the backplane for transferring a user command to the media device via a command interface. | 09-11-2008 |
20100180131 | POWER MANAGEMENT MECHANISM FOR DATA STORAGE ENVIRONMENT - A method, system, and computer program product for facilitating power instability in a central electronics complex (CEC) of data storage computing environment in advance of a potential power failure is provided. Upon receipt of a first early power off warning (EPOW) signal indicating power instability, a first priority of execution of a first data storage task to be performed pursuant to a new data storage request is decreased, while a second priority of execution of a second data storage task to destage data in nonvolatile storage (NVS) to disk is increased. Upon receipt of a second EPOW signal indicating power failure, a system shutdown procedure is executed. | 07-15-2010 |
20120151167 | SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - Systems, methods, and computer storage mediums for managing read-only memory are provided. A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. One computer storage medium includes a computer program product for performing the above method. | 06-14-2012 |
20120233375 | ADJUSTMENT OF POST AND NON-POST PACKET TRANSMISSIONS IN A COMMUNICATION INTERCONNECT - In a communication interconnect such as PCIe which favors post transmissions such as write requests over non-post transmissions such as read requests and completions, methods and systems for shortening the delay for non-post transmissions while maintaining fairness among the post transmissions. Undispatched non-post transmission requests are monitored on a running basis; and when a running value of the undispatched non-post transmission requests exceeds a threshold; ones of the post transmission requests are randomly dropped. | 09-13-2012 |
20120254498 | SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. | 10-04-2012 |
20130007755 | METHODS, COMPUTER SYSTEMS, AND PHYSICAL COMPUTER STORAGE MEDIA FOR MANAGING RESOURCES OF A STORAGE SERVER - For managing a storage server having improving overall system performance, a first input/output (I/O) request is received. A first priority level is dynamically assigned to the first I/O request, the first I/O request associated with a performance level for an application residing on a host in communication with the storage server. A second I/O request of a second priority level is throttled to allow at least a portion of a predetermined amount of resources previously designated for performing the second I/O request to be re-allocated to performing the first I/O request. The second priority level is different than the first priority level. | 01-03-2013 |
20130007757 | METHODS, COMPUTER SYSTEMS, AND PHYSICAL COMPUTER STORAGE MEDIA FOR MANAGING RESOURCES OF A STORAGE SERVER - For managing a storage server having improving overall system performance, a first input/output (I/O) request is received. A first priority level is dynamically assigned to the first I/O request, the first I/O request associated with a performance level for an application residing on a host in communication with the storage server. A second I/O request of a second priority level is throttled to allow at least a portion of a predetermined amount of resources previously designated for performing the second I/O request to be re-allocated to performing the first I/O request. The second priority level is different than the first priority level. | 01-03-2013 |
20150186294 | SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - Embodiments for managing read-only memory. A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. | 07-02-2015 |
20160041920 | SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - Embodiments for managing read-only memory. A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. | 02-11-2016 |
Patent application number | Description | Published |
20140138825 | MOLDED INSULATOR IN PACKAGE ASSEMBLY - Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed. | 05-22-2014 |
20140268612 | CORELESS SUBSTRATE WITH PASSIVE DEVICE PADS - Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate. | 09-18-2014 |
20140353827 | BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. | 12-04-2014 |
20150028486 | INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE - Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed. | 01-29-2015 |
20150318191 | MOLDED INSULATOR IN PACKAGE ASSEMBLY - Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed. | 11-05-2015 |
20150364423 | BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. | 12-17-2015 |