Patent application number | Description | Published |
20090072126 | Light source frequency detection circuit for image sensor - An apparatus for measuring the power frequency of a light source includes a photo-sensor, a modulator, and a logic unit. The photo-sensor generates an electrical signal that is responsive to light incident thereon from the light source. The modulator generates a modulated signal based on the electrical signal that toggles at a rate substantially proportional to the power frequency of the light source. The logic unit is coupled to receive the modulated signal and determine its toggling frequency. | 03-19-2009 |
20090128232 | SWITCHED-CAPACITOR AMPLIFIER WITH IMPROVED RESET PHASE - A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the scamplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier. | 05-21-2009 |
20090128660 | LIGHT SOURCE FREQUENCY DETECTION CIRCUIT USING BIPOLAR TRANSISTOR - An apparatus for measuring the power frequency of a light source includes a photo-sensitive transistor, a modulators and a logic unit. The photo-sensitive transistor generates an electrical signal that is responsive to light incident thereon from the light source. The modulator generates a modulated signal based on the electrical signal that toggles at a rate substantially proportional to the power frequency of the light source. The logic unit is coupled to receive the modulated signal and determine its toggling frequency. | 05-21-2009 |
20110148523 | OP-AMP SHARING WITH INPUT AND OUTPUT RESET - An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs. | 06-23-2011 |
20120262614 | MISSING CODE REDISTRIBUTION IN PIPELINE ANALOG TO DIGITAL CONVERTER - A stage of pipeline analog to digital converter (ADC) includes a multiplying digital to analog converter (MDAC) and a sub-analog to digital converter (sub-ADC). The sub-ADC includes a comparator and a random offset controller. The comparator is coupled to compare a first analog signal received by the stage with a reference signal. The random offset controller is coupled to the comparator to apply a random offset to an input of the comparator to randomly distribute errors by the sub-ADC in a digital output of the pipeline ADC. | 10-18-2012 |
20140008515 | HYBRID ANALOG-TO-DIGITAL CONVERTER HAVING MULTIPLE ADC MODES - A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage. | 01-09-2014 |
20150109500 | IMAGE SENSOR INCLUDING SPREAD SPECTRUM CHARGE PUMP - A method of reducing harmonic tones of noise in an image sensor includes generating a system clock and generating a random clock in response to the system clock. A charge pump is clocked with the random clock to generate a boosted voltage. The boosted voltage is provided to a pixel array of the image sensor. Image charge is readout from pixel cells of the pixel array using the boosted voltage from the charge pump. | 04-23-2015 |
20150288902 | FEED-FORWARD TECHNIQUE FOR POWER SUPPLY REJECTION RATIO IMPROVEMENT OF BIT LINE - An image sensor read out circuit includes a first current mirror circuit in which a second current conducted through a second current path is controlled in response to a first current conducted through the first current path. The second current is conducted through an amplifier transistor of a pixel circuit. A first current source coupled to the first current path to provide a substantially constant current component of the first current. A second current source coupled to a power supply rail of the pixel circuit and coupled to the first current path to provide a ripple current component of the first current. The ripple current component provided by the second current source is responsive to a ripple in the power supply rail. The first current is responsive to a sum of the currents from the first and second current sources. | 10-08-2015 |