Patent application number | Description | Published |
20150104098 | NOTE RECOGNITION AND MANAGEMENT USING MULTI-COLOR CHANNEL NON-MARKER DETECTION - Techniques are described for creating and manipulating software notes representative of physical notes. A computing device comprises a processor and a note identification module executable on the processor and configured to separate an input image into a plurality of channelized input images. Each of the channelized input images are associated with a different color. The note identification module is configured to apply edge detection and feature extraction to identify polygons within each of the channelized input images and select, from the polygons from the channelized input images, a representative polygon for each of the physical notes in the input image. | 04-16-2015 |
20150104107 | NOTE RECOGNITION AND ASSOCIATION BASED ON GROUPING INDICATORS - Techniques are described for creating and manipulating software notes representative of physical notes. A computing device is described that includes a processor and an image collection module executable on the processor and configured to receive an input image of an environment having a plurality of physical notes. An image processing engine executable on the processor is configured to identify the plurality of physical notes in the input image and generate, for each of the physical notes, a corresponding digital note. The image processing engine is further configured to identify an indication of one or more groups of the plurality of identified notes in the input image and group the plurality of digital notes according to the indication. | 04-16-2015 |
20150106755 | EDITING DIGITAL NOTES REPRESENTING PHYSICAL NOTES - In one example, a method includes receiving a digital note of a plurality of digital notes generated based on image data comprising a visual representation of a scene that includes a plurality of physical notes such that each of the plurality of digital notes respectively corresponds to a particular physical note of the plurality of physical notes, wherein each of the physical notes includes respective recognizable content. In this example, the method also includes receiving user input indicating a modification to one or more visual characteristics of the digital note. In this example, the method also includes editing, in response to the user input, the one or more visual characteristics of the digital note. In this example, the method also includes outputting, for display, a modified version of the digital note that includes the one or more visual characteristics. | 04-16-2015 |
20150106760 | ORGANIZING DIGITAL NOTES ON A USER INTERFACE - At least some aspects of the present disclosure feature a computing device configured to display visual representations of digital notes and one or more group images representing one or more groups on a user interface, where each group may include one or more digital notes. The computing device is further configured to receive one or more user inputs via the user interface and change the compositions of the groups based on the received user inputs. | 04-16-2015 |
20150213310 | NOTE RECOGNITION AND ASSOCIATION BASED ON GROUPING INDICATORS - Techniques are described for creating and manipulating software notes representative of physical notes. A computing device is described that includes a processor and an image collection module executable on the processor and configured to receive an input image of an environment having a plurality of physical notes. An image processing engine executable on the processor is configured to identify the plurality of physical notes in the input image and generate, for each of the physical notes, a corresponding digital note. The image processing engine is further configured to identify an indication of one or more groups of the plurality of identified notes in the input image and group the plurality of digital notes according to the indication. | 07-30-2015 |
20150220257 | NOTE CAPTURE AND RECOGNITION WITH MANUAL ASSIST - At least some aspects of the present disclosure feature a computing device configured to receive an input image of an environment having a plurality of physical notes. The computing device automatically processes the input image to identify at least some of the plurality of the physical notes in the input image and displays the input image and indications indicative of the identified physical notes on a user interface. The computing device receives a user input indicating a position within the input image via a user interface and, responsive to the user input, recognizes proximate to the position a missed one of the physical notes that was not identified by the computing device when initially processing the input image. | 08-06-2015 |
20150220800 | NOTE CAPTURE, RECOGNITION, AND MANAGEMENT WITH HINTS ON A USER INTERFACE - At least some aspects of the present disclosure feature a computing device with an image capture device to capture a visual representation of one or more notes. The computing device is configured to generate hint related to image capture and present the hint via a user interface. | 08-06-2015 |
20150269751 | NOTE RECOGNITION AND MANAGEMENT USING MULTI-COLOR CHANNEL NON-MARKER DETECTION - Techniques are described for creating and manipulating software notes representative of physical notes. A computing device comprises a processor and a note identification module executable on the processor and configured to separate an input image into a plurality of channelized input images. Each of the channelized input images are associated with a different color. The note identification module is configured to apply edge detection and feature extraction to identify polygons within each of the channelized input images and select, from the polygons from the channelized input images, a representative polygon for each of the physical notes in the input image. | 09-24-2015 |
Patent application number | Description | Published |
20140273443 | METHODS OF FORMING TRENCH/HOLE TYPE FEATURES IN A LAYER OF MATERIAL OF AN INTEGRATED CIRCUIT PRODUCT - One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material. | 09-18-2014 |
20140329388 | METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS - Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer. | 11-06-2014 |
20150064912 | METHODS OF FORMING INTEGRATED CIRCUITS AND MULTIPLE CRITICAL DIMENSION SELF-ALIGNED DOUBLE PATTERNING PROCESSES - Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space. | 03-05-2015 |
20150187905 | METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES - One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material. | 07-02-2015 |
20150214331 | REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL - A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions. | 07-30-2015 |
20150255299 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SELECTIVELY FORMING AND REMOVING FIN STRUCTURES - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures. | 09-10-2015 |
20150318181 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING - Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features. | 11-05-2015 |
20150357434 | REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL - A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions. | 12-10-2015 |
20150380405 | REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS - After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions. | 12-31-2015 |
20160064236 | METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS - A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask. | 03-03-2016 |
Patent application number | Description | Published |
20100010599 | System and method to regulate temperature - A system and method for thermal regulation, the system comprising a bedding element that is configured to enclose at least a part of a living being or other object. The system further comprising a temperature regulation element that is included in the bedding element and that includes a phase change material which changes between a liquid phase and a solid phase within the desired temperature range. | 01-14-2010 |
20120305231 | SYSTEMS AND METHODS TO REGULATE BODY TEMPERATURE - Systems and methods are disclosed for regulating body temperature. The system includes a housing that comprises compartments for a phase change material and a heat transfer material. The compartments are configured to transfer heat from the heat transfer material to the phase change material. A temperature sensor is used to determine when the phase change material has reached a pre-determined temperature. When the pre-determined temperature is reached, a release mechanism or lever is coupled to the temperature sensor to separate the phase change material compartment from the heat transfer material compartment or to remove the heat transfer material away from the phase change material compartment. The heated phase change material compartment can be used to regulate body temperature. | 12-06-2012 |
20120330388 | SYSTEM AND METHOD TO REGULATE TEMPERATURE - A system and method for thermal regulation, the system comprising a bedding element that is configured to enclose at least a part of a living being or other object. The system further comprising a temperature regulation element that is included in the bedding element and that includes a phase change material which changes between a liquid phase and a solid phase within the desired temperature range. | 12-27-2012 |
20150066119 | INFANT WARMING SYSTEMS - Infant warming systems are described herein generally comprising a temperature regulation assembly which encloses a phase change material (PCM). The temperature regulation assembly may be initially heated (or re-heated) by water contained within a heating assembly and then placed within a retaining pouch of an infant bedding. The PCM may then provide constant heat over a period of time to the infant. A control/indicator interface coupled to the regulation assembly may constantly monitor the temperature of the PCM as well as the ambient temperature to provide one or more indications or alerts to the user with respect to one of several states of the warming assembly. | 03-05-2015 |
Patent application number | Description | Published |
20150156181 | METHODS AND DEVICES FOR SECURITY KEY RENEWAL IN A COMMUNICATION SYSTEM - A method is provided for security key renewal performed in a key management device of a communication system. The communication system includes two or more communication devices communicating data packets by using a first security key for transmission and reception. The method includes transmitting, to the two or more communication devices, a second security key for transmission and reception of the data packets; transmitting, to the two or more communication devices, an activation message for activating use of the second security key for reception of the data packets; transmitting, to the two or more communication devices, an activation message for activating use of the second security key for transmission of the data packets; transmitting, to the two or more communication devices; a deactivation message for deactivating use of the first security key for transmission of the data packets; and transmitting, to the two or more communication devices, a deactivation message for deactivating use of the first security key for reception of the data packets. | 06-04-2015 |
20150222520 | LATENCY DETERMINATION IN SUBSTATION NETWORKS - The present disclosure relates to latency determination in a substation network. One aspect relates to a method being performed in a first electronic device of the substation network. Another aspect relates to a method being performed in a relay device of the substation network. Yet another aspect relates to a method being performed in a second electronic device of the substation network. Latency is determined using a precision time protocol, such as the IEEE 1588v2 protocol. However, no GPS based master clock timing is required. Instead at least one data value is included as payload in a message of the precision time protocol. The relay device adds a residence time duration and a link latency to the message. The message is then forwarded to the second electronic device. A corresponding first electronic device, relay device, and second electronic device as well as a computer program and computer program product are also provided. | 08-06-2015 |
Patent application number | Description | Published |
20080313440 | SWITCHING TO ORIGINAL CODE COMPARISON OF MODIFIABLE CODE FOR TRANSLATED CODE VALIDITY WHEN FREQUENCY OF DETECTING MEMORY OVERWRITES EXCEEDS THRESHOLD - A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions. | 12-18-2008 |
20100169613 | TRANSLATING INSTRUCTIONS IN A SPECULATIVE PROCESSOR - A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds. | 07-01-2010 |
20100262955 | METHOD FOR INTEGRATION OF INTERPRETATION AND TRANSLATION IN A MICROPROCESSOR - A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known. | 10-14-2010 |
20120036502 | CONSISTENCY CHECKING FOR TRANSLATED INTRUCTIONS - In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled. | 02-09-2012 |