Patent application number | Description | Published |
20080299761 | Interconnection process - An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole. | 12-04-2008 |
20090081859 | Metallization process - A metallization process is provided. The metallization process comprises the following steps. First, a semiconductor base having at least a silicon-containing conductive region is provided. Afterwards, nitrogen ions are implanted into the silicon-containing conductive region. Next, a first thermal process is performed on the semiconductor base for repairing the surface of the semiconductor base. Then, a metal layer is formed on the surface of the semiconductor base and the metal layer covers the silicon-containing conductive region. Lastly, a second thermal process is performed on the semiconductor base covered with the metal layer so as to form a metal silicide layer on the silicon-containing conductive region. | 03-26-2009 |
20090114973 | METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS SIMULTANEOUSLY - The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic. | 05-07-2009 |
20110075486 | CHARGE TRAPPING MEMORY CELL HAVING BANDGAP ENGINEERED TUNNELING STRUCTURE WITH OXYNITRIDE ISOLATION LAYER - A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes. | 03-31-2011 |
20150110384 | IMAGE INSPECTION METHOD OF DIE TO DATABASE - An image inspection method of die to database is provided, and the positions in the to-be-inspected chips within one wafer may be selected. In the method, a plurality of inspection areas in a plurality of positions in the to-be-inspected chips within a wafer are selected, a plurality of raw images of the inspection areas are obtained, and a plurality of locations of the raw images are then decoded. After that, an image extraction is performed on the raw images to obtain a plurality of image contours. Thereafter, the image contours are compared with a design database of the chip in order to obtain a result of a defect inspection, and execute the same thing in whole wafer. | 04-23-2015 |
20150213172 | METHOD FOR MEASURING AND ANALYZING SURFACE STRUCTURE OF CHIP OR WAFER - A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect. | 07-30-2015 |
20150226687 | ELECTRON BEAM INSPECTION OPTIMIZATION - An electron beam (E beam) inspection optimization is provided, in which a plurality of initial inspection regions in a chip are obtained, wherein a center of each of the initial inspection regions is a defect point. Thereafter, reset inspection regions are regenerated without overlap, wherein each of the reset inspection regions is within a scope covered by a field of view (FOV) and the scope contains at least one of the defect points. Afterwards, a center of the reset inspection region is transferred into an inspection center, and then an E beam inspection is performed on the inspection center. | 08-13-2015 |
20150323583 | METHOD FOR DETECTING AN ELECTRICAL DEFECT OF CONTACT/VIA PLUGS - A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal. | 11-12-2015 |