Patent application number | Description | Published |
20090208692 | LIMITED LIFE OPTICAL MEDIA - Optical media of a limited usable life are disclosed. The invention relates to chemical formulations and methods and processes for creating time limiting mechanisms for the inclusion in optical media thereby providing optical media with a limited usable life in which encoded information may be accessed, played and/or read for a prescribed limited time. The invention provides formulations and methods for corrosion of and/or the corrosive degradation of a reflective layer(s) and/or reflective material of optical media such that the encoded information stored on an optical medium can not longer be read by a reading beam. | 08-20-2009 |
20090262623 | OPTICAL MEDIA FORMAT - Apparatuses, products, devices and methods, of manufacture consistent with the invention include optically readable media with at least one mechanism, chemical, agent, and/or process for limiting the time period that at least a portion of encoded information can be read and/or accessed by an optical beam and/or reader capable of reading the encoded information. | 10-22-2009 |
20130032204 | NOVEL ELECTRODE - Photovoltaic cells containing a novel electrode, as well as related systems, methods, modules, and components, are disclosed. | 02-07-2013 |
20130263925 | Hole Carrier Layer For Organic Photovoltaic Device - The present invention relates to a photovoltaic cell that comprises a first electrode, a second electrode, a photoactive layer between the first electrode and the second electrode, and a hole carrier layer between the first electrode and the photoactive layer. In one embodiment, the hole carrier layer comprises an oxidizing agent and a hole carrier polymer. | 10-10-2013 |
Patent application number | Description | Published |
20080290387 | Semiconductor device having reduced sub-threshold leakage - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 11-27-2008 |
20090026530 | METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FINS - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 01-29-2009 |
20100032739 | Methods Of Forming Vertical Field Effect Transistors, vertical field effect transistors, and dram cells - A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated. | 02-11-2010 |
20100072557 | Semiconductor Constructions - Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C | 03-25-2010 |
20100171170 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 07-08-2010 |
20100327369 | Semiconductor Constructions - Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C | 12-30-2010 |
20110057269 | SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 03-10-2011 |
20110133263 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 06-09-2011 |
20110140187 | Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, And DRAM Cells - A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated. | 06-16-2011 |
20120003810 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 01-05-2012 |
20120175748 | SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS AND METHODS OF FABRICATION - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 07-12-2012 |
20120241831 | Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, and DRAM Cells - A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated. | 09-27-2012 |
20130309839 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING RECESSES - Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 11-21-2013 |