Patent application number | Description | Published |
20120292740 | HIGH VOLTAGE RESISTANCE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A HIGH VOLTAGE RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate, a lateral semiconductor diode, a field insulation structure, and a polysilicon resistor. The diode is formed in a surface region of the semiconductor substrate, and includes a cathode electrode and an anode electrode. The field insulation structure is disposed between the cathode and anode electrodes. The polysilicon resistor is formed over the field insulation structure, and between the cathode and anode electrodes. The polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated from the anode electrode. | 11-22-2012 |
20130207236 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra IN-type layer that reduces recombination of electrons and holes. | 08-15-2013 |
20140061721 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention. | 03-06-2014 |
20140175547 | SEMICONDUCTOR DEVICE HAVING VARYING P-TOP AND N-GRADE REGIONS - An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor. | 06-26-2014 |
20140175560 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region, a second doped region, and a gate structure. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The gate structure is formed on the first doped region and the second doped region. The gate structure comprises a first gate portion and a second gate portion, which are separated from each other by a gap. | 06-26-2014 |
20140191792 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD AND OPERATING METHOD FOR THE SAME - A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high threshold voltage channel region is formed in the first well and extending down from the surface of the substrate. | 07-10-2014 |
20150048452 | ULTRA-HIGH VOLTAGE SEMICONDUCTOR HAVING AN ISOLATED STRUCTURE FOR HIGH SIDE OPERATION AND METHOD OF MANUFACTURE - A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided. | 02-19-2015 |
20150179527 | SEMICONDUCTOR DEVICE HAVING VARYING P-TOP AND N-GRADE REGIONS - An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor. | 06-25-2015 |
20150263085 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping. | 09-17-2015 |
20150357481 | JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor is disclosed. The junction field effect transistor includes a first doped region and a second doped region. The first doped region includes a source and a drain. The second doped region includes a gate. The first doped region and the second doped region have a U-shape PN junction there between. The U-shape PN junction is between the source and the drain. | 12-10-2015 |
20160064494 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device including a P type substrate, a high voltage N type well, a first P type well, a drift region, and a P type doping layer is provided. The high voltage N type well and the P type doping layer, which is formed in a region located below the first P type well and the drift region, are formed in the P type substrate. The first P type well is formed in the high voltage N type well. A bottom of the first P type well and a bottom of the P type doping layer are separated from a surface of the P type substrate by a first depth and a second depth larger than the first depth, respectively. The drift region is formed in the high voltage N type well and extending down from the surface of the P type substrate. | 03-03-2016 |
20160064558 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure comprises a doped substrate, a gate structure, a source, a drain and a field doped region. The source and the drain are in the doped substrate on opposing sides of the gate structure respectively. The field doped region has a conductivity type opposite to a conductivity type of the source and the drain. The field doped region is extended from the source to be beyond a first gate sidewall of the gate structure but not reach a second gate sidewall of the gate structure opposing to the first gate sidewall. | 03-03-2016 |
Patent application number | Description | Published |
20120207047 | Priority Rules of Periodic CSI Reporting in Carrier Aggregation - A method of determining priority rules for periodic CSI reporting in carrier aggregation is proposed. A UE obtains channel state information (CSI) feedback for multiple downlink component carriers (CCs) in a multi-carrier wireless communication network. Each downlink CC is associated with a feedback mode, and each feedback mode comprises a set of feedback types to be reported to a base station at time slots configured by an upper layer. The UE then determines a prioritized downlink CC for CSI reporting based on priority levels of the feedback types to be transmitted for each downlink CC at a given time slot. The UE then transmits the corresponding CSI feedback for the prioritized downlink CC at the given time slot via a feedback channel over a primary uplink CC. In one embodiment, different feedback types are prioritized by groups, and each group has several feedback types sharing the same priority. | 08-16-2012 |
20120281646 | Signaling Methods for UE-Specific Dynamic Downlink Scheduler in OFDMA Systems - Signaling methods for UE-specific downlink control channels in OFDMA systems are provided. In a first method, a dynamic downlink signaling in cell-specific radio resources is used to signal UE-specific downlink control channel in UE-specific radio resources. In LTE, a specific DCI format in PDCCH is used to dynamically signal the UE-specific downlink control channel X-PDCCH that resides in legacy PDSCH region. In a second method, a semi-static higher-layer signaling is used to signal UE-specific downlink control channel in UE-specific radio resources. In LTE, RRC signaling is used to semi-statically signal the UE-specific downlink control channel X-PDCCH that resides in legacy PDSCH region. By using UE-specific downlink control channels, significant control overhead reduction can be achieved. | 11-08-2012 |
20130039199 | Methods of Point Association for Cooperative Multiple Point Transission - Procedures for point association as well as measurement and feedback required to enable point association for CoMP deployment scenario 4 are proposed. In a first novel aspect, a serving eNB configures a first higher-layer configuration for RSRP measurement to be used by a UE for serving point selection. The higher-layer configuration contains multiple CSI-RS configurations, and each CSI-RS configuration indicates a set of resource elements (REs) or subcarriers in both frequency domain and time domain as one CSI-RS resource with non-zero transmission power. The UE then performs RSRP measurements based on the multiple CSI-RS configurations and reports RSRP measurement results to the serving eNB. In a second novel aspect, the serving eNB configures a second higher-layer configuration for CSI reporting based on the reported RSRP measurement results. In a third novel aspect, the serving eNB sends CSI-RS information to the UE for uplink power control. | 02-14-2013 |
20140321385 | Physical Structure and Sequence Design of Midamble in OFDMA Systems - In wireless OFDMA systems, midamble is used to facilitate downlink (DL) channel estimation. Midamble signals are transmitted by a base station via a midamble channel allocated in a DL subframe. In a novel symbol-based midamble channel allocation scheme, a midamble channel is allocated in the first or the last OFDM symbol of multiple resource blocks of the subframe, while the remaining consecutive OFDM symbols are used for data transmission. The symbol-based midamble channel provides good coexistence between midamble signals and pilot signals without inducing additional limitation or complexity. Under a novel midamble channel and sequence arrangement, both code sequence and either time-domain or frequency-domain location degrees-of-freedom are considered such that the required number of midamble sequences is substantially smaller than the number of strong interferences. In addition, different midamble sequences are systematically generated based on a base sequence such that the receiving mobile station does not need to memorize all the different code sequences. | 10-30-2014 |
20140341065 | Priority Rules of Periodic CSI Reporting in Carrier Aggregation - A method of determining priority rules for periodic CSI reporting in carrier aggregation is proposed. A UE obtains channel state information (CSI) feedback for multiple downlink component carriers (CCs) in a multi-carrier wireless communication network. Each downlink CC is associated with a feedback mode, and each feedback mode comprises a set of feedback types to be reported to a base station at time slots configured by an upper layer. The UE then determines a prioritized downlink CC for CSI reporting based on priority levels of the feedback types to be transmitted for each downlink CC at a given time slot. The UE then transmits the corresponding CSI feedback for the prioritized downlink CC at the given time slot via a feedback channel over a primary uplink CC. In one embodiment, different feedback types are prioritized by groups, and each group has several feedback types sharing the same priority. | 11-20-2014 |
20140341167 | Sounding Mechanism and Configuration under Carrier Aggregation - A method of multi-set RRC signaling for ap-SRS configuration is provided to enhance ap-SRS flexibility. An eNB transmits a plurality of sets of UE-specific SRS parameters to a UE via upper layer messaging in a multi-carrier wireless communication system. The eNB also determines triggering information of a selected set of UE-specific SRS parameters and an indicated carrier for the UE. The eNB then transmits an uplink or downlink grant over a primary carrier, the grant comprises triggering information for the UE to send an ap-SRS over the indicated carrier using the selected set of UE-specific SRS parameters. In one embodiment of joint signaling, the plurality of sets of UE-specific SRS parameters are signaled together in a single RRC transmission. In another embodiment of separate signaling, each set of UE-specific SRS parameters is signaled independently. | 11-20-2014 |
20140362811 | Sounding Mechanism under Carrier Aggregation - Sounding mechanism for LTE-A systems under carrier aggregation is provided. A UE receives an uplink or downlink grant transmitted from an eNB over a primary carrier in a multi-carrier LTE-A system. The UE determines indicated carrier(s) and detects a triggering condition for aperiodic sounding transmission in the grant. The UE then selects UE-specific sounding reference signal (SRS) parameters. Finally, the UE transmits an aperiodic SRS (ap-SRS) over the indicated carrier(s) using the selected UE-specific SRS parameters. In one embodiment, the uplink or downlink grant is transmitted via a PDCCH carrying various DCI formats. Each DCI format contains a carrier indicator field (CIF) that indicates which carrier is used for ap-SRS transmission if cross-carrier scheduling is enabled. In another embodiment, DCI format 3/3A is transmitted via a PDCCH carrying a plurality of information fields, each field indicates if the UE should enable ap-SRS in a particular carrier. | 12-11-2014 |
Patent application number | Description | Published |
20100139757 | PHOTOVOLTAIC CELL STRUCTURE - A photovoltaic cell structure includes a substrate, a metal layer, a high resistivity layer, a p-type semiconductor layer, an n-type semiconductor layer and a transparent conductive layer. The metal layer may include molybdenum and be formed on the substrate to be a back contact metal layer of the cell. The high resistivity layer (e.g., V | 06-10-2010 |
20100139758 | PHOTOVOLTAIC CELL STRUCTURE AND MANUFACTURING METHOD THEREOF - A photovoltaic cell structure includes a substrate, a metal layer, a p-type semiconductor layer, an n-type semiconductor layer and a transparent conductive layer. The substrate has a rough surface. The metal layer may include molybdenum and be formed on the rough surface. The p-type semiconductor layer is formed on the metal layer and may include CIGSS, CIGS, CIS, or compound of two or more of copper, selenium, sulfur. The n-type semiconductor layer is formed on the p-type semiconductor layer thereby forming a rough p-n junction surface. The n-type semiconductor layer may include CdS. The transparent conductive layer is formed on the n-type semiconductor layer. In an embodiment, the roughness Ra of the rough surface is between 0.01 to 100 μm. | 06-10-2010 |
20100243044 | PHOTOVOLTAIC CELL STRUCTURE - A photovoltaic cell structure includes a substrate, a metal layer, a p-type semiconductor layer, an n-type semiconductor layer, a transparent conductive layer and a high resistivity layer. The metal layer is formed on the substrate. The p-type semiconductor layer is formed on the metal layer and may include a compound of copper indium gallium selenium sulfur (CIGSS), copper indium gallium selenium (CIGS), copper indium sulfur (CIS), copper indium selenium (CIS) or a compound of at least two of copper, selenium or sulfur. The n-type semiconductor layer exhibits photo catalyst behavior that can increase carrier mobility by receiving light, and is formed on the p-type semiconductor layer, thereby forming a p-n junction. The transparent conductive layer is formed on the n-type semiconductor layer. The high resistivity layer is formed between the metal layer and the transparent conductive layer. | 09-30-2010 |
20100258167 | PHOTOVOLTAIC CELL STRUCTURE AND MANUFACTURING METHOD - A photovoltaic cell structure includes a substrate, a metal layer, a p-type semiconductor layer, an n-type semiconductor layer, a high resistivity layer, an assistant electrode layer, and a transparent conductive layer. The metal layer is formed on the substrate, and comprises a plurality of p-type electrode units separated from each other. The p-type semiconductor layer is formed on the metal layer. The n-type semiconductor is formed on the p-type semiconductor layer, thereby forming a p-n junction. The high resistivity layer is formed on the n-type semiconductor layer. The assistant electrode layer is formed on the high resistivity layer and the p-type electrode units. The transparent conductive layer is formed on the assistant electrode layer, the high resistivity layer and the p-type electrode units. Accordingly, at least one cell is formed on each of the p-type electrode units. The assistant electrode layer and the transparent conductive layer are connected to the cells in series. | 10-14-2010 |
20110297225 | PHOTOVOLTAIC CELL STRUCTURE - A photovoltaic cell structure includes a substrate, a metal layer, a p-type semiconductor layer, an n-type semiconductor layer, a transparent conductive layer and a high resistivity layer. The metal layer is formed on the substrate. The p-type semiconductor layer is formed on the metal layer and may include a compound of copper indium gallium selenium sulfur (CIGSS), copper indium gallium selenium (CIGS), copper indium sulfur (CIS), copper indium selenium (CIS) or a compound of at least two of copper, selenium or sulfur. The n-type semiconductor layer exhibits photo catalyst behavior that can increase carrier mobility by receiving light, and is formed on the p-type semiconductor layer, thereby forming a p-n junction. The transparent conductive layer is formed on the n-type semiconductor layer. The high resistivity layer is formed between the metal layer and the transparent conductive layer. | 12-08-2011 |
Patent application number | Description | Published |
20090289688 | SIGNAL ADJUSTING CIRCUIT - A signal adjusting circuit is provided. The signal adjusting circuit includes a first operational unit, a second operational unit, an auto-gain controller (AGC), a first clamp circuit, and a second clamp circuit is provided. The first operational unit performs an operation to a digital signal and a first gain value, to obtain a first adjusting signal. The second operational unit performs an operation to the digital signal and a second gain value, to obtain a second adjusting signal. The AGC generates a third gain value according to the first adjusting signal. The first clamp circuit receives and restricts the third gain value between a first upper limit and a first lower limit for generating the first gain value. The second clamp circuit receives and restricts the third gain value between a second upper limit and a second lower limit for generating the second gain value. | 11-26-2009 |
20090290066 | SIGNAL ADJUSTING CIRCUIT AND VIDEO APPARATUS THEREOF - A signal adjusting circuit and a video apparatus thereof are provided. The signal adjusting circuit includes a delay unit, a minimum value acquisition device, and a first operating unit. The delay unit receives a digital signal and delays the digital signal for N periods to serve as a delay signal. The minimum value acquisition device receives the digital signal and acquires a minimum value of the digital signal in every N periods. The first operating unit is coupled to the delay unit and the minimum value acquisition device for operating the delay signal with the minimum value to obtain an adjusting signal. | 11-26-2009 |
20100040181 | APPARATUS AND METHOD FOR FILTERING NOISE IN IMAGE SIGNAL - An apparatus and a method for filtering noise in an image signal are provided. The apparatus includes an analog-to-digital converter (ADC), a first filter, and a second filter. The ADC receives the image signal and converts the image signal into a digital signal. The first filter receives the digital signal and filters a first noise portion of the digital signal to generate a first signal. The second filter coupled to the first filter receives the first signal and filters a second noise portion of the first signal, wherein the first noise portion is a sampled-based impulse noise, and the second noise portion is a line-based impulse noise. | 02-18-2010 |
20100053445 | STATE DETECTOR OF VIDEO DEVICE AND STATE DETECTION METHOD THEREOF - A state detector of a video device and a state detection method thereof are provided. The state detector includes a first chroma detector, a second chroma detector, and a controller. The first chroma detector and the second chroma detector operate in a first state among a plurality of states. When the second chroma detector is not capable of processing an input signal normally, the controller controls the second chroma detector to switch between the states until the second chroma detector operates in a second state to process the input signal normally, and the first chroma detector is set to operating in the second state. As a result, the quality of a displayed image is improved. | 03-04-2010 |
20120236202 | VIDEO SIGNAL PROCESSING CIRCUIT AND METHOD APPLICABLE THERETO - A video signal processing circuit includes: a composite sync signal generation circuit, generating a composite sync signal from a received composite video signal; a signal-noise-ratio calculation unit, generating a SNR of the composite video signal; a timing generation unit, generating a gated window based on the SNR; and a vertical sync signal separation unit, generating a vertical sync signal from the composite sync signal based on the SNR and the gated window, and dynamically adjusting a detection criterion on the vertical sync signal. | 09-20-2012 |
20120240173 | VIDEO SIGNAL PROCESSING CIRCUIT AND METHOD APPLICABLE THERETO - A video signal processing circuit includes: a transport stream (TS) decoding unit, decoding a demodulated analog radio frequency (RF) signal for generating a first TS signal; and a TS bit rate control unit, deciding whether to insert a null packet stream into the first TS signal to generate a second TS signal. | 09-20-2012 |
20150254815 | IMAGE DOWNSAMPLING APPARATUS AND METHOD - An image downsampling apparatus and an image downsampling method are provided. The image downsampling apparatus includes a one-directional downsampling circuit, a multi-directional downsampling circuit and an output circuit. The one-directional downsampling performs one-directional downsampling by using an original image signal to obtain and output a first adjusted image signal. The multi-directional downsampling circuit performs multi-directional downsampling by using the original image signal to obtain and output a second adjusted image signal. The output circuit outputs a downsampled image signal according to the first adjusted image signal and the second adjusted image signal. | 09-10-2015 |
Patent application number | Description | Published |
20110062513 | OVERLAPPING TRENCH GATE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer. | 03-17-2011 |
20110084334 | BILATERAL CONDUCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A bilateral conduction semiconductor device and a manufacturing method thereof are provided. The bilateral conduction semiconductor device includes an epitaxial layer having a first conductive type and a first trench, a first gate conductive layer disposed on a sidewall of the first trench, a second gate conductive layer disposed opposite to the first gate conductive layer, and a doped region having the first conductive type. The doped region is disposed in the epitaxial layer between the first gate conductive layer and the second gate conductive layer, and a doped concentration of the doped region is larger than a doped concentration of the epitaxial layer. | 04-14-2011 |
20110084335 | SEMICONDUCTOR DEVICE WITH DRAIN VOLTAGE PROTECTION AND MANUFACTURING METHOD THEREOF - A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device. | 04-14-2011 |
20110278671 | LATERALLY DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICE - A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length. | 11-17-2011 |
20110291183 | POWER SEMICONDUCTOR DEVICE HAVING LOW GATE INPUT RESISTANCE AND MANUFACTURING METHOD THEREOF - A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process. | 12-01-2011 |
20120139037 | DEPLETION MODE TRENCH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region. | 06-07-2012 |
Patent application number | Description | Published |
20110235712 | LOW COMPLEXITY VIDEO DECODER - A low complexity video decoder includes: a fast variable length decoding (VLD) and inverse quantization module arranged to perform fast VLD and inverse quantization on an input bit stream to generate inverse quantization results; an inverse transform unit arranged to perform inverse transform on the inverse quantization results to generate inverse transform results; a motion compensation module arranged to perform motion compensation according to the input bit stream and generate associated prediction outputs, wherein the motion compensation module includes a temporal/spatial prediction unit arranged to perform temporal/spatial prediction to generate at least a portion of the prediction outputs; an arithmetic unit arranged to sum up the inverse transform results and the prediction outputs to generate compensated outputs; a reconstructed frame output unit arranged to generate reconstructed frames according to the compensated outputs; and a frame storage arranged to store some reconstructed frames. | 09-29-2011 |
20110235713 | METHOD FOR ADAPTIVELY PERFORMING VIDEO DECODING, AND ASSOCIATED ADAPTIVE COMPLEXITY VIDEO DECODER AND ADAPTIVE AUDIO/VIDEO PLAYBACK SYSTEM - A method for adaptively performing video decoding includes: performing decoding complexity management based upon bit stream information of an input bit stream, in order to determine whether to reduce decoding complexity of at least one component of a plurality of components within an adaptive complexity video decoder; and selectively reducing decoding complexity of a portion of components within the adaptive complexity video decoder. An associated adaptive complexity video decoder and an associated adaptive audio/video playback system are also provided. In particular, the adaptive complexity video decoder includes a plurality of components and a decoding complexity manager. When needed, the decoding complexity manager delays audio playback of audio information. | 09-29-2011 |
20110255598 | METHOD FOR PERFORMING LOCAL MOTION VECTOR DERIVATION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method for performing local motion vector derivation during video coding of a coding unit includes: processing a plurality of sub-coding units in the coding unit; and performing motion vector prediction of each of the sub-coding units. More particularly, the step of performing motion vector prediction of each of the sub-coding units further includes: deriving a motion vector of a specific sub-coding unit of the sub-coding units by utilizing at least one motion vector of at least one other sub-coding/coding unit. Thus, the method performs motion compensation on the specific sub-coding unit according to the motion vector of the specific sub-coding unit. An associated apparatus is also provided. | 10-20-2011 |
20110255600 | METHOD FOR PERFORMING LOCALIZED MULTIHYPOTHESIS PREDICTION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method for performing localized multihypothesis prediction during video coding of a coding unit includes: dividing the coding unit into a plurality of sub-coding units; and performing motion vector prediction of each of the sub-coding units. More particularly, the step of performing motion vector prediction of each of the sub-coding units further includes: obtaining a plurality of motion vectors for multihypothesis motion compensation of a specific sub-coding unit of the sub-coding units from a plurality of other sub-coding/coding units. The method further includes performing multihypothesis motion compensation on the specific sub-coding unit according to the plurality of motion vectors, and more particularly, includes utilizing a linear combination of a plurality of pixel values of the plurality of other sub-coding/coding units as a predicted pixel value of the specific sub-coding unit. An associated apparatus is also provided. | 10-20-2011 |
20110310956 | METHODS FOR CONTROLLING VIDEO DECODER TO SELECTIVELY SKIP ONE OR MORE VIDEO FRAMES AND RELATED SIGNAL PROCESSING APPARATUSES THEREOF - An exemplary method for processing an input bitstream having a plurality of video frames includes the following steps: deriving an indication data from decoding of a current video frame, and controlling a video decoder to decode or skip a next video frame by referring to at least the indication data and a video decoder capability of the video decoder. A signal processing apparatus for processing an input bitstream including a plurality of video frames includes a video decoder, an indication data estimating unit, and a controller. The video decoder is arranged to decode a current video frame. The indication data estimating unit is for deriving an indication data from decoding of the current video frame. The controller is for controlling the video decoder to decode or skip a next video frame by referring to at least the indication data and a video decoder capability of the video decoder. | 12-22-2011 |
20120027097 | METHOD FOR PERFORMING LOCALIZED MULTIHYPOTHESIS PREDICTION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method for performing localized multihypothesis prediction during video coding of a coding unit includes processing the coding unit. More particularly, the step of processing the coding unit further includes: obtaining at least two sets of motion information derived from a set of coded units for multihypothesis motion compensation of the coding unit; and utilizing a linear combination of a plurality of pixel values derived from the at least two sets of motion information derived from the set of coded units as a predicted pixel value of the coding unit. An associated apparatus is also provided. | 02-02-2012 |
20120063514 | METHOD FOR PERFORMING HYBRID MULTIHYPOTHESIS PREDICTION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method for performing hybrid multihypothesis prediction during video coding of a coding unit includes: processing a plurality of sub-coding units in the coding unit; and performing motion vector derivation of a portion of the sub-coding units. More particularly, the step of performing motion vector derivation of the portion of the sub-coding units further includes: deriving a plurality of motion vectors for multihypothesis motion-compensated prediction of a specific sub-coding unit of the portion of the sub-coding units from at least one other sub-coding/coding unit or by performing motion estimation. The method further includes performing multihypothesis motion-compensated prediction on the specific sub-coding unit according to the plurality of motion vectors, and more particularly, includes utilizing a linear combination of a plurality of pixel values derived from the plurality of motion vectors as a predicted pixel value of the specific sub-coding unit. An associated apparatus is also provided. | 03-15-2012 |
20120275502 | APPARATUS FOR DYNAMICALLY ADJUSTING VIDEO DECODING COMPLEXITY, AND ASSOCIATED METHOD - An apparatus for dynamically adjusting video decoding complexity includes a decoding resolution control circuit and an adaptive spatial resolution decoder. The decoding resolution control circuit is arranged to dynamically determine whether at least one portion of a plurality of frames should be decoded in accordance with a specific resolution differing from an original resolution of the plurality of frames. In addition, the adaptive spatial resolution decoder is arranged to decode the plurality of frames according to whether the at least one portion of the plurality of frames should be decoded in accordance with the specific resolution. In particular, the apparatus further includes a system capability analyzing circuit arranged to analyze system capability of at least a portion of the apparatus, in order to generate analyzing results for being sent to the decoding resolution control circuit. An associated method is also provided. | 11-01-2012 |
20130208804 | Method and Apparatus for Parsing Error Robustness of Temporal Motion Vector Prediction - A method and apparatus for deriving a motion vector predictor (MVP) are disclosed. The MVP is selected from spatial MVP and temporal MVP candidates. The method uses a flag to indicate whether temporal MVP candidates are disabled. If the flag indicates that the temporal MVP candidates are disabled, the MVP is derived from the spatial MVP candidates only. Otherwise, the MVP is derived from the spatial and temporal MVP candidates. The method may further skip spatial redundant MVP removal by comparing MV values. Furthermore, the parsing error robustness scheme determines a forced temporal MVP when a temporal MVP is not available and the temporal MVP candidates are allowed as indicated by the flag. The flag may be incorporated in sequence, picture, slice level, or a combination of these levels. | 08-15-2013 |
20130243098 | METHOD AND APPARATUS FOR DERIVATION OF MOTION VECTOR CANDIDATE AND MOTION VECTOR PREDICTION CANDIDATE - An apparatus and method for deriving a motion vector predictor are disclosed. A search set comprising of multiple (spatial, or temporal) search MVs with priority is determined, wherein the search MVs for multiple neighboring reference block or one or more co-located reference blocks arc configured into multiple search MV groups. In order to improve coding efficiency, embodiments according to the present invention, perform redundancy check every time after a search MV group is searched to determine whether an available search MV found. If an available search MV is found and the available search MV is not the same as a previously derived motion vector predictor (MVP), the available search MV is used as the MVP and the MVP derivation process terminates. Otherwise, the MVP derivation process moves to the next reference block. The search MV group can be configured to include different search MV(s) associated with reference blocks. | 09-19-2013 |
20130251343 | METHOD FOR PERFORMING FLUENT PLAYBACK CONTROL IN RESPONSE TO DECODING STATUS, AND ASSOCIATED APPARATUS - A method for performing fluent playback control is provided, where the method is applied to an electronic device. The method includes the steps of: determining whether an out of synchronization status regarding audio playback and video playback occurs; and when it is detected that the out of synchronization status occurs, controlling jump timing of video playback according to at least one of scene change detection and standstill detection. For example, the scene change detection can be performed to determine whether a scene change exists, and when it is detected that the scene change exists, a jump operation of video playback is triggered. In another example, the standstill detection can be performed to determine whether a standstill phenomenon exists, in order to determine whether to delay triggering a jump operation of video playback. In another example, a temporary audio pause operation can be selectively performed. An associated apparatus is also provided. | 09-26-2013 |
20140092981 | METHOD AND APPARATUS FOR REMOVING REDUNDANCY IN MOTION VECTOR PREDICTORS - A method and apparatus of deriving a motion vector predictor (MVP) for a current block in an Inter, Merge, or Skip mode are disclosed. Embodiments according to the present invention determine redundant MVP candidates according to a non-MV-value based criterion. The redundant MVP candidates are then removed from the MVP candidate set. In other embodiments according to the present invention, motion IDs are assigned to MVP candidates to follow the trail of motion vectors associated with the MVP candidate. An MVP candidate having a same motion ID as a previous MVP is redundant and can be removed from the MVP candidate set. In yet another embodiment, redundant MVP candidates correspond to one or more of the MVP candidates that cause the second 2N×N or N×2N PU to be merged into a 2N×2N PU are removed from the MVP candidate set. | 04-03-2014 |
20140219357 | METHOD AND APPARATUS FOR DERIVATION OF MOTION VECTOR PREDICTOR CANDIDATE SET - A method and apparatus for deriving a motion vector predictor (MVP) candidate set for a block are disclosed. Embodiments according to the present invention generate a complete full MVP candidate set based on the redundancy-removed MVP candidate set if one or more redundant MVP candidates exist. In one embodiment, the method generates the complete full MVP candidate set by adding replacement MVP candidates to the redundancy-removed MVP candidate set and a value corresponding to a non-redundant MVP is assigned to each replacement MVP candidate. In another embodiment, the method generates the complete full MVP candidate set by adding replacement MVP candidates to the redundancy-removed MVP candidate set and a value is as signed to each replacement MVP candidate according to a rule. The procedure of assigning value, checking redundancy, removing redundant MVP candidate are repeated until the MVP candidate set is complete and full. | 08-07-2014 |
20140241434 | METHOD AND APPARATUS OF MOTION AND DISPARITY VECTOR DERIVATION FOR 3D VIDEO CODING AND HEVC - A method and apparatus for deriving MVP (motion vector predictor) for a block for three-dimensional video coding or multi-view video coding are disclosed. Embodiments according to the present invention replace an unavailable inter-view MV of one neighboring block with a disparity vector derived from depth data of a subset of a depth block corresponding to one neighboring block. A method and apparatus for generating additional candidates for motion vector prediction associated with Merge mode or AMVP (Inter) mode for a block are disclosed. Embodiments according to the present invention generate one or more additional MVP candidates to add to the MVP list if the MVP list size is less than a given list size. The additional MVP candidates are generated either by reducing precision of an available MVP in the MVP list or by adding an offset to the available MVP in the MVP list. | 08-28-2014 |
20150085932 | METHOD AND APPARATUS OF MOTION VECTOR DERIVATION FOR 3D VIDEO CODING - A method and apparatus for deriving MVP (motion vector predictor) for Skip or Merge mode in 3D video coding are disclosed. In one embodiment, the method comprises determining an MVP candidate set for a selected block and selecting one MVP from an MVP list for motion vector coding of the block. The MVP candidate set may comprise multiple spatial MVP candidates associated with neighboring blocks and one inter-view candidate, and the MVP list is selected from the MVP candidate set. The MVP list may consist of only one MVP candidate or multiple MVP candidates. If only one MVP candidate is used, there is no need to incorporate an MVP index associated with the MVP candidate in the video bitstream corresponding to the three-dimensional video coding. Also, the MVP candidate can be the first available MVP candidate from the MVP candidate set according to a pre-defined order. | 03-26-2015 |
20150131724 | METHOD FOR PERFORMING HYBRID MULTIHYPOTHESIS PREDICTION DURING VIDEO CODING OF A CODING UNIT, AND ASSOCIATED APPARATUS - A method and apparatus for performing hybrid multihypothesis prediction during video coding of a coding unit includes: processing a plurality of sub-coding units in the coding unit; and performing disparity vector (DV) derivation when the coding unit is processed by a 3D or multi-view coding tool or performing block vector (BV) derivation when the coding unit is processed by intra picture block copy (IntraBC) mode. The step of performing DV or BV derivation includes deriving a plurality of vectors for multihypothesis motion-compensated prediction of a specific sub-coding unit from at least one other sub-coding/coding unit. The one other sub-coding/coding unit is coded before the corresponding DV or BV is derived for multihypothesis motion-compensated prediction of the specific sub-coding unit. A linear combination of a plurality of pixel values derived from the plurality of vectors is used as a predicted pixel value of the specific sub-coding unit. | 05-14-2015 |
20150181229 | Method and Apparatus of Inter-View Candidate Derivation in 3D Video Coding - A method and apparatus for three-dimensional video coding are disclosed. Embodiments according to the present invention apply the pruning process to one or more spatial candidates and at least one of the inter-view candidate and the temporal candidate to generate a retained candidate set. The pruning process removes any redundant candidate among one or more spatial candidates and at least one of the inter-view candidate and the temporal candidate. A Merge/Skip candidate list is then generated, which includes the retained candidate set. In one embodiment, the temporal candidate is exempted from the pruning process. In another embodiment, the inter-view candidate is exempted from the pruning process. In other embodiments of the present invention, the pruning process is applied to the inter-view candidate and two or more spatial candidates. The pruning process compares the spatial candidates with the inter-view candidate. | 06-25-2015 |
20150189321 | Method of Binarization and Context Adaptive Binary Arithmetic Coding of Depth Coding Syntax - A method for improved binarization and entropy coding process of syntax related to depth coding is disclosed. In one embodiment, a first value associated with the current depth block is bypass coded, where the first value corresponds to the residual magnitude of a block coded by an Intra or Inter SDC mode, the delta magnitude of a block coded by a DMM mode, or a residual sign of a block coded by the Inter SDC mode. In another embodiment, a first bin of a binary codeword is coded using arithmetic coding and the rest bins of the binary codeword are coded using bypass coding. The codeword corresponds to the residual magnitude of a block coded by the Intra or Inter SDC mode, or the delta DC magnitude of a block coded by the DMM mode. | 07-02-2015 |
20150189323 | Method of Three-Dimensional and Multiview Video Coding Using a Disparity Vector - A method and apparatus for a three-dimensional or multi-view video encoding or decoding system are disclosed, where a three-dimensional coding tool relying on a disparity vector are adaptively applied depending on whether the inter-view reference picture pointed by the disparity vector is in the reference list associated with the current slice. The three-dimensional coding tool may correspond to the Inter-View Motion Prediction (IVMP) or View Synthesis Prediction (VSP). If the inter-view reference picture pointed by the DV is not in the current reference list associated with the current slice, the selected three-dimensional coding tool is disabled for the current block. If the inter-view reference picture pointed by the DV is in the current reference list associated with the current slice, the selected three-dimensional coding tool can be applied to the current block. | 07-02-2015 |
20150195570 | Method of Texture Dependent Depth Partition - A method of improved texture-partition-dependent depth partition is disclosed. First, the available texture partitions for a collocated texture block are classified into two or more groups, and a set of candidate depth partitions is determined for each group. In one embodiment, at least one set of the candidate depth partitions contain more than one candidate depth partition and less than all candidate depth partitions. In another embodiment, the collocated texture blocks are classified into two groups, and one of the two groups includes the N×N texture partition and at least another texture partition. In yet another embodiment, the collocated texture blocks are classified into three groups or more. A current depth partition for the current depth block is then selected from a corresponding set of candidate depth partitions according to a corresponding group that a current texture partition associated with the collocated texture block belongs. | 07-09-2015 |
20150201214 | METHOD AND APPARATUS OF DISPARITY VECTOR DERIVATION IN 3D VIDEO CODING - A method and apparatus for three-dimensional video encoding or decoding using the disparity vector derived from an associated depth block are disclosed. The method determines an associated depth block for a current texture block and derives a derived disparity vector based on a subset of depth samples of the associated depth block. The subset contains less depth samples than the associated depth block and the subset excludes a single-sample subset cprresponding to a center sample of the associated depth block. The derived disparity vector can be used as an inter-view motion (disparity) vector predictor in Inter mode, an inter-view (disparity) candidate in Merge mode or Skip mode. The derived disparity vector can also be used to locate a reference block for inter-view motion prediction in Inter mode, inter-view candidate in Merge or Skip mode, inter-view motion prediction, inter-view disparity prediction, or inter-view residual prediction. | 07-16-2015 |
20150201215 | METHOD OF CONSTRAIN DISPARITY VECTOR DERIVATION IN 3D VIDEO CODING - A method for three-dimensional video encoding or decoding are disclosed. In one embodiment, the method constrains the disparity vector (DV) to generate a constrained DV, wherein horizontal, vertical, or both components of the constrained DV is constrained to be zero or within a range from M to N units of DV precision, and M and N are integers. In another embodiment, a derived DV for DV based motion-compensated-prediction is determined from a constrained neighboring block set of the current block. In yet another embodiment, a derived disparity vector is derived to replace an inter-view Merge candidate if the inter-view Merge candidate of the current block is not available or not valid. In yet another embodiment, a DV difference (DVD) or a motion vector difference (MVD) for the current block is determined according to a DV and the DVD/MVP is constrained to be zero or within a range. | 07-16-2015 |
20150201216 | Method and Apparatus of Unified Disparity Vector Derivation for 3D Video Coding - A method and apparatus for three-dimensional video coding or multi-view video coding are disclosed. Embodiments according to the present invention derive a unified disparity vector from depth information for Inter mode and Skip/Direct mode. The unified disparity vector is derived from a subset of depth samples in an associated depth block corresponding to the current block using a unified derivation method. The unified derivation method is applied in Inter mode, Skip mode, or Direct mode when a disparity vector derived from depth data is required for encoding or decoding. The unified disparity vector can also be applied to derive a disparity vector for locating a corresponding block, and thus an inter-view motion vector candidate can be determined for Skip mode or Direct mode. | 07-16-2015 |
20150237324 | Method of Depth Based Block Partitioning - A method of simplified depth-based block partitioning (DBBP) for three-dimensional and multi-view video coding is disclosed. In one embodiment, the derivation of a representative value of a corresponding depth block or a reference texture block in a reference view for generating a segmentation mask and selecting a block partition are unified. In another embodiment, the first representative value, the second representative value, or both are calculated from partial samples of the corresponding depth block or the reference texture block. In yet another embodiment, a first representative value for first samples in a first partitioned block of the corresponding depth block or the reference texture block, and a second representative value for second samples in a second partitioned block of the corresponding depth block or the reference texture block for each of block partition candidates are determined. | 08-20-2015 |
20150281708 | METHOD AND APPARATUS OF SCALABLE VIDEO CODING - A method and apparatus for coding video data using Inter prediction mode or Merge mode in a video coding system are disclosed, where the video data is configured into a Base Layer (BL) and an Enhancement Layer (EL), and the EL has higher spatial resolution or better video quality than the BL. In one embodiment, at least one information piece of motion information associated with one or more BL blocks in the BL is identified. A motion vector prediction (MVP) candidate list or a Merge candidate list for the selected block in the EL is then determined, where said at least one information piece associated with said one or more BL blocks in the BL is included in the MVP-candidate list or a Merge candidate MVP candidate list or the Merge candidate list. The input data associated with the selected block is coded or decoded using the MVP candidate list or the Merge candidate list. | 10-01-2015 |
20150304681 | METHOD AND APPARATUS OF INTER-VIEW MOTION VECTOR PREDICTION AND DISPARITY VECTOR PREDICTION IN 3D VIDEO CODING - A method and apparatus for deriving inter-view candidate for a block in a picture for three-dimensional video coding are disclosed. Embodiments of the present invention derive the inter-view candidate from an inter-view collocated block in an inter-view picture corresponding to the current block of the current picture, wherein the inter-view picture is an inter-view reference picture and wherein the inter-view reference picture is in a reference picture list of the current block. The derived inter-view candidate is then used for encoding or decoding of the current motion vector or disparity vector of the current block. One aspect of the invention addresses re-use of the motion information of the inter-view collocated block. Another aspect of the invention addresses constrains on the inter-view picture that can be used to derive the inter-view candidate. | 10-22-2015 |
20160007036 | METHOD FOR ADAPTIVELY PERFORMING VIDEO DECODING, AND ASSOCIATED ADAPTIVE COMPLEXITY VIDEO DECODER AND ADAPTIVE AUDIO/VIDEO PLAYBACK SYSTEM - A method for adaptively performing video decoding includes: performing decoding complexity management based upon parameter representing processing capability related to the adaptive complexity video decoder, in order to determine whether to reduce decoding complexity of at least one component of a plurality of components within an adaptive complexity video decoder; and selectively reducing decoding complexity of a portion of components within the adaptive complexity video decoder. An associated adaptive complexity video decoder and an associated adaptive audio/video playback system are also provided. In particular, the adaptive complexity video decoder includes a plurality of components and a decoding complexity manager. When needed, the decoding complexity manager delays audio playback of audio information. | 01-07-2016 |
20160057453 | Method and Apparatus of Camera Parameter Signaling in 3D Video Coding - A method of three-dimensional video encoding and decoding that adaptively incorporates camera parameters in the video bitstream according to a control flag is disclosed. The control flag is derived based on a combination of individual control flags associated with multiple depth-oriented coding tools. Another control flag can be incorporated in the video bitstream to indicate whether there is a need for the camera parameters for the current layer. In another embodiment, a first flag and a second flag are used to adaptively control the presence and location of camera parameters for each layer or each view in the video bitstream. The first flag indicates whether camera parameters for each layer or view are present in the video bitstream. The second flag indicates camera parameter location for each layer or view in the video bitstream. | 02-25-2016 |
20160100190 | Method of View Synthesis Prediction in 3D Video Coding - A method and apparatus for three-dimensional or multi-view video encoding and decoding using VSP (view synthesis prediction) with uniform sub-block partition are disclosed. For a current texture block comprising multiple partition blocks, the system derives a single partition decision and partitions each partition block of the current texture block into multiples sub-blocks according to the single partition decision. The VSP processing is then applied to each sub-block to derive the inter-view prediction using VSP. The single partition decision is derived using depth samples of the depth block in a reference view. | 04-07-2016 |
20160112721 | Method of Sub-Prediction Unit Prediction in 3D Video Coding - A method for a three-dimensional encoding or decoding system incorporating restricted sub-PU level prediction is disclosed. In one embodiment, the sub-PU level prediction associated with inter-view motion prediction or view synthesis prediction is restricted to the uni-prediction. In another embodiment, the sub-PU partition associated with inter-view motion prediction or view synthesis prediction is disabled if the sub-PU partition would result in sub-PU size smaller than the minimum PU split size or the PU belongs to a restricted partition group. The minimum PU split size may correspond to 8×8. The restricted partition group may correspond to one or more asymmetric motion partition (AMP) modes. | 04-21-2016 |
Patent application number | Description | Published |
20080253129 | LAMP FIXTURE - An improved lamp fixture with anti-glare function is disclosed, which comprises: a lamp; a light source; and a light-control unit, composed of a semi-Fresnel microstructure and a light-control microstructure; wherein the light source and the light-control unit are mounted on the lamp; and the semi-Fresnel microstructure is used for diffusing/collimating light of the light source while the light-control microstructure is used for controlling the resulting lighting angle. With the aforesaid lamp fixture, not only glare can be prevented, but also uniformity of the lamp fixture is improved. | 10-16-2008 |
20090009868 | DIFFRACTION GRATING RECORDING MEDIUM - A diffraction grating recording medium including a waveguide layer and a grating structure layer is provided. The waveguide layer has a reflective surface and a light incident surface, in which a thickness of the waveguide layer is between 100 nanometers and 2 micrometers, and the reflective surface reflects a light that enters the waveguide layer from the light incident layer. The grating structure layer is disposed on the light incident surface of the waveguide layer, in which the grating structure layer has a plurality of diffractive elements, and the arranging period of the diffractive elements is between 50 nanometers and 900 nanometers. | 01-08-2009 |
20100157595 | LED MODULE AND PACKAGING METHOD THEREOF - A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve. | 06-24-2010 |
20110111539 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method of manufacturing a light emitting diode (LED) package includes disposing at least one LED chip on a first surface of a lead frame, and the LED chip is connected to the lead frame. At least one heat dissipation area corresponding to the LED chip is defined on a second surface of the lead frame. A thermal conductive material is disposed in the heat dissipation area. The thermal conductive material directly comes into contact with the lead frame. A solidification process is performed to solidify the thermal conductive material and form a plurality of heat dissipation blocks. The heat dissipation blocks directly come into contact with the lead frame, and the solidification process is performed at a temperature substantially lower than 300° C. | 05-12-2011 |
20110127563 | DIE-BONDING METHOD OF LED CHIP AND LED MANUFACTURED BY THE SAME - A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C. | 06-02-2011 |
20110156071 | MULTI-STACK PACKAGE LED - A multi-stack package light emitting diode (LED) includes an LED chip, a first fluorescent powder layer, a first optical bandpass filter layer and a second fluorescent powder layer. The LED chip generates an LED light. The first fluorescent powder layer and the second fluorescent powder layer respectively have a first fluorescent powder and a second fluorescent powder. The first fluorescent powder and the second fluorescent powder are excited by the LED light to respectively generate a first excitation light and a second excitation light. The first optical bandpass filter layer allows the LED light and the first excitation light to pass and reflects the second excitation light. A wavelength of the LED light is shorter than a wavelength of the second excitation light. The wavelength of the second excitation light is shorter than a wavelength of the first excitation light. Therefore, the multi-stack package LED improves a light emission efficiency. | 06-30-2011 |
20120168950 | DIE STRUCTURE, MANUFACTURING METHOD AND SUBSTRATE THEREOF - A die structure, a manufacturing method and a substrate, wherein the die structure is constituted by a chip on wafer (COW) and the substrate, and the substrate is formed by stacking and then cutting a plurality of thermal and electrical conductive poles and a plurality of insulating material layers. Moreover, the fabricating of the die structure comprises a plurality of COWs carried on a carrier board is bonded on the substrate, the plurality of COWs are in contact with the plurality of thermal and electrical conductive poles on the substrate, and then the carrier board is removed. After that, a phosphor plate is adhered on the plurality of COWs so as to form a stacked structure. Thereafter, the stacked structure is cut, thus forming a plurality of die structures having at least one COW. | 07-05-2012 |
20120256228 | DIE-BONDED LED - An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics. | 10-11-2012 |
20130005055 | LED MODULE AND PACKAGING METHOD THEREOF - A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve. | 01-03-2013 |
20130139808 | SOLAR HEATING DEVICE - The disclosure relates to a solar heating device comprising at least one incidence collector and a thermal container. The thermal container includes at least one light absorbing recess, wherein at least one of the incidence collectors focuses solar beams on a focal point, which is located inside the light absorbing recess. The inner surface of the light absorbing recess converts the energy of the solar beams into radiant heating. | 06-06-2013 |
20130206135 | APPARATUS FOR SOLAR THERMAL COLLECTION AND SYSTEM OF THE SAME - One embodiment of the present invention discloses an apparatus for solar-thermal collection. The apparatus includes a thermal resistance body; a solar-thermal converter disposed inside the thermal resistance body, wherein the volume of the solar-thermal converter is less than that of the thermal resistance body, so that a space exists between the inner wall of the thermal resistance body and the outer wall of the solar-thermal converter; and at least one opening disposed on the wall of the thermal resistance body, wherein the opening is a through hole only on the wall of the thermal resistance body | 08-15-2013 |
20140175495 | DIE BONDING METHOD AND DIE BONDING STRUCTURE OF LIGHT EMITTING DIODE PACKAGE - A die bonding method and a die bonding structure of a light emitting diode package are provided. The die bonding structure includes a light transmissive adhesive layer formed on a surface of a base plate of a light emitting diode chip, a first metal layer formed on the adhesive layer, a second metal layer formed on a packaging base plate and multiple metallic compound layers. The metallic compound layers are formed by spreading a third metal layer disposed on at least one of the first metal layer and the second metal layer into the first metal layer and the second metal layer after the third metal layer is heated up. The melting points of the first metal layer and the second metal layer are higher than the melting point of the third metal layer. | 06-26-2014 |
Patent application number | Description | Published |
20080238895 | Driving Device of Display Device and Related Method - In order to increase charge time of thin-film transistor (TFT) cells of a display device, the present invention provides a driving device, which includes a timing controller, a column driver module and at least a delay module. The timing controller is used for outputting at least a load signal. The column driver module is coupled to the timing controller and includes at least a column driver. The delay module can be installed in the column driver module or the timing controller, and is used for delaying the load signal for a predetermined time. The load signal is utilized to trigger the plurality of column drivers to output video data provided by a video data source and the video data corresponds to pixels on a panel of the display device. The driving device can use in a cascading, point-to-point or bus-type interfacing architecture to transmit the load signal. | 10-02-2008 |
20090115477 | Circuit Device and Related Method for Mitigating EMI - In order to mitigate electromagnetic interference (EMI), the present invention provides a circuit device for an electronic device including a signal generating unit, a phase adjusting unit and an output interface. The signal generating unit generates a plurality of in-phase signals. The phase adjusting unit is coupled to the signal generating unit and is used for adjusting the plurality of in-phase signals to generate a plurality of output signals, where all or some of the output signals have different phases. The output interface is coupled to the phase adjusting unit and is used for outputting the plurality of output signals to a plurality of signal processing units for image processing. | 05-07-2009 |
20090201277 | Transmission Signal Generating Method and Related Apparatus for a Display Device - The present invention provides a transmission signal generating method for a display device to compensate channel effect. The transmission signal generating method includes using a plurality of signal amplitudes and a first signal direction to generate a plurality of positive levels, using the plurality of signal amplitudes and a second signal direction to generate a plurality of negative levels, and using a plurality of signaling lines for transmission of the pluralities of negative and positive levels. A first positive level and a first negative level both have a minimum signal amplitude of the plurality of signal amplitudes. The amplitude difference of the first positive and negative levels is greater than an amplitude difference of any two neighboring levels of the plurality of negative levels and also the plurality of positive levels. | 08-13-2009 |
20100067611 | TRANSMISSION DEVICE WITH ENHANCED SIGNALS - A transmission device includes a first encoder, a plurality of current sources, a switch module, a second encoder, and a plurality of current enhanced circuits. The first encoder converts an input signal to a first control signal. The switch module is coupled between the plurality of current sources and a plurality of signal lines for controlling the connection of the current sources and the signal lines according to the first control signal to generate a current signal. The second encoder generates a second control signal according to the first control signal or the input signal. The plurality of current enhanced circuits is coupled to the plurality of current sources respectively. The plurality of current enhanced circuits provides an extra current in a predetermined duration to enhance the current signal. | 03-18-2010 |
20130120471 | IMAGE DISPLAY APPARATUS, DISPLAY CONTROL APPARATUS THEREOF, AND SCALER CHIP IMAGE - A display control apparatus applied for an image display apparatus having a plurality of display regions is provided. The display regions are respectively corresponding to a plurality of backlight modules and the luminance of the backlight modules are independently controlled. The display control apparatus includes a backlight control unit. The backlight control unit receives a first image data to generate a plurality of local backlight control signals accordingly. The local backlight control signals are used for controlling the luminance of the backlight modules. The backlight control unit divides the first image data to be a plurality of local image data respectively corresponding to the display regions. Furthermore, the backlight control unit generates one of the local backlight control signals according to one of the local image data respectively. | 05-16-2013 |
20140198089 | IMAGE PROCESSING UNIT, IMAGE PROCESSING APPARATUS AND IMAGE DISPLAY SYSTEM - An image processing unit including an always on circuit block and a non-always on circuit block is provided. When operating under a first operation mode, the non-always on circuit block receives a bias voltage from a power supply unit, so as to perform an image processing operation on an image input signal. When operating under a second operation mode, the non-always on circuit block stops receiving the bias voltage from the power supply unit, so as to stop the image processing operation, and at least a microcontroller of the non-always on circuit block is powered down. One of the always on circuit block and the non-always on circuit block controls the power supply unit to stop supplying the bias voltage to the non-always on circuit block according an event trigger signal, such that the non-always on circuit block enters the second operation mode from the first operation mode. | 07-17-2014 |