Patent application number | Description | Published |
20090067703 | Memory cell and page break inspection - A method of inspecting an array having memory blocks with page breaks disposed between them. The memory array is imaged with a sensor at a magnification such that the memory cell size is a whole integer pixel multiple within the sensor. This creates an array image that is divided into sections. Those sections that include at least a portion of the memory blocks are selected into a candidate image. Pixels of the image within a boundary distance of a horizontal single line of pixels are inspected to determine horizontal edges of the memory blocks to an accuracy of a single pixel. Pixels of the image within a boundary distance of a vertical single line of pixels are inspected to determine vertical edges of the memory blocks to an accuracy of a single pixel. An image of a first memory block is compared on a pixel by pixel basis to an image of a second memory block to determine differences between pixel values in the first and second memory blocks, where the images are created at the same magnification using the imaging sensor. The differences are flagged as potential memory block defects. Images of the page breaks are compared to determine differences between pixel values of the images of the page breaks, and the differences are flagged as potential page break defects. | 03-12-2009 |
20090067722 | Memory cell and page break inspection - A method of inspecting an array having memory blocks with page breaks disposed between them. The memory array is imaged with a sensor at a magnification such that the memory block size is a whole integer pixel multiple within the sensor. This creates an array image that is divided into sections. Those sections that include at least a portion of the memory blocks are selected into a candidate image. Pixels of the image within a boundary distance of a horizontal single line of pixels are inspected to determine horizontal edges of the memory blocks to an accuracy of a single pixel. Pixels of the image within a boundary distance of a vertical single line of pixels are inspected to determine vertical edges of the memory blocks to an accuracy of a single pixel. An image of a first memory block is compared on a pixel by pixel basis to an image of a second memory block to determine differences between pixel values in the first and second memory blocks, where the images are created at the same magnification using the imaging sensor. The differences are flagged as potential memory block defects. Images of the page breaks are compared to determine differences between pixel values of the images of the page breaks, and the differences are flagged as potential page break defects. | 03-12-2009 |
20090290784 | METHODS AND SYSTEMS FOR BINNING DEFECTS DETECTED ON A SPECIMEN - Methods and systems for binning defects detected on a specimen are provided. One method includes comparing a test image to reference images. The test image includes an image of one or more patterned features formed on the specimen proximate to a defect detected on the specimen. The reference images include images of one or more patterned features associated with different regions of interest within a device being formed on the specimen. If the one or more patterned features of the test image match the one or more patterned features of one of the reference images, the method includes assigning the defect to a bin corresponding to the region of interest associated with the reference image. | 11-26-2009 |
20090299681 | METHODS AND SYSTEMS FOR GENERATING INFORMATION TO BE USED FOR SELECTING VALUES FOR ONE OR MORE PARAMETERS OF A DETECTION ALGORITHM - Methods and systems for generating information to be used for selecting values for parameter(s) of a detection algorithm are provided. One method includes without user intervention performing a scan of an area of a wafer using an inspection system and default values for parameter(s) of a detection algorithm to detect defects on the wafer. The method also includes selecting a portion of the defects from results of the scan based on a predetermined maximum number of total defects to be used for selecting values for the parameter(s) of the detection algorithm. The method further includes storing information, which includes values for the parameter(s) of the detection algorithm determined for the defects in the portion. The information can be used to select the values for the parameter(s) of the detection algorithm to be used for the inspection recipe without performing an additional scan of the wafer subsequent to the scan. | 12-03-2009 |
20110164130 | METHODS AND APPARATUS FOR SIMULTANEOUSLY INSPECTING MULTIPLE ARRAY REGIONS HAVING DIFFERENT PITCHES - One embodiment relates to a method of automatically inspecting multiple array regions ( | 07-07-2011 |
20140002632 | DETECTION OF DEFECTS EMBEDDED IN NOISE FOR INSPECTION IN SEMICONDUCTOR MANUFACTURING | 01-02-2014 |
20140153814 | Method and System for Mixed Mode Wafer Inspection - Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells. | 06-05-2014 |
Patent application number | Description | Published |
20100284414 | FLEXIBLE STACKING PORT - A stackable device having a plurality of data ports, wherein each of the data ports is capable of operating as a regular data port or a stacking port. A first set of one or more of the data ports is specified as a first flexible stacking port, and a second set of one or more of the data ports is specified as a second flexible stacking port. Each flexible stacking port can be individually configured to operate as an actual stacking port, if required by the configuration of an associated stack. If a flexible stacking port is not configured to operate as an actual stacking port, then the data port(s) included in the flexible stacking port are available to operate as regular data port(s). | 11-11-2010 |
20100293327 | TCAM Management Approach That Minimize Movements - Methods for efficiently managing a ternary content-addressable memory (TCAM) by minimizing movements of TCAM entries include determining a first node and a second node in the TCAM, determining if there is a free TCAM entry between the first node and the second node, and storing the new entry in the free TCAM entry. Upon determining that a free TCAM entry does not exist between the first node and the second node, further determining a chain of nodes and then determining if there is a free TCAM entry in the chain of nodes. Upon determining that there is a free TCAM entry within the chain of nodes, moving the TCAM entries identified as the nodes in the chain of nodes to generate a free node nearest to the new entry and inserting the new entry in the free node. Moving the TCAM entries identified as the nodes in the chain of nodes preserves the order of the nodes. | 11-18-2010 |
20130215791 | FLEXIBLE STACKING PORT - A stackable device having a plurality of data ports, wherein each of the data ports is capable of operating as a regular data port or a stacking port. A first set of one or more of the data ports is specified as a first flexible stacking port, and a second set of one or more of the data ports is specified as a second flexible stacking port. Each flexible stacking port can be individually configured to operate as an actual stacking port, if required by the configuration of an associated stack. If a flexible stacking port is not configured to operate as an actual stacking port, then the data port(s) included in the flexible stacking port are available to operate as regular data port(s). | 08-22-2013 |
Patent application number | Description | Published |
20140181275 | DEVICE ID ASSIGNMENT IN A SYSTEM OF DEVICES - Techniques for assigning device identifiers in a system of devices are provided. In one embodiment, a master device of the system can maintain a first configuration that specifies a set of links between a first subset of the devices, where the first configuration includes a device identifier for each device in the first subset. The master device can further generate a second configuration that specifies a set of links between a second subset of the devices, where the second configuration is based on a physical topology of the system, and where one or more devices in the second subset are unknown devices that are not associated with a device identifier in the physical topology. The master device can then assign device identifiers to the unknown devices in the second subset by comparing the first configuration with the second configuration. | 06-26-2014 |
20140334494 | HARDWARE HASH TABLE VIRTUALIZATION IN MULTI-PACKET PROCESSOR NETWORKING SYSTEMS - Techniques for virtualizing hardware hash tables in a networking system are provided. In one embodiment, the networking system can maintain a plurality of virtual hash tables corresponding to a plurality of hardware hash tables in the networking system. For each hardware hash table and its corresponding virtual hash table, the networking system can intercept operations directed to the hardware hash table and apply the intercepted operations to the virtual hash table. The networking system can then selectively install and/or uninstall virtual hash table entries to/from the hardware hash table in view of the operations. | 11-13-2014 |
20140341079 | CONFIGURATION VALIDATION IN A MIXED NODE TOPOLOGY - Techniques for validating configuration changes in a mixed node topology are provided. In one embodiment, a device can identify a link to be removed from a topology comprising a plurality of nodes, where the plurality of nodes includes one or more nodes of a first type and one or more nodes of a second type. The device can then determine whether the removal of the link from the topology would require data traffic between two nodes of the first type to pass through a node of the second type. | 11-20-2014 |
20140341080 | BROADCAST AND MULTICAST TRAFFIC REDUCTION IN STACKING SYSTEMS - Techniques for reducing broadcast and multicast traffic in a stacking system are provided. In one embodiment, a master device in the stacking system can automatically determine a minimal set of VLAN associations for stacking links in the stacking system. The minimal set of VLAN associations can avoid unnecessary transmission of broadcast or multicast packets through the system's topology. | 11-20-2014 |
Patent application number | Description | Published |
20110116399 | ANALOG BIAS CONTROL FOR PACKET COMMUNICATION SYSTEMS - Apparatus having corresponding methods and non-transitory computer-readable media comprise an amplifier configured to amplify signals according to a bias current, wherein the signals represent packets of data; a packet module configured to recover the packets of data from the signals amplified by the amplifier; and a control module configured to control the bias current according to one or more characteristics of the packets of data. | 05-19-2011 |
20110285475 | RF Front-End with Integrated T/R Switch - Disclosed is a transmit/receive circuit arrangement wherein a transceiver circuit including a transmit/receive switch is fabricated on an integrated circuit chip. A matching network is wholly disposed off-chip relative to the integrated circuit chip. In embodiments, at least a portion of the matching network is formed off-chip and a portion of the matching network is formed on-chip. | 11-24-2011 |
20120182072 | Self-Biasing Radio Frequency Circuitry - The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit. | 07-19-2012 |
20120276857 | FREQUENCY MULTIPLICATION USING SELF-MIXING - Frequency multipliers having corresponding methods and multifunction radios comprise: N multipliers, wherein N is an integer greater than one; wherein the multipliers are connected in series such that each of the multipliers, except for a first one of the multipliers, is configured to mix a periodic input signal with an output of another respective one of the multipliers; wherein the first one of the multipliers is configured to mix the periodic input signal with the periodic input signal. | 11-01-2012 |
20130271229 | METHOD AND APPARATUS FOR LOCAL OSCILLATOR - Aspects of the disclosure provide a local oscillator (LO) circuit that includes a first phase locked loop (PLL) circuit and a second PLL. The first PLL circuit is configured to generate a first oscillation signal having a first frequency based on a reference signal having a reference frequency. The second PLL circuit is configured to receive the first oscillation signal and generate a second oscillation signal having a second frequency based on the first oscillation signal. | 10-17-2013 |
20140077919 | TRANSFORMER CIRCUITS HAVING TRANSFORMERS WITH FIGURE EIGHT AND DOUBLE FIGURE EIGHT NESTED STRUCTURES - A transformer includes a first loops and second loops. The first loops include a first set of input terminals. The first loops include at least three loops that are conductively coupled to each other in series by first crossovers. The second loops include a first set of output terminals. The second loops include at least three loops that are conductively coupled to each other in series by second crossovers. Each of the second conductive loops is inductively coupled to and nested within a respective one of the first conductive loops. | 03-20-2014 |
20140132349 | Self-Biasing Radio Frequency Circuitry - The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit. | 05-15-2014 |
Patent application number | Description | Published |
20080309186 | MAGNETIC BELT AND ROLLER SYSTEM - A belt and roller system comprising a roller having a permanent magnet sandwiched in between a pair of temporarily magnetic disks with the magnetism of the disks induced by the permanent magnet. For example, each temporarily magnetic disk may be steel. Each pole of the permanent magnet is disposed adjacent to a pole of one of the temporarily magnetic disks resulting in a magnetic attraction to a disk at each pole of the permanent magnet. The opposing magnetic poles of the disks form a magnetic flux circuit by which a temporarily magnetic belt, such as a steel belt is guidable to prevent or reduce deviation which it may have from its roller path. Additional permanent magnetic rollers, as described above, or other rollers known in the art may be combined with the magnetic roller of the present invention to form a gear train about which the belt rotates. | 12-18-2008 |
20110037352 | MOTOR END CAP POSITIONING ELEMENT FOR MAINTAINING ROTOR-STATOR CONCENTRICITY - A motor is provided with a set of end cap guides on the ends of a stator winding assembly to plot the placement of end caps into the correct placement relative to the stator winding assembly so that the rotor assembly is maintained concentric with the stator. The end cap guides may be rings fitting within the winding insulators on the ends of the stator stack or may be integrated as guide segments with the winding insulators to outline an interrupted cylindrical inner surface coinciding with the inner diameter of the stator winding assembly. The guides allow proper positioning of the rotor assembly without increasing the stator stack length. | 02-17-2011 |
20110316364 | MOTOR END CAP WITH INTERFERENCE FIT - A rotary machine (e.g., motor or generator) has end caps with plastic piloting rings that engage a stator's plastic winding frame in an interference fit, so that a rotor seated by bearings in the end caps is properly aligned with the stator. The flexibility of the plastic-to-plastic fit allows looser tolerances in comparison to machining of all-metal end caps, while the average circle of the piloting ring's outer diameter still assures proper concentricity of rotor shaft, bearings, piloting rings and stator. | 12-29-2011 |
20120200249 | TWO-PHASE PERMANENT MAGNET STEP MOTOR FOR MOTION CONTROL - A two-phase permanent magnet step motor comprises a permanent magnet rotor having an equal number Nr of magnetic north and south poles defining a fundamental step angle θ=90°/Nr, such that a number of steps per revolution of the rotor is 360°/θ, and a toothless hybrid stator with windings defining a number Ns of stator poles, with Ns being divisible by four and a ratio Nr/Ns=n/4, n being an odd integer. The permanent magnet rotor may comprise a set of rare-earth magnets. Preferably, Nr is at most 10 (i.e., not more than 20 rotor poles). A method of driving the step motor continuously applies successive current phases to the windings with the motor speed being controllable simply by the step pulse rate. The motor can be micro-stepped at low speeds for smooth operation. | 08-09-2012 |
20140111056 | SMALL STEPPER MOTOR WITH MAXIMUM STATOR TEETH PER POLE - A step motor having a stator constructed with six teeth per pole is achieved for a stator inner diameter (ID) less than one inch (25.4 mm) by a either (1) reducing the pitch angle of the outer teeth of each pole (e.g., to at most 6.8 degrees for a 19 mm stator ID), or (2) narrowing the tooth width of those outer teeth (e.g., to at most 0.0175 inch or 0.444 mm for a 19 mm stator ID), or (3) combination of both. These changes allow sufficient space (i.e., wider than 0.052 inch or 1.321 mm) between poles for passage of a winding needle, even with the extra stator teeth. Although narrowing the pitch angle and reducing the tooth width do sacrifice some torque contribution from each tooth, there still results a net overall gain in torque. | 04-24-2014 |
20140125191 | VIBRATION DAMPENING STRUCTURE FOR STEPPER MOTORS - A stepper motor has electromagnetically driven stator segments facing corresponding rotor segments. In order to reduce vibration of the stator segments, motor body end caps are provided with a stepped annular rim along an inside diameter of a centering sleeve. The stepped rim bears against each axial end of the stator segments, with a radial dimension and an axial dimension bracketing a stator segment end in place. | 05-08-2014 |
20140333159 | HYBRID STEP MOTOR - A stepper motor is provided in which a permanent ring magnet is sandwiched in an outer part of the stator winding assembly located far from the gap between rotor and stator teeth, so that magnetic flux in the gap is dominated by the Ampere-turns of energized stator coils and therefore more easily controlled for reduced vibration at low stepping speeds. The rotor need not contain any permanent disk magnet. If one is provided, it can be completely embedded within the rotor and merely supplement the primary flux from the stator to enhance torque. In most cases, where the rotor lacks any permanent magnet, the motor's axial shaft can have a larger diameter and may, together with the rotor, form a linear actuator. | 11-13-2014 |
Patent application number | Description | Published |
20110305165 | METHOD AND SYSTEM FOR PHYSICAL-LAYER HANDSHAKING FOR TIMING ROLE TRANSITION - Aspects of a method and system for physical-layer handshaking for timing role transition are provided. Prior to changing the timing role of a first Ethernet device, the first Ethernet device may communicate over an Ethernet link to a second Ethernet PHY utilizing a first set of one or more PCS code-groups. In response to a determination to change the timing role of the first Ethernet device, the first Ethernet device may communicate one or more IDLE symbols over the Ethernet link to the second Ethernet device. The IDLE symbol(s) may be generated utilizing a second set of one or more PCS code-groups. The first set of PCS code-group(s) may be mutually exclusive with the second set of PCS code-group(s). In response to detecting a received Ethernet physical layer symbol corresponding to the second set of PCS code-groups, the second Ethernet device may make a determination to change its timing role. | 12-15-2011 |
20110305173 | PHASE AND FREQUENCY RE-LOCK IN SYNCHRONOUS ETHERNET DEVICES - A first PHY may be coupled to a second PHY via a network link. The first PHY may transition from a role of timing master for the network link to a role of timing slave for the network link. During a first time interval subsequent to the transition, the PHYs may communicate half-duplex over the link while the first PHY synchronizes to a transmit clock of the second PHY. During a second time interval, the PHYs may communicate full-duplex while the second Ethernet PHY synchronizes to a transmit clock of the first PHY. Also during the second time interval, the first PHY may determine that the first PHY and the second PHY are synchronized. Subsequent to the determination, the PHYs may begin full-duplex communication of data on the network link. | 12-15-2011 |
20110305248 | CLOCK SELECTION FOR SYNCHRONOUS ETHERNET - An Ethernet PHY may receive an indication from a local timing source that a local clock is suitable for propagation to a link partner. In response, a timer in the Ethernet PHY may be started. In instances that the Ethernet PHY receives, during a time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, the Ethernet PHY may be configured as timing slave. In instances that the Ethernet PHY does not receive, during the time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, Ethernet PHY may be configured as timing master upon the timer reaching the predetermined value. | 12-15-2011 |
20140112176 | POLARITY DETECTION SYSTEM - In the subject system for polarity detection, link initialization between a primary device and a secondary device may be performed in at least two stages, a half-duplex stage when only the primary device transmits initialization signals and any encoded handshaking signals may be set to false, and a full-duplex stage when both devices may transmit initialization signals. The secondary device may perform polarity detection during the half-duplex stage. If the secondary device determines that the polarities of the received signals are reversed, the secondary device may reverse the polarities of any signals subsequently received from, and transmitted to, the primary device. In this manner, the polarities can be corrected for both devices during the half-duplex stage by the secondary device. The secondary device may initiate the full-duplex link initialization stage, during which any handshaking signals may be exchanged, by transmitting signals to the primary device. | 04-24-2014 |
Patent application number | Description | Published |
20090016113 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 01-15-2009 |
20090290430 | Method And Apparatus For Reading And Programming A Non-Volatile Memory Cell In A Virtual Ground Array - A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line. | 11-26-2009 |
20100200904 | GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. | 08-12-2010 |
20100220533 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 09-02-2010 |
20100238731 | PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL - A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage. | 09-23-2010 |
20110286276 | PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line. | 11-24-2011 |
20140104957 | PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line. | 04-17-2014 |
20140159138 | GATE FRINGINE EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. | 06-12-2014 |
Patent application number | Description | Published |
20120182058 | NEGATIVE CHARGE PUMP - A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node. | 07-19-2012 |
20120194263 | CHARGE PUMP AND METHOD OF BIASING DEEP N-WELL IN CHARGE PUMP - A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), and is coupled to at least one capacitor, an input node, and an output node. The input node is arranged to receive an input signal. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the output node, and the DNW is arranged to float for a positive pump operation. | 08-02-2012 |
20120201084 | OPERATING METHODS OF FLASH MEMORY AND DECODING CIRCUITS THEREOF - A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating. | 08-09-2012 |
20120223766 | INTEGRATED CIRCUITS WITH BI-DIRECTIONAL CHARGE PUMPS - Integrated circuits such as memory arrays are coupled to a bi-directional charge pump that includes an input circuit and output circuit, and one or more pump stages coupled between the input circuit and the output circuit of the bi-directional charge pump. The output circuit includes a diode having an input and output and a transistor connected to the output of the diode and a ground potential. The input of the diode is electrically connected to the pump stages in a configuration that allows the charge pump to apply a positive or negative voltage to the memory array or other load. | 09-06-2012 |
20130076335 | INTEGRATED CIRCUIT INCLUDING A VOLTAGE DIVIDER AND METHODS OF OPERATING THE SAME - An integrated circuit includes at least one FLASH memory array and at least one capacitor array disposed over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures each includes a first capacitor electrode disposed over the substrate. A second capacitor electrode is disposed over the first capacitor electrode. A third capacitor electrode is disposed adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is disposed adjacent to second sidewalls of the first and second capacitor electrodes. | 03-28-2013 |
20130106504 | INTEGRATED CIRCUITS WITH CASCODE TRANSISTOR | 05-02-2013 |
20130214853 | INTEGRATED CIRCUITS WITH BI-DIRECTIONAL CHARGE PUMPS - A method includes receiving a first voltage at a first input circuit of a bi-directional charge pump circuit, selectively turning on a first switch of a switching circuit that is coupled electrically to a deep N-well transistor of a first set of one or more intermediate pump stages that are coupled between the first input circuit and a first output circuit, and providing a third voltage from the first output circuit in response to receiving a second voltage at an input of a first diode of the output circuit from the first set of the one or more intermediate pump stages. | 08-22-2013 |
20140197881 | CHARGE PUMP AND METHOD OF BIASING DEEP N-WELL IN CHARGE PUMP - A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation. | 07-17-2014 |
20140285255 | INTEGRATED CIRCUITS HAVING CASCODE TRANSISTOR - An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor. | 09-25-2014 |
20140307510 | INTEGRATED CIRCUIT INCLUDING A VOLTAGE DIVIDER AND METHODS OF OPERATING THE SAME - An integrated circuit includes at least one memory array and at least one capacitor array over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures comprise a first capacitor electrode over the substrate. A second capacitor electrode is over the first capacitor electrode. A third capacitor electrode is adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is adjacent to second sidewalls of the first and second capacitor electrodes. A fifth capacitor electrode is over the substrate and adjacent to the fourth capacitor electrode. | 10-16-2014 |