Patent application number | Description | Published |
20150103584 | CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING - A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage. | 04-16-2015 |
20150206576 | NEGATIVE BIT LINE WRITE ASSIST FOR MEMORY ARRAY - A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided. | 07-23-2015 |
20150206577 | HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY - A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided. | 07-23-2015 |
20150222266 | LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE - A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF). | 08-06-2015 |
20150235681 | PSEUDO-DIFFERENTIAL READ SCHEME FOR DUAL PORT RAM - A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included. | 08-20-2015 |
Patent application number | Description | Published |
20100066849 | ADAPTIVE BINNING METHOD AND APPARATUS - An image processing method and device are described. The method includes the steps of capturing the contents a scene in a first pass ( | 03-18-2010 |
20130100296 | MEDIA CONTENT DISTRIBUTION - A method of distributing media content includes capturing an image of a static media content, detecting at least one feature in the image, seeking a correlation of the image to a reference image using the at least one feature, and identifying at least one region of dynamic media content of the reference image in the image of the static media content. | 04-25-2013 |
20130110818 | PROFILE DRIVEN EXTRACTION | 05-02-2013 |
20130257906 | Generating publication based on augmented reality interaction by user at physical site - Interaction data represents augmented reality interaction by a user using a mobile computing device with physical points of interest at a physical site. A publication is generated based on this interaction data and provided to the user. | 10-03-2013 |
20130259374 | IMAGE SEGMENTATION - In one implementation, an image segmentation system defines a first discriminative classifier and a second discriminative classifier. The first discriminative classifier is associated with a first segment of an object in an image based on a first foreground sample region of the image and a first background sample region of the image. The second discriminative classifier is associated with a second segment of the object based on a second foreground sample region of the image and a second background sample region of the image. The image segmentation system then identifies at least a portion of the first segment using the first discriminative classifier and at least a portion of the second segment using the second discriminative classifier. | 10-03-2013 |
20130343615 | IDENTIFYING A STYLE OF CLOTHING BASED ON AN ASCERTAINED FEATURE - Examples disclose a method executed on a computing device to locate a clothing region within an image to segment into a region of related clothing. Further, the examples provide detecting a feature of the related clothing. Additionally, the examples also disclose determining a style of the related clothing in the region based on the detection of the feature. | 12-26-2013 |
20140201183 | Personalized Content Delivery System and Method - A system and method are provided to deliver personalized content to a user. The system includes a memory for storing computer executable instructions and a processing unit for accessing the memory and executing the computer executable instructions. The computer executable instructions include an engine to apply content extraction rules based on at least one pre-determined delivery schedule to extract content of interest pointed to by links in user-selected sections of at least one content portal of at least one web page regardless of changes in the links in the at least one content portal. The computer executable instructions also include a module to compose the extracted content in a layout format to provide personalized content. The system includes computer executable instructions to deliver the personalized content to at least one pre-determined destination according to the at least one pre-determined delivery schedule. | 07-17-2014 |
20150242522 | ACTIVE REGIONS OF AN IMAGE WITH ACCESSIBLE LINKS - A computer device to generate an image with content and create active regions at locations or coordinates of the image including the content. The computing device associates the active regions with accessible links corresponding to the content. | 08-27-2015 |
Patent application number | Description | Published |
20140134050 | SUPPRESSOR DEVICE - An apparatus for detecting analytes in a liquid sample may include an elongated primary channel through which an ionic species flows, the primary channel extending through a primary channel member, a first regenerant channel through which a regenerant flows, the first regenerant channel extending adjacent to the primary channel and being formed in a first block, a first charged barrier having exchangeable ions capable of passing ions of only one charge, positive or negative, and of blocking bulk liquid flow, the first charged barrier disposed between the primary channel member and the first block for separating the primary channel from the first regenerant channel, and a first sealing member disposed between the first charged barrier and the first block defining the first regenerant channel. | 05-15-2014 |
20140332387 | CURRENT EFFICIENT ELECTROLYTIC DEVICE AND METHOD - A sandwich suppressor in an ion chromatography system in which loosely packed ion exchange resin of low density is disposed in the central sample stream flow channel. Also, a method of using the suppressor is described. | 11-13-2014 |
20150076005 | ELECTROLYTIC FOUR-CHANNEL DEVICE AND METHOD - An electrolytic device includes four channels separated by three charged barriers. The device can be used to suppress an eluent stream containing separated sample analyte ions and/or to pretreat a sample stream containing unseparated analyte ions. | 03-19-2015 |
20150111305 | MULTIELECTRODE ELECTROLYTIC DEVICE AND METHOD - An electrolytic device comprising: a central sample flow channel, first and second regenerant flow channels, first and second charged barriers disposed between said sample flow channel and first and second regenerant flow channels, and pairs of oppositely charged, spaced electrodes disposed in the regenerant flow channels. Also, electrolytic devices with a different electrode configuration are described. Also, methods of using the devices, e.g., for suppression in an ion chromatography system are described. | 04-23-2015 |
20150157976 | GAS-LESS ELECTROLYTIC DEVICE AND METHOD - An electrolytic device, e.g. a suppressor, including at least two flow-through channels separated by a charged membrane barrier, and a catalyst, for combining hydrogen and oxygen gas, together with ion exchange material, disposed in one of the channels. Also, a method for simultaneous electrolysis and catalytic gas elimination in a channel of the device is described. | 06-11-2015 |
Patent application number | Description | Published |
20140097874 | SYSTEMS AND METHODS OF HARMONIC EXTRACTION AND REJECTION - A device includes a first hybrid, where a first input of the first hybrid is coupled to an output of a first amplifier configured to receive a first input signal. A first input of a second hybrid is coupled to an output of a second amplifier configured to receive a second input signal. The device includes a first phase shifter configured to receive the first input signal and a second phase shifter configured to receive the second input signal. An output of the first phase shifter is coupled to an input of a third amplifier, and an output of the third amplifier is coupled to a second input of the second hybrid. An output of the second phase shifter is coupled to an input of a fourth amplifier, and an output of the fourth amplifier is coupled to a second input of the first hybrid. | 04-10-2014 |
20140176217 | SIGNAL COMPONENT REJECTION - A method includes providing a first local oscillator signal having a first duty cycle to a first mixer unit and providing a second local oscillator signal having a second duty cycle to a second mixer unit. At least one of the first duty cycle or the second duty cycle is greater than fifty percent. A frequency of the first local oscillator signal approximately equals a frequency of the second local oscillator signal. The method may also include generating a modulated output signal based on an output signal of the first mixer unit and based on an output signal of the second mixer unit. | 06-26-2014 |
20140179245 | METHOD AND APPARATUS FOR GENERATING IN-PHASE (I) AND QUADRATURE-PHASE (Q) SIGNALS - In a particular embodiment, a method of generating in-phase (I) and quadrature-phase (Q) signals includes generating a first I output signal based on a first I input signal, a second I input signal, a first Q input signal, and a second Q input signal. The method further includes generating a second I output signal based on the first I input signal, the second I input signal, the first Q input signal, and the second Q input signal. A first Q output signal is generated based on the first I input signal, the second I input signal, the first Q input signal, and the second Q input signal. A second Q output signal is generated based on the first I input signal, the second I input signal, the first Q input signal, and the second Q input signal. According to further embodiments, an apparatus is disclosed. | 06-26-2014 |
Patent application number | Description | Published |
20090091648 | Multi-resolution Image Sensor Array with High Image Quality Pixel Readout Circuitry - A configurable, compact multi-resolution linear image sensor array is disclosed. The multi-resolution image sensor array employs a spatial array of photoelectric sites with each site having an image output terminal and a cluster of switched photo-detector elements. To effect a high quality snapshot operation mode for a high pixel count array, a transfer control switch is added bridging each photo-detector element and its correspondingly connected negative input terminal of an operational amplifier to form an active pixel sensor circuit. To minimize a reset kTC noise associated with numerous traditional active pixel sensor circuits, an in-pixel KTC noise-correlated correlated multiple sampling (CMS) circuitry is also proposed to replace an otherwise traditional correlated double sampling (CDS) circuitry. | 04-09-2009 |
20100007775 | Areal Active Pixel Image Sensor with Programmable Row-specific Gain for Hyper-Spectral Imaging - An areal active pixel image sensor (AAPS) with programmable row-specific gain is disclosed for converting hyper-spectral light image into video output signal (VOS). The AAPS includes:
| 01-14-2010 |
20100213355 | Full-width Line Image-sensing Head - A full-width line image-sensing head (FLIH) is proposed for, expressed in X-Y-Z coordinates, converting a pixel line image (PLI) of length L | 08-26-2010 |
20110019044 | Time Delay Integration Based MOS Photoelectric Pixel Sensing Circuit - A time delay integration (TDI) based MOS photoelectric pixel sensing circuit (TDIPSC) is proposed. The TDIPSC includes multi-element photoelectric pixel sensor (MEPS) having sub-pixel sensor elements SPSE | 01-27-2011 |
20110149132 | Wafer-scale Cluster Image Sensor Chip and Method with Replicated Gapless Pixel Line and Signal Readout Circuit Segments - A multi-pixel row wafer-scale cluster image sensor chip (WCISC) is proposed. Expressed in X-Y-Z coordinates with its pixel rows along X-axis, the WCISC converts areal image frame (IMFM) into areal image frame signal (AIFS). The WCISC includes multiple imaging pixel rows PXRW | 06-23-2011 |
20130208110 | System and method for monitoring multiple targets using a single camera - Techniques to monitor multiple targets with a single camera are disclosed. In one embodiment, an image sensor is provided with two or more readout circuits, each operating independently and is designed to read out charges from a designated area of the image sensor. When two or more designated sensing areas in the image sensor are being focused onto different objects and read out respectively, such an image sensor is capable of monitoring multiple targets. When placed in traffic surveillance, a camera equipped with such an image sensor is able to monitor multiple forward and backward lanes in near or far field. Further with the control of the designated areas, different resolutions of the images may be produced. | 08-15-2013 |
20130208154 | High-sensitivity CMOS image sensors - Designs of image sensors with subpixels are disclosed. According to one aspect of an image sensor in one embodiment, subpixels within a pixel are designed without significantly increasing the cell or pixel area of the pixel. The readouts from the subpixels are accumulated to increase the sensitivity of the pixel without increasing the area of the image sensor. According to another aspect of the image sensors in the present invention, some subpixels within a pixel are respectively coated with filters, each designed for a frequency range. Thus the frequency response of a CMOS image sensor can be enhanced significantly according to application. | 08-15-2013 |
20140022425 | Multi-band sensors - Designs of multi-band sensor array to generate multi-spectral images are disclosed. According to one aspect of the present invention, a multi-band sensor array includes one linear sensor configured to sense a scene in panchromatic spectrum to produce a panchromatic (PAN) sensing signal, and four color-band linear sensors to sense the same scene in different color bands to produce respective sensing signals. These sensors are packaged in a single module that is disposed on a single optical plane when used to scan a scene. A multi-spectral image is produced by combining these sensing signals. Further a unique packaging of the sensor array and a combination of soft and hard PCB are disclosed to withstand extremes in a harsh environment. | 01-23-2014 |
Patent application number | Description | Published |
20130121133 | GROUP COMMUNICATIONS WITH MIXED CASTING SERVICES - The disclosure is directed to group communications in a mixed casting services wireless communication system. An embodiment detects a loss of multicast coverage at a user equipment (UE), notifies a server of the loss of multicast coverage, wherein the server is configured to provide a desired multicast communication, and requests that communications related to the desired multicast communication be conducted on a unicast service using application layer signaling independent of link layer signaling. | 05-16-2013 |
20130121226 | GROUP COMMUNICATIONS OVER EVOLVED MULTIMEDIA BROADCAST/MULTICAST SERVICES - The disclosure is directed to group communications over evolved multimedia broadcast/multicast services (E-MBMS). An embodiment identifies a schedule for an indicator on a broadcast/multicast medium of a first multicast media on a multicast flow, wherein the indicator is configured to identify a location of data on the broadcast/multicast medium and to identify a presence of the data on the multicast flow, binds application layer paging, an application layer wake up mechanism, or a power saving mechanism to the schedule for the indicator on the multicast flow, wakes from a sleep mode to monitor the indicator to determine availability of the first multicast media based on the indicator, tunes to the first multicast media if the first multicast media is available, and returns to the sleep mode, if the first multicast media is not available. | 05-16-2013 |
20130121313 | ADJUSTING A BUNDLING FACTOR FOR A COMMUNICATION SESSION BASED ON WHETHER AN ACCESS NETWORK SUPPORTS HEADER COMPRESSION AND DYNAMICALLY SETTING A DE-JITTER BUFFER SIZE BASED ON A BUNDLING FACTOR - In an embodiment, a user equipment (UE) determines to originate a communication session, and the UE further determines whether an access network serving the UE supports header compression. Based on the header compression determination, the UE establishes on a given bundling factor (BF). The UE transmits a first set of media packets to a server during the communication session, the first set of media packets each including a first number of media frames based on the given BF. The server determines target BF(s) for target UE(s) and determines whether to modify the given BF based on the target BF(s). Based on these determinations, the server transmits a second set of media packets either unmodified from the first stream of data packets, or modified based on the target BF(s). The target UE(s) receive the second stream of data packets and set a de-jitter buffer size based on the associated BF. | 05-16-2013 |
20130170352 | APPLICATION LAYER ACCESS CHANNEL CONGESTION AVOIDANCE IN GROUP COMMUNICATIONS OVER BROADCAST/MULTICAST SERVICES - The disclosure is directed to prioritizing call announce response in a broadcast/multicast communication system. An embodiment establishes a first priority for response based on assigning each user equipment (UE) a first random delay for response to a first call announce, responds to the first call announce using the first random delay, and determines a second priority for response to a subsequent call announce based on an elapsed time that each UE is present in a multicast area. | 07-04-2013 |
20130170357 | APPLICATION-SERVER-ASSISTED PREEMPTIVE MULTICAST BEARER ESTABLISHMENT FOR REAL-TIME LOW-LATENCY APPLICATIONS - The disclosure is directed to preemptively establishing a multicast bearer. An embodiment determines whether adding a multicast session to a plurality of multicast bearers will exceed a high bandwidth threshold, requests setup of a new multicast bearer if adding the multicast session will exceed the high bandwidth threshold, and hosts the multicast session on an available one of the plurality of multicast bearers or the new multicast bearer. | 07-04-2013 |
Patent application number | Description | Published |
20100096170 | CIRCUIT BOARD AND LAYOUT METHOD THEREOF - A circuit board includes a signal plane and a ground plane. The signal plane is configured to have a plurality of signal traces arranged thereon. Each of the signal traces includes a plurality of straight line segments. Each line segment extends along a path different from the others. The ground plane includes a plurality of tiles connected in an array. Each tile is formed by ground traces. The straight line segments of each signal trace mapped on the ground plane are arranged at an angle relative to any one ground trace of the tiles. The angle is defined within a range determined by one of ground traces of a tile and an adjacent diagonal line of the tile. A method for laying out such a circuit board is also provided. | 04-22-2010 |
20110127069 | PRINTED CIRCUIT BOARD AND LAYOUT METHOD THEREOF - A printed circuit board layout method includes the following steps. A printed circuit board with a signal layer, and a pair of differential transmission lines positioned on the signal layer is provided. A first distance is determined, when the distance between the pair of differential transmission lines is greater or less than the first distance, an eye width and an eye height of an eye diagram obtained at output terminals of the pair of differential transmission lines increases. A second distance less than the first distance is set between the pair of differential transmission lines which makes the eye width and the eye height meet requirement of the differential transmission lines for the eye diagram. | 06-02-2011 |
20110273240 | PRINTED CIRCUIT BOARD AND LAYOUT METHOD THEREOF - A printed circuit board layout method includes the following steps. A printed circuit board with a signal layer and a pair of differential transmission lines positioned on the signal layer is provided. A first distance is determined; when the distance between the pair of differential transmission lines is greater than the first distance, an eye width and an eye height of an eye diagram nearly remains the same. When a distance between the pair of differential transmission lines is less than the first distance, an eye width and an eye height of an eye diagram decreases. A second distance that is less than the first distance is set between the pair of differential transmission lines which makes the eye width and the eye height greater than a predetermined value, and which is determined by a Far End Crosstalk (FEXT) on the eye diagram when the pair differential transmission lines transmit signals. | 11-10-2011 |
20110304977 | ELECTRONIC DEVICE ENCLOSURE WITH ANTI-EMI HOLES - An electronic device enclosure for suppressing Electro-Magnetic Interference (EMI) includes a first plate defined on a first plane, a second plate defined on a second plane and a number of polygonal holes defined in the first plate at an angle of orientation. The second plane is substantially perpendicular to the first plane. The angle of orientation of the number of polygonal holes in the first plate is set according to a number of maximum dimensions in a direction substantially perpendicular to the second plane. The angle of orientation is defined such that there are a minimum number of maximum dimensions. | 12-15-2011 |
20120267148 | CIRCUIT BOARD - A circuit board includes a signal plane and a ground plane. The signal plane is configured to have a plurality of signal traces. Each of the signal traces includes a plurality of straight line segments. Each line segment extends along a path different from the others. The ground plane includes a plurality of tiles connected in an array. Each tile is formed by ground traces. The straight line segments of each signal trace mapped on the ground plane are arranged at an angle relative to any one ground trace of the tiles. The angle is defined within a range determined by one of ground traces of a tile and an adjacent diagonal line of the tile. A method for laying out such a circuit board is also provided. | 10-25-2012 |
20130098661 | PRINTED CIRCUIT BOARD AND LAYOUT METHOD THEREOF - A printed circuit board includes a signal layer having a pair of differential transmission lines thereon. An eye width and an eye height of an eye diagram obtained at output terminals of the pair of differential transmission lines are variable according to a distance between the pair of differential transmission lines. The eye width and the eye height of the eye diagram are at minimum values when the distance between the pair of differential transmission lines is at a first distance. The eye width and the eye height meet requirements of the pair of differential transmission lines for the eye diagram when the distance between the pair of differential transmission lines is set at a second distance, the second distance is less than the first distance. | 04-25-2013 |
20130154680 | SIGNAL TRANSMISSION LINES WITH TEST PAD - A pair of signal transmission lines includes an aggressor line, a victim line, a first test pad, and a second test pad. The first test pad is in the aggressor line. The victim line is parallel to the aggressor line. A second test pad is in the victim line. The first test pad, on the aggressor line, is misaligned with the second test pad, on the victim line, to reduce the incidence and amplitude of any crosstalk generated. | 06-20-2013 |
20130162364 | PRINTED CIRCUIT BOARD - A printed circuit board includes an outer signal layer, a first ground layer, a first ground layer located below the outer signal layer, an inner signal layer located below the first ground layer, an second ground layer located below the inner signal layer, and a first differential signal transmission pair and a second differential signal transmission pair laid on the outer signal layer and the inner signal layer. A value h is equal to a distance between the inner signal layer and its closest ground layer. A distance between the first pair and the second pair is not more than h×3. | 06-27-2013 |
20140140186 | CIRCUIT BOARD WITH LOW SIGNAL FAR END CROSSTALK - A circuit board includes at least four signal lines. The at least four signal lines are substantially parallel to each other and includes two first adjacent signal lines and two second adjacent signal lines adjacent to the first adjacent signal lines. A polarity of signals transmitted by the two first adjacent signal lines is opposite to a polarity of signals transmitted by two second adjacent signal lines. | 05-22-2014 |
20140289688 | METHOD AND SYSTEM FOR TESTING DIRECT CURRENT TRANSMISSION LAYOUT OF PRINTED CIRCUIT BOARD - An system for testing direct current (DC) layout of a printed circuit board, the system includes a layout information obtaining module, a rule loading module, a test script building module, a script executing module, and a report generating module. The layout information obtaining module obtains layout information of the printed circuit board. The rule loading module load DC transmission rules. The test script building module builds a DC transmission test scrip of the printed circuit board according to one of the DC transmission rules. The script executing module executes the DC transmission test script to determine whether the layout information of the printed circuit board complies with the one of the DC transmission rules. The report generating module generates a DC transmission testing report depicting whether the layout information of the printed circuit board complies with the one of the DC transmission rules and displays the testing report. | 09-25-2014 |
20140290981 | PRINTED CIRCUIT BOARD - A printed circuit board includes a board body, a signal transmission line laid in the board body, and a metal bracket attached to the board body. The metal bracket tightly abuts side surfaces of the board body and shields electromagnetic interference of the signal transmission line when the signal transmission line transmits high-speed differential signals. | 10-02-2014 |
20140313687 | PRINTED CIRCUIT BOARD ASSEMBLY - A printed circuit board assembly comprises a PCB and a shielding structure. The PCB comprises a top surface, a bottom surface, a first side surface, a second side surface, a third side surface, and a fourth side surface. A signal transmission line is laid in the top surface. The shielding structure is attached to the PCB and securely contacts the first side surface, the second side surface, the third side surface, and the fourth side surface. Edges of the top surface and the bottom surface are configured to shield EMI in the signal transmission line when transmitting high-speed differential signals. | 10-23-2014 |
20140317587 | COMPUTING DEVICE AND METHOD FOR TESTING LAYOUT OF POWER PIN OF CHIPSET ON CIRCUIT BOARD - A testing system for testing a layout of a power pin of a chipset on a circuit board includes a layout information obtaining module, a power pin sorting module, a transmission line sorting module, a transmission line length calculating module, and a report generating module. The layout information obtaining module obtains layout information of the printed circuit board. The power pin sorting module sorts the power pin from a number of pins of the chipset. The transmission line sorting module sorts transmission lines that are connected to the power pin and are located on outer layers of the printed circuit board. The transmission line length calculating module calculates a total length of the transmission lines sorted by the transmission line sorting module and compares the total length with a threshold length. The report generating module generates a testing report indicating whether or not the power pin is qualified. | 10-23-2014 |