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| 20100109772 | SIGMA DELTA CLASS D POWER AMPLIFIER AND METHOD THEREOF - A sigma delta class D power amplifier includes a loop filter, a quantizer, and an output stage. The quantizer is coupled to the loop filter and quantifies an error signal according to levels of two reference signals to output a pair of mean signals, wherein different logic combinations of the mean signals belong to one of three quantum states. The output stage is coupled to the quantizer and outputs a corresponding output signal according to the different quantum states to drive a load, wherein a driving current of the output signal belongs to one of the three driving states which include at least a steady state with no current of a power amplifier. | 05-06-2010 |
| 20100123518 | POWER AMPLIFIER AND MODULATOR THEREOF - A power amplifier including a loop filter, a frequency generator, a quantizer, and an output stage module is provided. The frequency generator outputs a signal with a reference frequency to the loop filter, and includes a logic circuit, a current array, and a dummy load. The dummy load representing a load circuit in the loop filter is coupled to the current array. An equivalent impedance of the dummy load is proportioned to an equivalent impedance of the load circuit. The current array outputs the signal and a dummy signal to the loop filter and the dummy load, respectively, according to a logic signal. By using the frequency generator to modulate the frequency automatically, an impact on the power amplifier caused by passive devices therein due to process variationscan be reduced. | 05-20-2010 |
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| 20140073278 | RSSI estimation based on VGA control and threshold detection - A circuit for RSSI estimation includes a cascaded chain of variable gain amplifier stages, a threshold detector configured to output an indication signal according to a comparison of output of the cascaded chain of variable gain amplifier stages with a predetermined threshold, and an automatic gain controller configured to adjust gain of at least one variable gain amplifier of the cascaded chain of variable gain amplifier stages according to the indication signal. Each stage may include a switch module configured to electrically connect or disconnect an input of the variable gain amplifier of the at least one variable gain amplifier stage to/from an output of a previous variable gain amplifier stage according to a switch control signal. | 03-13-2014 |
| 20150063504 | Digital Receiver System Activated by RSSI Signal - A digital receiver includes a radio frequency analog front end, a digital processing unit, a plurality of cascaded amplifier stages configured to receive output of the radio frequency analog front end, a first analog to digital converter configured to convert an analog signal output from the plurality of cascaded amplifier stages into a digital signal output to the digital processing unit, a first received signal strength indicator unit configured to receive outputs of each of the plurality of cascaded amplifier stages and output signal to the digital processing unit, a second received signal strength indicator unit configured to receive output of at least one amplifier stage in the plurality of cascaded amplifier stages, and a received signal strength indicator detection unit configured to activate and to deactivate digital units according to a comparison of output from the second received signal strength indicator unit to a predetermined threshold. | 03-05-2015 |
| 20150263670 | Frequency Modulation Based on Two Path Modulation - A two path direct frequency modulation system is disclosed. The system includes a Varactor, a voltage-controlled oscillator (VCO) calibration capacitor bank including a first plurality of switchable capacitors, and a frequency deviation capacitor bank including a second plurality of switchable capacitors. The method includes switching on or off a number of the first plurality of switchable capacitors to obtain a desired frequency band and determining number of cycles within a first predetermined time to obtain a first count, switching on or off a number of the first plurality of switchable capacitors or of the second plurality of switchable capacitors to change the desired frequency band and determining number of cycles within a second predetermined time to obtain a second count, and modulating a data signal by switching on or off a switchable capacitors of the second plurality of switchable capacitors according to the first and the second count. | 09-17-2015 |
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| 20100315843 | METHOD OF DETECTION FOR OUTPUT SHORT CIRCUIT OF A FLYBACK POWER SUPPLY - Disclosed are methods of detection for output short circuit of a flyback power supply, which detect the current sense signal provided by a current sense resistor serially connected to a power switch of the flyback power supply, and thus quickly identify whether or not the flyback power supply suffers output short circuit. | 12-16-2010 |
| 20110012554 | APPARATUS AND METHOD FOR IMPROVING THE STANDBY EFFICIENCY OF A CHARGER, AND ULTRA LOW STANDBY POWER CHARGER - A charger has two pins for connecting with a battery therebetween, and an apparatus and method are proposed to determine to wake up or turn off the charger according to a voltage or a current detected from the two pins, to reduce the standby power consumption of the charger. | 01-20-2011 |
| 20120086480 | CIRCUIT AND METHOD FOR SUB-HARMONIC ELIMINATION OF A POWER CONVERTER - A circuit and method are provided for a power converter to select one from a plurality of current limit signals as a final current limit signal according to the present duty ratio of a power switch for the pulse width modulation of the next cycle, so that the duty ratio of the power switch in the next cycle is prevented from acute variation to eliminate sub-harmonic which otherwise may happen. | 04-12-2012 |
| 20120194162 | PULSE WIDTH MODULATION CONTROLLER AND METHOD FOR OUTPUT RIPPLE REDUCTION OF A JITTERING FREQUENCY SWITCHING POWER SUPPLY - A pulse width modulation controller and method for output ripple reduction of a jittering frequency switching power supply detect the current of a power switch of the switching power supply to generate a current sense signal, and adjust the gain or the level of the current sense signal according to the switching frequency of the power switch to adjust the on time of the power switch, to reduce the output ripple of the switching power supply caused by the jittering frequency of the switching power supply. | 08-02-2012 |
| 20120194227 | JITTERING FREQUENCY CONTROL CIRCUIT AND METHOD FOR A SWITCHING MODE POWER SUPPLY - A jittering frequency control circuit and method for a switching mode power supply enlarge the uttering frequency range of the switching frequency of the switching mode power supply when the switching mode power supplier enters a frequency reduction mode, to improve the electro-magnetic interference of the switching mode power supply operating with the frequency reduction mode. | 08-02-2012 |
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| 20130164127 | FAN STRUCTURE AND A BEARING MODULE THEREOF - A fan structure at least includes a bearing module and a rotor, the bearing module includes a hollow cylinder body, a bearing, a limiting member and a blocking member. The hollow cylinder body comprises a ring wall and an accommodating hole, wherein the bearing, the limiting member and the blocking member are disposed at the accommodating hole in sequence. The ring wall comprises an inner ring wall and a limiting slot recessed from the inner ring wall. The blocking member comprises a body portion and a blocking portion extendedly formed at the body portion, the body portion embedded into the limiting slot, and the blocking portion is in contact against the limiting member. A rotating shaft of the rotor penetrated through the limiting member and the bearing, and a plurality limiting plates of the limiting member inserted into a ring slot of the rotating shaft. | 06-27-2013 |
| 20140017077 | FAN STRUCTURE AND IMPELLER THEREOF - A fan structure at least includes a cap, an impeller, a bearing and a fixing shaft, wherein the cap comprises a bottom portion, a body and an accommodating space. The impeller comprises a hub and a coupling base having a ring wall and an accommodating slot. The bearing couples to the accommodating slot, and the fixing shaft penetrates through an axial hole of the bearing. The ring wall of the coupling base comprises at least one guidance hole exposing the fixing shaft. The guidance hole is in communication with the accommodating space and the accommodating slot. The lubricants can be collected inside the accommodating space of the cap through the guidance of the guidance hole to prevent the lubricants from leakage when the impeller is in rotation. | 01-16-2014 |
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| 20130068276 | SOLAR BATTERY MODULE AND MANUFACTURING METHOD THEREOF - A solar battery module includes a substrate, a plurality of first striped electrodes separately formed on the substrate, a plurality of striped photoelectric transducing layers respectively formed on the corresponding first striped electrode and the substrate wherein parts of the first striped electrode are exposed, a plurality of second striped electrodes respectively formed on the corresponding striped photoelectric transducing layer, and a plurality of conductive layers respectively formed on a side of the corresponding second striped electrode and the first striped electrode adjacent to the side, and not contacting the other second striped electrode. | 03-21-2013 |
| 20130074772 | THIN-FILM SOLAR CELL MANUFACTURING SYSTEM - A manufacturing system for thin-film solar cell is disclosed in the present invention. The manufacturing system includes a chamber, a boat disposed inside the chamber, a solid substrate with a first precursor which has a first I B group and III A group, and a flexible substrate with a second precursor which has a second I B group and III A group, a gas controller for pouring reactant gas, and a heater for increasing the temperature of the chamber, so that the reactant gas reacts to the first precursor and the second precursor to form a chalcopyrite structure. | 03-28-2013 |
| 20130098421 | FLEXIBLE SOLAR BATTERY MODULE AND RELATED MANUFACTURING METHOD - A flexible solar battery module includes a flexible insulating base and a plurality of solar batteries separately disposed on the flexible insulating base. The solar battery includes a substrate disposed on the flexible insulating base, a first electrode disposed on the substrate, a photoelectric transducing layer disposed on the first electrode and exposing parts of the first electrode, and a second electrode disposed on the photoelectric transducing layer. The flexible solar battery module further includes an insulating layer disposed on the exposed first electrode of each solar battery and the exposed flexible insulating base between the adjacent solar batteries, and an auxiliary electrode disposed on the second electrode of each solar battery and the exposed first electrode of the adjacent solar battery for setting the plurality of solar batteries in a series connection. | 04-25-2013 |
| 20130130432 | RAPID THERMAL PROCESSING SYSTEM AND SULFIDATION METHOD THEREOF - A rapid thermal processing system includes a rapid thermal processing furnace, a back electrode substrate, and a cover. The rapid thermal processing furnace includes a reaction chamber and a heating device. The heating device is capable of generating heat energy. The back electrode substrate is adapted to dispose in the reaction chamber and has a precursor layer and a selenium layer formed on the precursor layer. The cover is disposed at a position corresponding to the selenium layer on the back electrode substrate and has a sulfur in solid form formed thereon, so as to make the sulfur in solid form opposite to the selenium layer. After the sulfur in solid form absorbs the heat energy generated by the heating device, the sulfur in solid form reacts with the selenium layer and the precursor layer to form a photoelectric transducing layer. | 05-23-2013 |
| 20130133720 | SOLAR BATTERY MODULE AND MANUFACTURING METHOD THEREOF - A solar battery module includes a substrate, striped metal electrode layers formed alternately on the substrate along a first direction, striped photoelectric transducing layers, striped transparent electrode layers, and electrode lines. Each striped photoelectric transducing layer is formed on the striped metal electrode layer and the substrate along the first direction. Each striped transparent electrode layer is formed on the striped metal electrode layer and the striped photoelectric transducing layer along the first direction. The striped transparent electrode layers and the striped metal electrode layers are in series connection along a second direction. The electrode lines are formed alternately on each striped transparent electrode layer or between each striped photoelectric transducing layer and each striped transparent electrode layer along the second direction. A width of each electrode line is less than an interval between the striped transparent electrode layer and the adjacent striped metal electrode layer. | 05-30-2013 |
| 20130236844 | SUBSTRATE CARRIER AND SELENIZATION PROCESS SYSTEM THEREOF - A substrate carrier is used for carrying a plurality of back electrode substrates into a furnace. Each back electrode substrate has a precursor layer formed thereon. The furnace is used for providing a process gas to react with the precursor layer, so as to form a photoelectric transducing layer on each back electrode substrate. The substrate carrier includes a heat-resistant metal frame and a first protective layer. The heat-resistant metal frame has a plurality of slots for supporting the plurality of back electrode substrates. The first protective layer is formed on the heat-resistant metal frame for preventing a chemical reaction of the heat-resistant metal frame with the process gas. | 09-12-2013 |
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| 20130187265 | PACKAGE STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor structure comprises a carrier, a plurality of under bump metallurgy layers, a plurality of copper containing bumps and an organic barrier layer, wherein the carrier comprises a protective layer and a plurality of conductive pads, mentioned protective layer comprises a plurality of openings, the conductive pads exposed by the openings, mentioned under bump metallurgy layers being formed on the conductive pads, mentioned copper containing bumps being formed on the under bump metallurgy layers, each of the copper containing bumps comprises a top surface and a ring surface in connection with the top surface, mentioned organic barrier layer having a first coverage portion, and mentioned first coverage portion covers the top surface and the ring surface of each of the copper containing bumps. | 07-25-2013 |
| 20130214407 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 08-22-2013 |
| 20130214419 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances. | 08-22-2013 |
| 20130249081 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer. | 09-26-2013 |
| 20130249089 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion. | 09-26-2013 |
| 20130252374 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 09-26-2013 |
| 20130256882 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer. | 10-03-2013 |
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| 20120313229 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound. | 12-13-2012 |
| 20120319258 | STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF - A method of forming a conductive pattern on a metallic frame for manufacturing a stack frame for electrical connections is disclosed. In one embodiment, a recess is formed in the metallic frame and a conductive element is bonded in the recess to make a stack frame for electrical connections. In another embodiment, the process can be performed on both top surface and bottom surface of metallic frame to make another stack frame for electrical connections. In yet another embodiment, a package structure and a manufacturing method of forming a conductive pattern on a lead frame for electrical connections are disclosed. | 12-20-2012 |
| 20150102475 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound. | 04-16-2015 |
| 20150348801 | STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF - A method for forming a conductive structure is disclosed, the method comprising the steps of: forming a metallic frame having a plurality of metal parts separated from each other; forming an insulating layer on the top surface of the plurality of metal parts; and forming a conductive pattern layer on the insulating layer for making electrical connections with at least one portion of the plurality of metal parts. | 12-03-2015 |
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| 20140179175 | ASYMMETRICAL CONTACT TERMINAL AND FABRICATION METHOD OF THE SAME - An asymmetrical contact terminal includes a root portion and at least one first branch and at least one second branch which are spaced apart. The first branch has a first arm portion and a first tip, and the second branch also has a second arm portion and a second tip. The first branch further has a protrusion selectively connects the second arm portion for deforming the force distribution and enhancing the engagement between the contact terminal and an associated housing. The instant disclosure also discloses a fabrication method for making the same. | 06-26-2014 |
| 20140273651 | COUPLING TERMINAL STRUCTURE AND ELECTRICAL CONNECTOR USING THE SAME - The present invention discloses a coupling terminal structure and electrical connector using the same. The coupling terminal structure comprises: at least a pair of first terminal and second terminal, wherein the first terminal includes a first contact portion, a first neck portion and a first extension portion, the second terminal includes a second contact portion, a second neck portion and a second extension portion. The first contact portion is disposed aside to the second contact portion at a first distance, while the first extension portion is disposed aside to the second extension portion at a second distance. The first distance is greater than the second distance, thereby forming an electromagnetic coupling effect between the first extension portion and the second extension portion to provide better shielding and decrease interference between and within terminals. | 09-18-2014 |
| 20140273656 | ELECTRICAL CONNECTOR AND TERMINAL NETWORK THEREOF - The present invention discloses a terminal network of an electrical connector, comprising: a terminal array used to form on a connector surface. The terminal array includes a plurality of terminal rows alternately arranged, wherein each of the terminal rows includes at least one signal transmitting unit and at least one ground unit. Each of the signal transmitting unit and the ground unit is arranged in an alternative form with each other in the same row. Each of the signal transmitting unit and the ground unit in one row are respectively aligned to the ground unit and signal transmitting unit in an adjacent row. By means of the terminal array, crosstalk between or within terminals can be decreased while the use of the ground unit is decreased and the use of the signal transmitting unit is increased. | 09-18-2014 |
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| 20140295629 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses. | 10-02-2014 |
| 20140349467 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface. | 11-27-2014 |
| 20150087126 | METHOD OF FABRICATION TRANSISTOR WITH NON-UNIFORM STRESS LAYER WITH STRESS CONCENTRATED REGIONS - A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer. | 03-26-2015 |
| 20150236158 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MADE THEREBY - A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8. | 08-20-2015 |
| 20150263170 | SEMICONDUCTOR PROCESS FOR MODIFYING SHAPE OF RECESS - A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface. | 09-17-2015 |
