Lin, Hsin-Chu City
An-Pang Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080297694 | BACKLIGHT MODULE OF REDUCING LIGHT LEAKAGE FOR USE IN A LIQUID CRYSTAL DISPLAY DEVICE - A backlight module includes a frame, a plurality of light tubes disposed on the frame, an optical sheet, a first light tube fixing component disposed on a side of the frame, and a second light tube fixing component disposed on a bottom surface of the frame. The frame includes a plurality of holes defined on a bottom surface of the frame. The first light tube fixing component is used for fixing the plurality of light tubes on the frame. The first light tube fixing component includes light proof member and a light reflective component. The light proof member is used for blocking light from the plurality of light tubes. The light reflective component is used for reflecting light from the plurality of light tubes toward the optical sheet. The light proof member and the light reflective component are integrally formed. The second light tube includes a substrate plate, a plurality of supporting holders disposed on a first side of the substrate plate, and a plurality of engaging portions disposed on a second side opposite to the first side. Each engaging portion is made of light proof materials and corresponds to one of the plurality of holes. The substrate plate, the plurality of supporting holders, and the plurality of engaging portions are integrally formed. | 12-04-2008 |
Chia-Chi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20090187866 | Electrical Parameter Extraction for Integrated Circuit Design - A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver. | 07-23-2009 |
20140099582 | Smart Subfield Method For E-Beam Lithographny - The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved. | 04-10-2014 |
Chih-Hsin Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20090153479 | Positioning Device of Pointer and Related Method - A positioning device for positioning an aim point of a pointer on a screen includes a screen, a pointer and a processor. The screen is utilized for displaying a plurality of characteristic points having already-known coordinate values. The pointer is utilized for forming an aim point, and includes an image acquisition unit for acquiring an image and a calculation unit for calculating image coordinate values of the plurality of characteristic points in the image. The processor is coupled to the screen and the pointer, and is utilized for establishing a transformation matrix according to the already-known coordinate values of the plurality of characteristic points and the image coordinate values of the plurality of characteristic points in the image and for deciding the position of the aim point according to the transformation matrix. | 06-18-2009 |
20100328244 | DISPLACEMENT DETECTION SYSTEM OF AN OPTICAL TOUCH PANEL AND METHOD THEREOF - At a first time, a first image sensor and a second image sensor capture a first image and a second image including images of an object respectively. At a second time, the first image sensor and the second image sensor capture a third image and a fourth image including images of the object respectively. A coordinate calculation device calculates a first coordinate of the object at the first time according to the first image and the second image, and a second coordinate of the object at the second time according to the third image and the fourth image. A coordinate correction device calculates a displacement between the first time and the second time according to the first coordinate and the second coordinate, and corrects an output coordinate of the object at the second time according to the displacement. | 12-30-2010 |
20100328270 | OBJECT DETECTION CALIBRATION SYSTEM OF AN OPTICAL TOUCH SCREEN AND METHOD THEREOF - A first image sensor captures a first image of a panel of a touch screen. The first image includes a first object, a second object, a first set of reference marks, a second set of reference marks, and a first boundary mark. The touch screen establishes relationships of relative positions among the first image sensor, the first object, the second object, and the reference marks according to positions of the first object, the second object, and the reference marks in the first image. And the touch screen calculates a relative position between the first image sensor and the panel according to the relationships of relative positions among the first image sensor, the first object, the second object, and the reference marks and relative positions among the first object, the second object, and the panel. | 12-30-2010 |
20110193823 | Optical sensing system - An optical sensing system includes a sensing area, a reflective mirror, a first image-sensing device, a second image-sensing device, and a processing circuit. The sensing area is an area in which a plurality of pointing objects may execute touch operation. The reflective mirror generates a mirror image of the sensing area. The first image-sensing device and the second image-sensing device respectively capture images including all or part of the pointing objects in the sensing area, and all or part of the pointing objects in the reflective mirror. The processing circuit generates candidate coordinates according to the images captured by the first and the second image-sensing devices, and obtains the locations of the pointing objects from the candidate coordinates by means of the symmetric relationship between the point objects and the corresponding mirror images with respect to the reflective mirror. In this way, the optical sensing system can perform multi-touch operation. | 08-11-2011 |
20110316813 | OPTICAL TOUCH DISPLAY - When an object touches a touch panel, a projection light source projects a predetermined image including image information and forms an object image having the image information on a surface of the object. An image sensor captures a reflection image including the object image. Then, an angle is calculated according to an image location of the object in the reflection image and a relative position of predetermined axis, and a distance between the object and the image sensor is calculated by comparing the predetermined image with the location, size and/or phase of the image information of the reflection image so as to determine a coordinate of the object on the touch panel according to the angle and the distance. | 12-29-2011 |
20120188203 | IMAGE SENSING MODULE AND OPTICAL SENSING SYSTEM - An image sensing module utilizes an image sensor to sense objects and a mirror image of the objects in a mirror through a plurality of first light filtering components with a first transmission spectrum and a plurality of second light filtering components with a second transmission spectrum for generating an image. A light filtering module substantially having the first transmission spectrum is disposed in front of the mirror. The image includes a plurality of pixels. Each pixel includes a first sub data and a second sub data. The image sensing module utilizes an image sensing controller to detect real images corresponding to the objects and virtual images correspond to the mirror image of the objects from the image according to the first sub data and the second sub data of the plurality of pixels. | 07-26-2012 |
20120206413 | DISPLACEMENT DETECTION SYSTEM OF AN OPTICAL TOUCH PANEL AND METHOD THEREOF - At a first time, a first image sensor and a second image sensor capture a first image and a second image including images of an object respectively. At a second time, the first image sensor and the second image sensor capture a third image and a fourth image including images of the object respectively. A coordinate calculation device calculates a first coordinate of the object at the first time according to the first image and the second image, and a second coordinate of the object at the second time according to the third image and the fourth image. A coordinate correction device calculates a displacement between the first time and the second time according to the first coordinate and the second coordinate, and corrects an output coordinate of the object at the second time according to the displacement. | 08-16-2012 |
Chin-Yen Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100141033 | EFFICIENT PWM CONTROLLER - This patent discloses an efficient PWM controller for generating a pulse signal in response to a feedback signal, capable of operating in a normal mode or a green mode, comprising: a capacitor for building a saw-tooth signal by current integration, the saw-tooth signal having a ramp-up period and a ramp-down period; a first composite current source for the ramp-up period, detachable into a first constant current source and a first variable current source; and a second composite current source for the ramp-down period, detachable into a second constant current source and a second variable current source; wherein, the first variable current source is attached to the first constant current source and the second variable current source is attached to the second constant current source respectively in the green mode. | 06-10-2010 |
Chou-Kun Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20150095864 | POWER RAIL FOR PREVENTING DC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met. | 04-02-2015 |
20150095873 | METAL LINES FOR PREVENTING AC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit. | 04-02-2015 |
20150302128 | ELECTROMIGRATION-AWARE LAYOUT GENERATION - In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment. | 10-22-2015 |
20160004809 | POWER RAIL FOR PREVENTING DC ELECTROMIGRATION - A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met. | 01-07-2016 |
Cho-Yi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100113093 | Serial Transmission Interface between an Image Sensor and a Baseband Circuit - A serial transmission interface between an image sensor and a baseband circuit includes a transmission end and a reception end. The transmission end is set in the image sensor, and is utilized for transmitting image data sensed by the image sensor. The reception end is set in the baseband circuit, and is utilized for receiving the image data transmitted from the transmission end. The transmission end is one of a master control end and a slave control end, and the reception end is correspondingly the other. | 05-06-2010 |
20100220210 | INTERACTIVE SYSTEM CAPABLE OF IMPROVING IMAGE PROCESSING - An interactive system capable of improving image processing includes a reference device, a processing module and a controller. The reference device is used for transmitting and/or reflecting light signals within a predetermined spectrum. The processing module includes an image sensor, an estimation unit and a transmission interface. The image sensor is used for sensing an image so as to generate pixel signals; the estimation unit is used for determining static parameters of at least one image object according to the pixel signals; and the transmission interface is used for serially outputting the static parameters of the at least one image object. The controller is used for controlling operation of the interactive system according to the static parameters of the at least one image object outputted from the transmission interface. The image sensor, the estimation unit, and the transmission interface can all be formed on the same substrate. | 09-02-2010 |
20100328244 | DISPLACEMENT DETECTION SYSTEM OF AN OPTICAL TOUCH PANEL AND METHOD THEREOF - At a first time, a first image sensor and a second image sensor capture a first image and a second image including images of an object respectively. At a second time, the first image sensor and the second image sensor capture a third image and a fourth image including images of the object respectively. A coordinate calculation device calculates a first coordinate of the object at the first time according to the first image and the second image, and a second coordinate of the object at the second time according to the third image and the fourth image. A coordinate correction device calculates a displacement between the first time and the second time according to the first coordinate and the second coordinate, and corrects an output coordinate of the object at the second time according to the displacement. | 12-30-2010 |
20100328270 | OBJECT DETECTION CALIBRATION SYSTEM OF AN OPTICAL TOUCH SCREEN AND METHOD THEREOF - A first image sensor captures a first image of a panel of a touch screen. The first image includes a first object, a second object, a first set of reference marks, a second set of reference marks, and a first boundary mark. The touch screen establishes relationships of relative positions among the first image sensor, the first object, the second object, and the reference marks according to positions of the first object, the second object, and the reference marks in the first image. And the touch screen calculates a relative position between the first image sensor and the panel according to the relationships of relative positions among the first image sensor, the first object, the second object, and the reference marks and relative positions among the first object, the second object, and the panel. | 12-30-2010 |
20110193823 | Optical sensing system - An optical sensing system includes a sensing area, a reflective mirror, a first image-sensing device, a second image-sensing device, and a processing circuit. The sensing area is an area in which a plurality of pointing objects may execute touch operation. The reflective mirror generates a mirror image of the sensing area. The first image-sensing device and the second image-sensing device respectively capture images including all or part of the pointing objects in the sensing area, and all or part of the pointing objects in the reflective mirror. The processing circuit generates candidate coordinates according to the images captured by the first and the second image-sensing devices, and obtains the locations of the pointing objects from the candidate coordinates by means of the symmetric relationship between the point objects and the corresponding mirror images with respect to the reflective mirror. In this way, the optical sensing system can perform multi-touch operation. | 08-11-2011 |
20120206413 | DISPLACEMENT DETECTION SYSTEM OF AN OPTICAL TOUCH PANEL AND METHOD THEREOF - At a first time, a first image sensor and a second image sensor capture a first image and a second image including images of an object respectively. At a second time, the first image sensor and the second image sensor capture a third image and a fourth image including images of the object respectively. A coordinate calculation device calculates a first coordinate of the object at the first time according to the first image and the second image, and a second coordinate of the object at the second time according to the third image and the fourth image. A coordinate correction device calculates a displacement between the first time and the second time according to the first coordinate and the second coordinate, and corrects an output coordinate of the object at the second time according to the displacement. | 08-16-2012 |
Chrong Jung Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20110095394 | ANTIFUSE AND METHOD OF MAKING THE ANTIFUSE - A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse. | 04-28-2011 |
20110260292 | Bipolar Junction Transistor Having a Carrier Trapping Layer - A bipolar junction transistor having a carrier trapping layer, comprises a semi-conductor substrate including a well with a first type ions formed thereon; two impurity regions with a second type ions formed opposite with each other over the well; an insulation layer over the well, and edges extend over the second two impurity regions; and a carrier trapping layer formed over the insulation layer. | 10-27-2011 |
Chu-Hsien Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20090101922 | LED ARRANGEMENT FOR PRODUCING PURE MONOCHOMATIC LIGHT - In an LED arrangement, two or more LEDs are particularly positioned for the color lights emitted therefrom to be fully mixed to produce a pure monochromatic light. The LEDs may include at least two identical LEDs, and each of the LEDs includes at least two light emitting chips that separately emit a different color light. The LEDs are positioned in a particular manner, so that the light emitting chips located in different LEDs at the same corresponding positions emit different lights. In this manner, the color lights emitted from the LEDs are fully overlapped and mixed to produce a pure monochromatic light having increased illumination intensity and area. | 04-23-2009 |
Chun-Sheng Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140146016 | POSITIONING MODULE, OPTICAL TOUCH SYSTEM AND METHOD OF CALCULATING A COORDINATE OF A TOUCH MEDIUM - A positioning module of calculating a coordinate of a touch medium is disclosed in the present invention. The positioning module includes at least one image detecting unit, a first light source, a second light source and a processor. The image detecting unit includes a lateral side and an upper side. The image detecting unit captures an image reflected from a reflection component. The first light source is disposed on the lateral side and outputs a first beam. The second light source is disposed on the upper side and outputs a second beam. The processor is electrically connected to the image detecting unit. The processor determines a touch status of the touch medium according to a first image generated by the first beam, and further determines a touch coordinate of the touch medium according to a second image generated by the second beam. | 05-29-2014 |
20140146019 | POSITIONING MODULE, OPTICAL TOUCH SYSTEM AND METHOD OF CALCULATING A COORDINATE OF A TOUCH MEDIUM - A method of calculating a coordinate of a touch medium is disclosed in the present invention. The method includes obtaining a first image to determine whether the first image overlaps a first threshold, generating a first interceptive boundary when the first image overlaps the first threshold, obtaining a second image to generate a second interceptive boundary by overlap of the second image and a second threshold, determining whether the first interceptive boundary overlaps the second interceptive boundary, and confirming a status of the touch medium according to determination. | 05-29-2014 |
Han-Chang Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100113093 | Serial Transmission Interface between an Image Sensor and a Baseband Circuit - A serial transmission interface between an image sensor and a baseband circuit includes a transmission end and a reception end. The transmission end is set in the image sensor, and is utilized for transmitting image data sensed by the image sensor. The reception end is set in the baseband circuit, and is utilized for receiving the image data transmitted from the transmission end. The transmission end is one of a master control end and a slave control end, and the reception end is correspondingly the other. | 05-06-2010 |
Hsien-Hsin Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080246057 | Silicon layer for stopping dislocation propagation - A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices. | 10-09-2008 |
20110042729 | METHOD FOR IMPROVING SELECTIVITY OF EPI PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 02-24-2011 |
20110079820 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 04-07-2011 |
20110084355 | Isolation Structure For Semiconductor Device - A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region. | 04-14-2011 |
20110108894 | METHOD OF FORMING STRAINED STRUCTURES IN SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material. | 05-12-2011 |
20110147846 | METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant. | 06-23-2011 |
20110193141 | METHOD OF FABRICATING A FINFET DEVICE - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate. | 08-11-2011 |
20110210393 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 09-01-2011 |
20120132957 | HIGH PERFORMANCE STRAINED SOURCE-DRAIN STRUCTURE AND METHOD OF FABRICATING THE SAME - A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour. | 05-31-2012 |
20130071980 | METHOD FOR FABRICATING A FINFET DEVICE - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes forming a fin structure on a semiconductor substrate and forming a gate structure on the fin structure. A capping layer is then formed over the semiconductor substrate, fin structure, and gate structure. The capping layer is patterned to form an opening exposing a second portion of the fin structure. An epitaxial layer is grown in the opening and on the second portion of the fin structure. At least one of a source region and a drain region is provided in the epitaxial layer. The method may continue to remove the capping layer. | 03-21-2013 |
20130161650 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 06-27-2013 |
20130299876 | Method For Improving Selectivity Of EPI Process - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 11-14-2013 |
20150115322 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 04-30-2015 |
20150364604 | METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant. | 12-17-2015 |
Huang-Chi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100321957 | STANDBY POWER METHOD AND APPARATUS FOR POWER MODULE APPLICATIONS - The present invention discloses a standby power saving method for power module applications, comprising the steps of: generating a mode signal according to voltage comparison of a feedback signal and a threshold voltage, wherein the mode signal has a normal mode state and a standby mode state; generating a pulse signal according to the mode signal, wherein the pulse signal has a normal PWM mode responsive to the normal mode state of the mode signal, and a V | 12-23-2010 |
20110068751 | SAFETY CAPACITOR DISCHARGING METHOD AND APPARATUS FOR AC-TO-DC CONVERTERS - The present invention discloses a safety capacitor discharging method for AC-to-DC converters, wherein the AC-to-DC converters have a safety capacitor connected between two line voltages, the method comprising the steps of: detecting at least one line voltage to generate a line-off signal, wherein the line-off signal is at a first state when the peak voltage of the at least one line voltage is above a reference voltage, and the line-off signal is at a second state when the peak voltage of the at least one line voltage is below the reference voltage; and performing discharge of the safety capacitor by generating a conduction path between two plates of the safety capacitor when the line-off signal is at the second state. The present invention also provides a safety capacitor discharging apparatus for AC-to-DC converters. | 03-24-2011 |
20140132228 | PWM CONTROLLER DETECTING TEMPERATURE AND AC LINE VIA A SINGLE PIN AND POWER CONVERTER USING SAME - A PWM controller detecting temperature and AC line via a single pin and a power converter using the PWM controller, the PWM controller comprising: an output pin for providing a PWM signal; and a dual-function pin for receiving a temperature signal when the PWM signal is at a high level, and for receiving an AC line signal when the PWM signal is at a low level. | 05-15-2014 |
Huan-Just Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20150348796 | Nano Wire Structure and Method for Fabricating the Same - A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern. | 12-03-2015 |
Hung-Chi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100162088 | XOR CIRCUIT, RAID DEVICE CAPABLE OF RECOVERING A PLURALITY OF FAILURES AND METHOD THEREOF - An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device. | 06-24-2010 |
Jing-Cheng Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140061897 | Bump Structures for Semiconductor Package - A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar. | 03-06-2014 |
Kai-Chun Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20130201754 | MRAM WITH CURRENT-BASED SELF-REFERENCED READ OPERATIONS - A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element. | 08-08-2013 |
20130258762 | REFERENCE CELL CONFIGURATION FOR SENSING RESISTANCE STATES OF MRAM BIT CELLS - A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states R | 10-03-2013 |
Kuan-Min Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140363918 | APPARATUS AND METHOD FOR PRODUCING SOLAR CELLS USING LIGHT TREATMENT - An light apparatus used in forming a solar cell includes a housing separate from other processing in a deposition processing system, a transport mechanism for carrying a solar cell into the housing after deposition of a front contact layer in the deposition processing system, and one or more light source elements arranged to apply light on the solar cell after deposition of the front contact layer. A method of making a solar cell includes forming a back contact layer on a glass substrate, forming an absorber layer on the back contact layer, forming a buffer layer on the absorber layer, and forming a front contact layer above the buffer layer, the glass substrate, back contact layer, absorber layer, buffer layer, and front contact layer forming a first module. The method includes applying a light source to the first module after forming the front contact layer separate from other processing. | 12-11-2014 |
Kwang-Ming Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140273305 | METHOD OF CURING SOLAR CELLS TO REDUCE LAMINATION INDUCED EFFICIENCY LOSS - A method for encapsulating solar cells includes a curing step that renders CIGS or other types of solar cell absorber layers resistant to degradation by high-temperature lamination processes. The curing process takes place after IV test and prior to the lamination of an encapsulant film. The curing step is carried out in conjunction with a light soaking step that takes place prior to the IV test. The curing process takes place for a time that may range from 10 minutes to two days and at a high relative humidity, RH. Relative humidities of 20-90% are used and have been effective in passivating selenium vacancy defects associated with the absorber layers. The cured absorber layers are resistant to degradation and produce a solar cell with a high solar cell efficiency. | 09-18-2014 |
20140273329 | SOLAR CELL LASER SCRIBING METHODS - A multi-step scribing operation is provided for forming scribe lines in solar panels to form multiple interconnected cells on a solar panel substrate. The multi-step scribing operation includes at least one step utilizing a nanosecond laser cutting operation. The nanosecond laser cutting operation is followed by a mechanical cutting operation or a subsequent nanosecond laser cutting operation. In some embodiments, the multi-step scribing operation produces a two-tiered scribe line profile and the method prevents local shunting and minimizes active area loss on the solar panel. | 09-18-2014 |
20150017757 | APPARATUS AND METHODS FOR FORMING THIN FILM SOLAR CELL MATERIALS - A method for forming thin film solar cell materials introducing a first inert gas mixture that includes hydrogen selenide into a chamber at a first pressure value until the chamber reaches a second pressure value and at a first temperature value, wherein the second pressure value is a predefined percentage of the first pressure value. The temperature in the chamber is increased to a second temperature value for a selenization process so that the pressure in the chamber increases to a third pressure value. Residual gas that is generated during the selenization process can be removed from the chamber. A second inert gas mixture that includes hydrogen sulfide is added into the chamber until the chamber reaches a fourth pressure value. The temperature in the chamber is increased to a third temperature value for a sulfurization process. The chamber is cooled after the sulfurization process. | 01-15-2015 |
Li-Chun Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20160065049 | LCL CAPACITOR CURRENT COMPENSATION AND CONTROL METHOD BASED ON DIVISION AND SUMMATION TECHNIQUE - An LCL capacitor current compensation and control method based on division and summation technique, comprising following steps: calculating new reference current i* | 03-03-2016 |
Ming-Yi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140159103 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed. | 06-12-2014 |
20140322871 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device. | 10-30-2014 |
Shih-Duen Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140125370 | Image Sensor Testing Probe Card - A probe card for use in testing a wafer and a method of making the probe card include a printed circuit board (PCB) formed with a conductor pattern and a probe head in proximity to the PCB, the probe head defining at least one hole through the probe head, and the probe head being made of an electrically insulating material. At least one conductive pogo pin is disposed respectively in the at least one hole, the pogo pin having a first end electrically connected to the conductor pattern on the PCB. At least one conductive probe pin includes a cantilever portion and a tip portion. The cantilever portion is in contact with and electrically connected to a second end of the pogo pin, and the tip portion is electrically connectable to the wafer to electrically connect the wafer to the conductor pattern on the PCB. The cantilever portion of the probe pin is fixedly attached to the probe head. | 05-08-2014 |
Shih-Fang Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080267488 | Apparatus and method for monitoring overlapped object - An apparatus and a method for monitoring overlapped objects are disclosed. The monitoring apparatus comprises a projection device and a camera for projecting images to a target plane at different angles and shooting the pictures from the target plane. When an object is placed on the target plane, the pictures present the part of the image overlapping the surface of the object for determining whether there are overlapped objects or not. | 10-30-2008 |
Sung-Bin Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20090179256 | MEMORY HAVING SEPARATED CHARGE TRAP SPACERS AND METHOD OF FORMING THE SAME - A silicon-oxide-nitride-oxide-silicon (SONOS) memory and the corresponding forming method are disclosed. The memory includes a plurality of select gate structures arranged in an array, a plurality of charge trap spacers that do not contact each other, and a plurality of word lines. The word lines can directly contact the select gates' surfaces of the select gate structures. All of the select gate structures disposed in one line can share two charge trap spacers, and the two charge trap spacers are disposed on the opposed sidewalls of these select gate structures. | 07-16-2009 |
Ta-Cheng Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100044748 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device includes a p-well with first protrudent portions, an N-well with second protrudent portions, a P-well/N-well boundary, a PMOS transistor disposed in the N-well, an NMOS transistor disposed in the P-well, first P+ diffusion regions in the first protrudent portions, first N+ diffusion regions in the second protrudent portions, second P+ diffusion regions disposed between the PMOS transistor and the second protrudent portions, second N+ diffusion regions disposed between the NMOS transistor and the first protrudent portions, third P+ diffusion regions disposed between the NMOS transistor, the boundary, and two adjacent second P+ diffusion regions, and third N+ diffusion regions disposed between the PMOS transistor, the boundary, and two adjacent second N+ diffusion regions, wherein the first and second protrudent portions are interlacedly arranged at the boundary. | 02-25-2010 |
20100163924 | LATERAL SILICON CONTROLLED RECTIFIER STRUCTURE - A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P | 07-01-2010 |
Tai-Chuan Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140170842 | METHOD FOR FORMING DUMMY GATE - Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part. | 06-19-2014 |
Tse-Chi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080218487 | Capacitive-type touch pad having special arrangement of capacitance sensor - A touch pad has a controller circuitry for generating an X-Y coordinate signal; a touch screen connecting with the controller circuitry, which has a transparent substrate and a transparent conductive film provided at the transparent substrate. The transparent conductive film having a plurality of capacitance sensors distributed along an X-coordinate direction and a Y-coordinate direction. The plurality of capacitance sensors are patterned for averaging the resistance capacitance distribution. | 09-11-2008 |
Tsu-Ping Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080247455 | Video signal processing apparatus to generate both progressive and interlace video signals - A video signal processing apparatus includes a main picture processor, an interlace recovering module and a video encoder. The main picture processor produces corresponding main picture signals based on video signals from a memory. The main picture signals are converted to progressive scan signals through a predetermined video signals processing. The interlace recovering module receives the progressive scan signals, retrieves the even portion and the odd portion of the progressive video signals alternately, and generates a set of interlace-scan signals. The video encoder receives both the progressive scan signals and the interlace scan signals and generates a set of progressive video signals and a set of interlace video signals to corresponding video display apparatuses. Thereupon, the video reproduction system can simultaneously provide both the progressive video signals and interlace video signals to the video display apparatuses. | 10-09-2008 |
Wei-Chieh Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20110254050 | REVERSE CONDUCTING IGBT - An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance. | 10-20-2011 |
Wei-Feng Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140125370 | Image Sensor Testing Probe Card - A probe card for use in testing a wafer and a method of making the probe card include a printed circuit board (PCB) formed with a conductor pattern and a probe head in proximity to the PCB, the probe head defining at least one hole through the probe head, and the probe head being made of an electrically insulating material. At least one conductive pogo pin is disposed respectively in the at least one hole, the pogo pin having a first end electrically connected to the conductor pattern on the PCB. At least one conductive probe pin includes a cantilever portion and a tip portion. The cantilever portion is in contact with and electrically connected to a second end of the pogo pin, and the tip portion is electrically connectable to the wafer to electrically connect the wafer to the conductor pattern on the PCB. The cantilever portion of the probe pin is fixedly attached to the probe head. | 05-08-2014 |
Wen-Hsiang Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20090127581 | NITRIDE-BASED LIGHT-EMITTING DEVICE - A nitride-based light-emitting device includes a substrate and a plurality of layers formed over the substrate in the following sequence: a nitride-based buffer layer formed by nitrogen, a first group III element, and optionally, a second group III element, a first nitride-based semiconductor layer, a light-emitting layer, and a second nitride-based semiconductor layer. | 05-21-2009 |
Yao-Hsuan Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140092019 | OPTICAL NAVIGATION METHOD FOR DYNAMICALLY ADJUSTING SIZE OF IMAGE SENSING REGION AND RELATED APPARATUS THEREOF - An optical navigation method includes: detecting inertia of an image of a feature point; and determining an effective sensing region of an image sensing array according to the detected inertia for reducing power consumption. Besides, an optical navigation apparatus includes a detecting circuit and a determining unit. The detecting circuit is arranged for detecting a moving inertia of a feature point. The determining circuit is coupled to the detecting circuit, and arranged for determining an effective sensing region of an image sensing array according to the detected moving inertia for reducing power consumption. | 04-03-2014 |
20140097330 | METHOD OF TESTING IMAGE SENSOR AND RELATED APPARATUS THEREOF - A method of testing an image sensor having a plurality of sensing units includes: utilizing the image sensor to generate a plurality of sensing results respectively corresponding to a plurality of captured images, wherein each sensing result includes a plurality of sensing values respectively generated by the sensing units; and generating a testing result which indicates a performance of the image sensor according to changing of the sensing results. | 04-10-2014 |
Yen-Tai Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080218252 | VOLTAGE REGULATOR OUTPUTTING POSITIVE AND NEGATIVE VOLTAGES WITH THE SAME OFFSETS - A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit. | 09-11-2008 |
20130064027 | Memory and Method of Adjusting Operating Voltage thereof - By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor. | 03-14-2013 |
Ying-Hsi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100066327 | VOLTAGE CONVERSION APPARATUS - A voltage conversion apparatus includes a DC-to-DC conversion circuit, a sensing circuit, and a compensation circuit. The voltage conversion apparatus is capable of adaptively adjusting the system bandwidth according to the load. The system bandwidth is increased to make the converted voltage responding to the load rapidly when the voltage conversion apparatus is operated at a transient state; and the system bandwidth is decreased to increase the system stability when the voltage conversion circuit is operated at a steady state. | 03-18-2010 |
20110115570 | CLOCK GENERATOR - This invention discloses a clock generator capable of automatically adjusting output clock when process, voltage, or temperature variation occurred. The clock generator comprises: a current generator, for generating a first current and a second current according to a bias signal; an oscillator, coupled to the current generator, for generating a clock signal according to the first current; a frequency detector, coupled to the oscillator, for generating a control signal according to the clock signal and a reference signal; and a bias voltage adjuster, coupled to the current generator and the frequency detector, for adjusting the bias signal according to the control signal; wherein, when the signal frequency of the clock signal changes, the bias signal corresponds to the bias voltage adjuster, to adjust the first current and the second current. | 05-19-2011 |
20120293081 | OPERATING CIRCUIT APPLIED TO BACKLIGHT AND ASSOCIATED METHOD - An operating circuit applied to a backlight includes at least one current control circuit, where the current control circuit includes a transistor, an operational amplifier and a switch module. The transistor has a gate, a first electrode and a second electrode, where the first electrode is coupled to a lighting element, and the second electrode is coupled to a resistor. The operational amplifier has positive and negative input terminals, and positive and negative output terminals. The switch module switches a connection relationship between the positive input terminal, the negative input terminal, the reference voltage and the second electrode of the transistor, and switches a connection relationship between the positive output terminal, the negative output terminal and the gate of the transistor to make the close loop form a negative feedback, and the current of the lighting element not influenced by an offset voltage of the operational amplifier. | 11-22-2012 |
20120293084 | OPERATING CIRCUIT APPLIED TO BACKLIGHT AND ASSOCIATED METHOD - An operating circuit applied to a backlight is provided, where the backlight includes a plurality of lighting elements, and the operating circuit includes a plurality of current control circuits, a plurality of switches, a minimum voltage selector, a supply voltage generating circuit and a control unit. The current control circuits are coupled to the lighting elements via a plurality of nodes, respectively. The switches are coupled to the nodes, respectively. The minimum voltage selector is utilized for receiving at least a portion of voltages of the plurality of nodes, and selecting a minimum voltage among the received voltages. The supply voltage generating circuit is utilized for generating a supply voltage of the lighting elements according to the minimum voltage. For each of the switches, the control unit determines an on/off state of the switch by determining whether the corresponding lighting element is an open circuit or not. | 11-22-2012 |
20130278320 | MIXER FOR MIXING INPUT SIGNAL WITH MULTIPLE OSCILLATING SIGNALS HAVING DIFFERENT PHASES AND RELATED MIXING METHOD THEREOF - A mixer includes a transformer and a mixing circuit. The transformer is employed for receiving an input signal to generate a differential output. The mixing circuit is coupled to the transformer, and employed for mixing the differential output with N oscillating signals having different phases to generate a plurality of mixed output signals, wherein N is greater than 2. | 10-24-2013 |
20130307620 | SIGNAL AMPLIFYING CIRCUIT WITH REDUCED OUTPUT SIGNAL NOISE BY INTRODUCING COUPLING EFFECT AND RELATED METHOD THEREOF - A signal amplifying circuit includes: an input stage circuit, arranged to receive an input signal; a first inductive device coupled between the input stage circuit and a first reference voltage; an output stage circuit arranged to generate an output signal according to the input signal; and a second inductive device coupled between the output stage circuit and a second reference voltage, wherein at least a part of a winding of the first inductive element is cross-coupled to at least a part of a winding of the second inductive element. | 11-21-2013 |
20140022018 | AMPLIFIER WITH GAIN CIRCUIT COUPELD TO PRIMARY COIL OF TRANSFORMER - An amplifier includes a transformer and a first stage gain circuit. The transformer includes a primary coil and a secondary coil. The primary coil is utilized for receiving an input signal. The first stage gain circuit has a first input port, which is coupled to the primary coil. The first stage gain circuit is utilized for gaining the input signal so as to generate a first output. | 01-23-2014 |
20140049441 | SIGNAL CONVERTING CIRCUIT CAPABLE OF REDUCING/AVOIDING SIGNAL LEAKAGE AND RELATED SIGNAL CONVERTING METHOD - A signal converting circuit includes: a first switching circuit; a second switching circuit; and a first balance-unbalance circuit (Balun) having a first signal terminal coupled to an antenna, a second signal terminal coupled to the first switching circuit, and a third signal terminal coupled to the second switching circuit; wherein when the first balance-unbalance circuit operates in a first signal converting mode, the first switching circuit and the second switching circuit are arranged to couple the second signal terminal and the third signal terminal, respectively, to a first signal processing circuit, and when the first balance-unbalance circuit does not operate in the first signal converting mode, the first switching circuit and the second switching circuit are arranged to couple the second signal terminal and the third signal terminal, respectively, to a reference voltage. | 02-20-2014 |
Ying-Shiou Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080237746 | Gated diode with non-planar source region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 10-02-2008 |
Ying-Yao Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20100026252 | Low Drop-Out Voltage Regulator with Efficient Frequency Compensation - A low drop-out (LDO) voltage regulator with efficient frequency compensation is disclosed. The LDO voltage regulator includes an error amplifier, a transmission element, a voltage divider and a pole control unit. The error amplifier generates a control signal according to a reference voltage and a feedback voltage. The transmission element is coupled to the error amplifier, and adjusts an input voltage to generate an output voltage according to the control signal. The voltage divider is coupled to the transmission element, and performs a voltage division operation on the output voltage to generate the feedback voltage. The pole control unit is coupled to the transmission element, and provides and adjusts an output capacitor of the LDO voltage regulator to fix a frequency of a pole according to variation of an output impedance of the transmission element, so as to maintain loop stability. | 02-04-2010 |
20100054378 | CENTER FREQUENCY ADJUSTMENT DEVICE AND RELATED METHOD FOR A COMMUNICATIONS RECEIVER - A center frequency adjustment device for a communications receiver includes an A/D converter coupled to an analog filter in the communications receiver for converting an output signal of the analog filter to a digital signal, a carrier frequency offset estimator coupled to the A/D converter for estimating a carrier frequency offset of the communications receiver according to the digital signal, and a control circuit coupled to the analog filter and the carrier frequency offset estimator for adjusting a center frequency of the analog filter according to the carrier frequency offset. | 03-04-2010 |
20110223878 | Signal Strength Detecting Device and Related Method - A signal strength detecting device of a communication system is disclosed. The signal strength detecting device is coupled to a frequency down mixer of the communication system and the frequency down mixer is used for receiving and converting a first signal to a second signal whose frequencies are lower than frequencies of the first signal. The signal strength detecting device comprises a frequency up converter for receiving and converting the second signal to a third signal whose frequencies are higher than the frequencies of the second signal and a detecting unit for detecting strength of the third signal and generating a signal strength indicator to the communication system according to a detecting result corresponding to the strength of the third signal, wherein the signal strength indicator represents the strength of the first signal received by the frequency down mixer. | 09-15-2011 |
Yuan-Chi Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20080267488 | Apparatus and method for monitoring overlapped object - An apparatus and a method for monitoring overlapped objects are disclosed. The monitoring apparatus comprises a projection device and a camera for projecting images to a target plane at different angles and shooting the pictures from the target plane. When an object is placed on the target plane, the pictures present the part of the image overlapping the surface of the object for determining whether there are overlapped objects or not. | 10-30-2008 |
20080290884 | Probe card assembly with ZIF connectors, method of assembling, wafer testing system and wafer testing method introduced by the same - This invention discloses a probe card assembly with adjustable ZIF connectors. The probe card assembly comprises a substrate, a plurality of ZIF connectors and a plurality of adjustable fastening means for assembling and disassembling the ZIF connectors on the substrate. The substrate is a disc-like plate, having a first surface, a second surface, a plurality of concave sections disposed on the second surface and a plurality of first through holes perpendicular to the first surface. The first through holes are circularly arranged toward the substrate center. Pairs of first contacts are provided on the first surface adjacent to both sides of first through holes. A plurality of terminals are protruded from the second surface of the substrate for contacting and testing the wafer. The ZIF connectors are also circularly arranged toward the substrate center. Each ZIF connector has parallelly arranged second through holes from the top to the bottom of the connector and pairs of contact terminals for contacting the first contacts of the substrate. The adjustable fastening means are disposed from the concave section through the first and second through holes to assembling and disassembling the ZIF connectors on the first surface of the substrate. | 11-27-2008 |
Yu-Chia Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140146016 | POSITIONING MODULE, OPTICAL TOUCH SYSTEM AND METHOD OF CALCULATING A COORDINATE OF A TOUCH MEDIUM - A positioning module of calculating a coordinate of a touch medium is disclosed in the present invention. The positioning module includes at least one image detecting unit, a first light source, a second light source and a processor. The image detecting unit includes a lateral side and an upper side. The image detecting unit captures an image reflected from a reflection component. The first light source is disposed on the lateral side and outputs a first beam. The second light source is disposed on the upper side and outputs a second beam. The processor is electrically connected to the image detecting unit. The processor determines a touch status of the touch medium according to a first image generated by the first beam, and further determines a touch coordinate of the touch medium according to a second image generated by the second beam. | 05-29-2014 |
20140146019 | POSITIONING MODULE, OPTICAL TOUCH SYSTEM AND METHOD OF CALCULATING A COORDINATE OF A TOUCH MEDIUM - A method of calculating a coordinate of a touch medium is disclosed in the present invention. The method includes obtaining a first image to determine whether the first image overlaps a first threshold, generating a first interceptive boundary when the first image overlaps the first threshold, obtaining a second image to generate a second interceptive boundary by overlap of the second image and a second threshold, determining whether the first interceptive boundary overlaps the second interceptive boundary, and confirming a status of the touch medium according to determination. | 05-29-2014 |
20140300582 | IMAGE SENSING METHOD AND IMAGE SENSING APPARATUS - Disclosed is an image sensor comprising: an image sensing unit array, for sensing an object and comprising a plurality of image sensing units arranged in a sensing matrix with M rows and N columns; an image data reading circuit, for reading and outputting image data caught by at least part of the image sensing units; and a control unit, for controlling numbers and locations of the image sensing units for each row or each column, from which the image data reading circuit reads the image data; for computing a read region that is in the image sensing unit array and corresponds to the object; and for controlling the image data reading circuit to read at least part of the image data of the column or the row. The part of the column or the row, which is read, comprises the read region. | 10-09-2014 |
Yung-Chang Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20130236051 | COMPUTER READABLE MEDIA CAN PERFORM INTERFERENCE IMAGE DETERMINING METHOD AND INTERFERENCE IMAGE DETERMINING APPARATUS - A computer readable media having at least one program code recorded thereon. An interference image determining method can be performed when the program code is read and executed. The interference image determining method comprises: (a) controlling a light source to illuminate an object on a detecting surface to generate an image; (b) controlling a sensor to catch a current frame of the image; (c) utilizing an image characteristic included in the current frame to determine a interference image part of the current frame; and (d) updating a defined interference image according to the determined interference image part. | 09-12-2013 |
20140132565 | IMAGE SENSING APPARATUS, OPTICAL TOUCH CONTROL APPARATUS AND MOTION TRACKING APPARATUS UTILIZING THE IMAGE SENSING APPARATUS - An image sensing apparatus, comprising: a control unit; and an image sensor, wherein the control unit controls the image sensor to utilize a first image sensing region to sense a first image to output a first image signal in a first mode, wherein the control unit controls the image sensor to utilize a second image sensing region to sense a second image to output a second image signal in a second mode. The first image sensing region is smaller than a total image sensing region of the image sensor, and the second image sensing region is smaller than the first image sensing region. | 05-15-2014 |
20140160023 | PORTABLE INTERACTIVE ELECTRONIC APPARATUS - A portable interactive electronic apparatus includes a shell and a touch control panel having a cover plate. The cover plate includes a first surface area and a second surface area, and the touch control panel is positioned on the shell. The first surface area is utilized for sensing a touch of a user's finger, and the second surface area is utilized for leading liquid components out from the cover plate. | 06-12-2014 |
20140210723 | OPTICAL MOUSE APPARATUS AND DATA COMPRESSION METHOD USED IN OPTICAL MOUSE APPARATUS - An optical mouse apparatus includes a light source circuit, a sensing circuit, and a processing circuit. The light source circuit is used for generating and emitting a light signal onto a surface so as to generate a light reflected signal. The sensing circuit is used for estimating an image offset of the optical mouse apparatus. The processing circuit is coupled to the light source circuit and the sensing circuit and used for generating and outputting a control signal to a terminal according to the image offset outputted by the sensing circuit. The sensing circuit is further used for detecting at least one of a moving speed or an offset direction of the image offset of the optical mouse apparatus, so as to dynamically determine whether to compress data of the image offset outputted to the processing circuit, for reducing data amount read by the processing circuit. | 07-31-2014 |
20140240229 | TOUCH CONTROL METHOD AND TOUCH CONTROL APPARATUS - A computer readable recording media comprising at least one program code recorded thereon, a touch control method is performed when the program code is read and executed. The touch control method comprises the following steps: (a) detecting location data for an object relative to a detecting surface to generate at least one displacement data; (b) storing the displacement data to a storage apparatus and outputting the stored displacement data to a target apparatus from the storage apparatus after storing the displacement data for a predetermined time period, when the object touches the detecting surface; and (c) cleaning the stored displacement data when the object leaves the detecting surface. | 08-28-2014 |
20140320409 | OPTICAL FINGER MOUSE EQUIPPED WITH FEEDBACK FUNCTION AND ASSOCIATED CONTROL METHOD - An optical finger mouse includes a housing, a light source, a light guide mechanism, an image sensor, a processor and a feedback module. The housing is arranged for an object to be detected performing a motion control thereon, wherein the object to be detected slides or taps on the housing to perform the motion control. The light source is arranged for generating light. The light guide mechanism is arranged for guiding the light generated by the light source to project on the object to be detected. The image sensor captures reflected light generated from the object to be detected to generate a sensing result. The processor generates detection information according to the sensing result. The feedback module generates feedback according to the detection information. | 10-30-2014 |
20140333540 | OPTICAL NAVIGATION DEVICE WITH DIFFERENT OPTICAL MECHANISMS AND ASSOCIATED METHOD THEREOF - An optical navigation device includes a first optical mechanism, a second optical mechanism, an image sensor, and a controller. The first optical mechanism is arranged for projecting light on a surface to generate a first projection result while the second optical mechanism is arranged for projecting light on the surface to generate a second projection result. The image sensor is arranged for sensing at least one of the first projection result and the second projection result within a sensing range to generate at least one first image sensing result. The controller is coupled to the first optical mechanism, the second optical mechanism and the image sensor, and is arranged for controlling the first optical mechanism and the second optical mechanism according to the first image sensing result. The optical navigation device accordingly performs movement detection. | 11-13-2014 |
Yung-Kai Lin, Hsin-Chu City TW
Patent application number | Description | Published |
---|---|---|
20140273505 | SEMICONDUCTOR APPARATUS WITH TRANSPORTABLE EDGE RING FOR SUBSTRATE TRANSPORT - An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools. | 09-18-2014 |