Patent application number | Description | Published |
20090027407 | DATA ACCESS TOOL FOR PROGRAMMABLE GRAPHICS HARDWARE - Methods and apparatuses for accessing data within programmable graphics hardware are provided. According to one aspect, a user inserts special log commands into a software program, which is compiled into instructions for the programmable graphics hardware to execute. The hardware writes data to an external memory during runtime according to a flow control protocol, and the software driver reads the data from the memory to display to the user. | 01-29-2009 |
20090085919 | SYSTEM AND METHOD OF MAPPING SHADER VARIABLES INTO PHYSICAL REGISTERS - The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types. | 04-02-2009 |
20090089763 | SHADER COMPILE SYSTEM AND METHOD - The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction. | 04-02-2009 |
20090213128 | SYSTEM AND METHOD FOR INSTRUCTION LATENCY REDUCTION IN GRAPHICS PROCESSING - A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions. | 08-27-2009 |
20120268484 | METHOD AND DEVICE FOR PERFORMING USER-DEFINED CLIPPING IN OBJECT SPACE - A method and device for performing and processing user-defined clipping in object space to reduce the number of computations needed for the clipping operation. The method and device also combine the modelview transformation of the vertex coordinates with projection transform. The user-defined clipping in object space provides a higher performance and less power consumption by avoiding generation of eye coordinates if there is no lighting. The device includes a driver for the user-defined clipping in the object space to perform dual mode user-defined clipping in object space when a lighting function is disabled and in eye space when the lighting function is enabled. | 10-25-2012 |
20130061027 | TECHNIQUES FOR HANDLING DIVERGENT THREADS IN A MULTI-THREADED PROCESSING SYSTEM - This disclosure describes techniques for handling divergent thread conditions in a multi-threaded processing system. In some examples, a control flow unit may obtain a control flow instruction identified by a program counter value stored in a program counter register. The control flow instruction may include a target value indicative of a target program counter value for the control flow instruction. The control flow unit may select one of the target program counter value and a minimum resume counter value as a value to load into the program counter register. The minimum resume counter value may be indicative of a smallest resume counter value from a set of one or more resume counter values associated with one or more inactive threads. Each of the one or more resume counter values may be indicative of a program counter value at which a respective inactive thread should be activated. | 03-07-2013 |
20130326158 | MEMORY CHANNEL SELECTION IN A MULTI-CHANNEL MEMORY SYSTEM - In general, this disclosure describes techniques for selecting a memory channel in a multi-channel memory system for storing data, so that usage of the memory channels is well-balanced. A request to write data to a logical memory address of a memory system may be received. The logical memory address may include a logical page number and a page offset, where the logical page number maps to a physical page number and the logical memory address maps to a physical memory address. A memory unit out of a plurality of memory units in the memory system may be determined by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number. The data may be written to a physical memory address in the determined memory unit in the memory system. | 12-05-2013 |
20130328889 | PADDING FOR MULTI-CHANNEL MEMORY - Techniques described in the disclosure are generally related to reserving padding bytes in system memory when storing data in the system memory. The reserving of padding bytes may allow a memory interface to efficiently utilize the channels to the system memory when storing or subsequently retrieving the data. | 12-12-2013 |
20140047223 | SELECTIVELY ACTIVATING A RESUME CHECK OPERATION IN A MULTI-THREADED PROCESSING SYSTEM - This disclosure describes techniques for selectively activating a resume check operation in a single instruction, multiple data (SIMD) processing system. A processor is described that is configured to selectively enable or disable a resume check operation for a particular instruction based on information included in the instruction that indicates whether a resume check operation is to be performed for the instruction. A compiler is also described that is configured to generate compiled code which, when executed, causes a resume check operation to be selectively enabled or disabled for particular instructions. The compiled code may include one or more instructions that each specify whether a resume check operation is to be performed for the respective instruction. The techniques of this disclosure may be used to reduce the power consumption of and/or improve the performance of a SIMD system that utilizes a resume check operation to manage the reactivation of deactivated threads. | 02-13-2014 |
20140075165 | EXECUTING SUBROUTINES IN A MULTI-THREADED PROCESSING SYSTEM - This disclosure is directed to techniques for executing subroutines in a single instruction, multiple data (SIMD) processing system that is subject to divergent thread conditions. In particular, a resume counter-based approach for managing divergent thread state is described that utilizes program module-specific minimum resume counters (MINRCs) for the efficient processing of control flow instructions. In some examples, the techniques of this disclosure may include using a main program MINRC to control the execution of a main program module and subroutine-specific MINRCs to control the execution of subroutine program modules. Techniques are also described for managing the main program MINRC and subroutine-specific MINRCs when subroutine call and return instructions are executed. Techniques are also described for updating a subroutine-specific MINRC to ensure that the updated MINRC value for the subroutine-specific MINRC is within the program space allocated for the subroutine. | 03-13-2014 |