Patent application number | Description | Published |
20080239948 | SPECULATIVE CONGESTION CONTROL SYSTEM AND CROSS-LAYER ARCHITECTURE FOR USE IN LOSSY COMPUTER NETWORKS - Methods and apparatus are provided to improve data throughput in a wireless, wireline or a combination wireless and wireline communication system. A congestion control manager selects between an assumption based congestion control algorithm and a speculation based congestion control algorithm. The selected algorithm generates data recovery instructions including instructions for resizing, or not, congestion window sizing for the communication gateways. By making the selection between the assumption based congestion control algorithm and the speculation based congestion control algorithm based upon network information, data recovery and throughput is optimized for networks having lossy data links. | 10-02-2008 |
20080239953 | METHOD AND APPARATUS FOR MINIMIZING CONGESTION IN GATEWAYS - Methods and apparatus are provided to reduce data congestion and thus improve data throughput in gateways used in a wireless, wireline or a combination wireless and wireline communication system. The congestion management system optimally resizes, or not, congestion window (or buffer) sizing and threshold for the communication gateways based upon mathematical models. Application of the inventive congestion management method optimizes data recovery and throughput in communication networks, particularly those networks having lossy data links. | 10-02-2008 |
20120314489 | SYSTEMS AND METHODS FOR DIRECT COMMUNICATION BETWEEN MAGNETIC TUNNEL JUNCTIONS - Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction. | 12-13-2012 |
Patent application number | Description | Published |
20120180005 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 07-12-2012 |
20130038348 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 02-14-2013 |
20130227499 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 08-29-2013 |
20140157223 | CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS - In various embodiments, an integrated circuit layout is disclosed. In one embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area. | 06-05-2014 |
20160048624 | CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS - In various embodiments, an integrated circuit derived from an integrated circuit layout is disclosed. In some embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold, the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area. | 02-18-2016 |
Patent application number | Description | Published |
20090044158 | METHOD, AND EXTENSIONS, TO COUPLE SUBSTRATE EFFECTS AND COMPACT MODEL CIRCUIT SIMULATION FOR EFFICIENT SIMULATION OF SEMICONDUCTOR DEVICES AND CIRCUIT - This invention comprises a new method to couple simulation of electronics circuits (using compact models) with simulation of physical effects which require a PDE (partial differential equation) based simulation, for semiconductor MOSFET based devices and circuits. In particular the method can be used to capture high injection substrate effects such as single event transients (SET), latch-up, ESD, or thermal effects. Bipolar substrate effects are handled correctly and completely with this algorithm. The method extends the applicability of technology CAD (TCAD) to multiple devices. | 02-12-2009 |
20090184733 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (≦90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 07-23-2009 |
20100264953 | Soft Error Hard Electronic Circuit and Layout - This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection. | 10-21-2010 |
20120185816 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 07-19-2012 |
20130162293 | Soft Error Hard Electronics Layout Arrangement and Logic Cells - A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell. | 06-27-2013 |
20140019921 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 01-16-2014 |
Patent application number | Description | Published |
20100077889 | METHOD TO ENHANCE CLARIFICATION IN A MIXING REACTOR AND SAID MIXING REACTOR - The invention relates to a mixing reactor for mixing a liquid and pulverous solid, clarification the solution that is formed and discharging the clarified solution from the mixing reactor, in the lower section of which a fluidized bed is formed. The invention also relates to a method for mixing a liquid and pulverous solid into each other in a fluidized bed, for clarification the solution that is formed and for discharging the clarified solution from the mixing reactor. | 04-01-2010 |
20100078380 | Method and Equipment for Liquid-Liquid Extraction - The invention relates to a method for reversing the dispersion formed in the mixing section of liquid-liquid extraction and kept condensed in the separation section and the separated solutions form the rear end of the separation section to flow back towards the feed end of the separation section. The invention also refers to the extraction equipment for implementing the reversed flow. | 04-01-2010 |
20100229687 | METHOD AND MIXER APPARATUS FOR MIXING GAS INTO SLURRY IN A CLOSED REACTOR - The mixer apparatus accordant with the invention includes a closed reactor, at least two mixers at different heights, which are on the same shaft, a gas feed pipe below the lower mixer and baffles. The blades of the mixers are mostly rectangular in shape and a minimum of six in number. The angle of inclination of the blades of the lower mixer is around 50-70° and that of the upper mixer around 25-35°. The number of baffles is at least six and their range around 20% of the reactor diameter. The invention is focused also the corresponding method. | 09-16-2010 |
20120039721 | IMPELLER FOR MIXING SLURRY IN METALLURGICAL PROCESSES - The invention relates to a turbine-type high-power impeller, to be used for mixing slurry in hydrometallurgical process reactors. The impeller is formed of at least five blades, each of which blades comprises a front edge, trailing edge, root and tip; the roots of the impeller blades are permanently attached by a joint to the hub or axis of the impeller, so that the front edge of the impeller blade is straight, and the trailing edge is chamfered, in which case the blade is narrowed towards the tip, and the blade is provided with two longitudinal folds arranged in parallel with the front edge of the blade. | 02-16-2012 |
20130176815 | DEVICE AND METHOD FOR DISPERSING TWO SOLUTIONS IN EACH OTHER IN SOLVENT EXTRACTION - The invention relates to a mixing device and method by means of which two solutions that are insoluble or poorly soluble in each other are mixed together into a dispersion. The device consists of at least three helical bars rotating upwards around a shaft and supported on it, so that the support structures between the shaft and the helical rods are set essentially in a horizontal position. The device and method are particularly suitable for mixing solvent extraction solutions used in the hydrometallurgical recovery of metals to form a dispersion. | 07-11-2013 |