Patent application number | Description | Published |
20080212674 | METHOD AND APPARATUS FOR VIDEO DECODING AND DE-INTERLACING - A method for video decoding in a video decoding/de-interlacing display apparatus that utilizes a storage device having four frame buffers is provided. The method includes following steps: (a) decoding video data of a next picture; (b) if the next picture is a B picture, buffering the decoded video data of the next picture into a frame buffer of the storage device not stored with a reference picture nor a present display picture nor a previous display picture; and (c) if step (b) is not applicable, buffering the decoded video data of the next picture into a frame buffer of the storage device stored with the previous display picture. | 09-04-2008 |
20090317059 | APPARATUS AND METHOD OF TRANSMITTING / RECEIVING MULTIMEDIA PLAYBACK ENHANCEMENT INFORMATION, VBI DATA, OR AUXILIARY DATA THROUGH DIGITAL TRANSMISSION MEANS SPECIFIED FOR MULTIMEDIA DATA TRANSMISSION - A data transmission interface apparatus is provided for communicating with another data transmission interface apparatus through a digital transmission means specified for multimedia data transmission. The data transmission interface apparatus has at least a processor for processing multimedia data; and a data converting circuit, coupled to the processor, for converting a plurality of first multimedia data sets into a plurality of second multimedia data sets; and for converting a plurality of first auxiliary data sets into a plurality of second auxiliary data sets. | 12-24-2009 |
20100020105 | MULTI-FORMAT IMAGE DISPLAY APPARATUS AND METHOD - An image display apparatus and method are disclosed. In the present invention, image frames of various data information sizes are displayed with a selected output data information size. If the selected output data information size is below a limit of a storage medium for buffering image frames to be displayed, the data information size of an input image frame is adjusted to the output data information, and the image frame is displayed in the output data information size. If the output data information exceeds the limit of the storage medium, the input image is over-compressed to have a lower data information size. Then an image processing is performed to the image frame, so that the processed image frame is decompressed to have the output data information size before being displayed. Therefore, the decompressed image frame can be displayed in the selected output data information size. | 01-28-2010 |
20100020236 | IMAGE DISPLAY APPARATUS AND METHOD - An image display apparatus and method are disclosed. In the present invention, an input image frame having a first solution is scaled by a scaling module so that a scaled image frame having a second dimension is generated. The scaled image frame is processed by a display device supporting the second dimension. The display device generates display signals corresponding to the scaled image frame and transmits the display signal to a display interface. Accordingly, the display interface can display an output image frame in the second dimension based on the display signals. | 01-28-2010 |
20100027973 | IMAGE PROCESSING CIRCUIT AND METHOD CAPABLE OF PERFORMING ONLINE COLOR SPACE CONVERSION - An image processing circuit includes: a video decoder for decoding at least one block image source to generate first decoded data, where the block image source and the first decoded data correspond to a first color space; a color space converting unit, coupled to the video decoder, for performing color space conversion on the first decoded data to generate second decoded data, where the second decoded data corresponds to a second color space; a block based scaling unit, coupled to the color space converting unit, for performing a scaling operation on the second decoded data to generate scaled data, where the scaled data corresponds to the second color space; and a frame buffer, coupled to the block based scaling unit, for temporarily storing the scaled data, where the scaled data temporarily stored in the frame buffer is utilized in the second color space. | 02-04-2010 |
20100157148 | METHOD AND APPARATUS FOR VIDEO DECODING AND DE-INTERLACING - A method for video decoding in a video decoding/de-interlacing display apparatus that utilizes a storage device is provided. The method includes: (a) decoding video data of a next picture; (b) if the next picture is a B picture, buffering the decoded video data of the next picture into a frame buffer of the storage device not stored with a reference picture nor a present display picture nor a previous display picture; and (c) if the decoded next picture is a reference picture, buffering the decoded video data of the next picture into a frame buffer of the storage device not stored with a last decoded reference picture nor the present display picture nor the previous display picture. | 06-24-2010 |
20100178037 | DISPLAY APPARATUS, VIDEO GENERATION APPARATUS, AND METHOD THEREOF - A video generation apparatus for processing a video source to generate a video stream supplied to a display apparatus comprises: a buffer and a scaler. The buffer is capable of storing scaling reference lines retrieved from the video source. The scaler is used for generating scaled lines based on the scaling reference lines stored in the buffer, wherein the scaled lines are used in the video stream supplied to the display apparatus, and an input line period length of the scaler receiving the video source and an output line period length of the scaler supplying the video stream to the display apparatus are the same. Valid scaled lines generated for each frame by the scaler is less than a total number of output line periods for each frame of the video stream. | 07-15-2010 |
20110311208 | Portable Multimedia Playback Apparatus - A portable multimedia playback apparatus is provided. The portable multimedia playback apparatus comprises a first video processing unit, a second video processing unit, a third video processing unit, a multiplexer, and a digital-to-analog converter (DAC). The first video processing unit generates a digital video signal. The second video processing unit processes the digital video signal to generate a TV compatible signal. The third video processing unit processes the digital video signal to generate a flat panel compatible signal. The multiplexer selects one of the TV compatible signal and the flat panel compatible signal. The DAC outputs an analog video signal after converting the selected signal. | 12-22-2011 |
20120314128 | APPARATUS AND METHOD OF TRANSMITTING/RECEIVING MULTIMEDIA PLAYBACK ENHANCEMENT INFORMATION, VBI DATA, OR AUXILIARY DATA THROUGH DIGITAL TRANSMISSION MEANS SPECIFIED FOR MULTIMEDIA DATA TRANSMISSION - A data transmission interface apparatus, communicating with another data transmission interface apparatus through a digital transmission means for transmitting multimedia data, includes a processor for processing multimedia data; and a data converting circuit, coupled to the processor, for converting a plurality of first multimedia data sets generated from the processor into a plurality of second multimedia data sets; and for converting a plurality of first auxiliary data sets into a plurality of second auxiliary data sets. The first auxiliary data set and the second auxiliary data set include closed caption information. | 12-13-2012 |
Patent application number | Description | Published |
20120257296 | COLOR FILTER SUBSTRATE - A color filter substrate includes a transparent plate, a black matrix, a plurality of filter layers, a plurality of first support pads, and a transparent conductive layer. The transparent plate has a plane. The black matrix is disposed on the plane and has a plurality of grid areas. The filter layers are disposed on the plane and located in the grid areas respectively. The first support pads partially cover the black matrix. Each of the first support pads is located among adjacent four filter layers. An area on the black matrix covered by each of the first support pads is in a shape of a cross. The first support pads are connected to the filter layers. Each first support pad includes a first pad layer, a second pad layer, and a third pad layer. The transparent conductive layer covers the filter layers, the first support pads, and the black matrix. | 10-11-2012 |
20130057459 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, a plurality of pixel structures and a plurality of resistance compensating devices is provided. The substrate has a display region and a scanning signal input region beside the display region. The pixel structures are disposed in the display region. Each of the pixel structures includes a scan line, a data line, an active device and a pixel electrode. The data line is disposed in stagger with the scan line. The active device is electrically connected with the scan line and the data line. The pixel electrode is electrically connected with the active device. Each of the resistance compensating devices and a scan line of a corresponding pixel structure are connected in parallel. Resistances of the resistance compensating devices gradually decrease from a region close to the scanning signal input region to another region away the scanning signal input region. | 03-07-2013 |
Patent application number | Description | Published |
20100045663 | METHOD AND APPARATUS FOR IDENTIFYING VISUAL CONTENT FOREGROUNDS - A method and apparatus for identifying visual content foregrounds, the method comprises steps of: determining a 3-D opening-by-reconstruction modest structure element (B | 02-25-2010 |
20140223154 | COMPUTER SYSTEM - A computer system is disclosed. The computer system comprises a near field communication (NFC) tag and a computer. The computer comprises a flash read only memory (ROM), a chipset, an NFC module and a central processing unit (CPU). The flash ROM stores a basic input/output system (BIOS) having a default user identification (UID) and a default entry key data. The chipset comprises a keyboard buffer. The NFC module reads a UID seed from the NFC tag when the NFC tag is close to the NFC module. The CPU generates a current UID according to the UID seed and a function, and determines whether the current UID is equal to the UID. The CPU writes the default entry key data to the keyboard buffer if the current UID is equal to the UID. | 08-07-2014 |
20140245428 | COMPUTER AND CONTROL METHOD THEREOF - A computer and a control method thereof are disclosed. The computer comprises a processor, a chipset, a near field communication (NFC) module and a coprocessor. The chipset is coupled to the processor. The NFC module reads a current user identification (UID) from the NFC card when the NFC card is close to the NFC module. The coprocessor stores a default UID, and verifies whether the current UID is the same as the default UID. The coprocessor controls the chipset to execute a power-on sequence when the current UID is the same as the default UID. | 08-28-2014 |
20140337969 | PORTABLE COMPUTER AND OPERATING METHOD THEREOF - A portable computer and an operating method thereof are provided. The portable computer comprises an input device, a power button, a non-volatile memory, a central processing unit (CPU), an embedded controller (EC), and a chipset. The input device inputs a user password, and the non-volatile memory stores a default password. The EC, in a soft off status, determines whether the power button protection item is enabled. The EC locks the power button if the power button protection item is enabled. The EC determines whether the user password is the same as the default password. The EC unlocks the power button if the user password is the same as the default password. The chipset is coupled to the non-volatile memory, the CPU and the EC. | 11-13-2014 |
20140373183 | COMPUTER AND CONTROL METHOD THEREOF - A computer and a control method thereof are provided. The computer includes a power button, a flash read-only memory (ROM), a processor, a near field communication (NFC) module, a chipset, and a coprocessor. The flash ROM stores a power button protection state for the power button. The chipset is coupled to the processor and the flash ROM. The coprocessor is coupled to the power button, the NFC module, and the chipset. The coprocessor verifies whether a current user identification (UID) of a NFC card equals a default user identification (UID) after the NFC module generates an interrupt request (IRQ). The coprocessor changes the power button protection state when the current UID equals the default UID. | 12-18-2014 |
Patent application number | Description | Published |
20090012363 | ENDOSCOPE AND MAGNETIC FIELD CONTROL METHOD THEREOF - An endoscope device is provided. The endoscope device includes a capsule sensor entering a human body for detection and sending a signal, a driving device movably disposed outside of the human body and moving and rotating the capsule sensor in the human body with non-contact force for omni-directional human body detection, a data receiving device disposed outside of the human body and receiving signals from the capsule sensor, and a power supply device providing power to the driving device and the data receiving device. | 01-08-2009 |
20150087898 | CAPSULE ENDOSCOPE MAGNETIC CONTROL SYSTEM - A capsule endoscope magnetic control system includes a control handle assembly, and a capsule endoscope having a controlled unit, a wireless power receiving unit, an image capturing unit, a processing unit, and a wireless communication unit. The control handle assembly includes a magnetic control unit for generating a magnetic field and a wireless power transmission unit for generating electromagnetic waves. After the capsule endoscope is placed inside a test object, the controlled unit fixed to the outside of the capsule endoscope changes the rotational direction of the capsule endoscope according to the changes in the magnetic field. The wireless power receiving unit generates an induced current. The image capturing unit generates an image data, which is received and converted by the processing unit into an image signal, which is transmitted by the wireless communication unit to the control handle assembly. Therefore, the capsule endoscope has a long battery life. | 03-26-2015 |
Patent application number | Description | Published |
20100289529 | POWER-ON DETECTOR AND METHOD THEREOF - A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures. | 11-18-2010 |
20130301343 | THRESHOLD VOLTAGE MEASUREMENT DEVICE - A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments. | 11-14-2013 |
20140063918 | CONTROL CIRCUIT OF SRAM AND OPERATING METHOD THEREOF - A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage. | 03-06-2014 |
20160111144 | PULSE WIDTH MODULATION DEVICE - A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal. | 04-21-2016 |
Patent application number | Description | Published |
20140375489 | ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD CAPABLE OF ACHIEVING FAST SETTLING - A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit. | 12-25-2014 |
20150214969 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A multiplying digital-to-analog converter (MDAC) with high slew rate and a pipeline Analog-to-digital converter using the same. The first set of capacitors for a first input terminal of the operational amplifier (op-amp) includes active capacitors coupling the first input terminal of the op-amp to a first enhanced reference voltage or a common mode terminal in accordance with first digital bits in an amplifying phase of the MDAC, and includes a feedback capacitor coupling the first input terminal of the op-amp to a first output terminal of the op-amp in the amplifying phase. The first set of capacitors contains M capacitor cells. The feedback capacitor between the first set of capacitors contains at most M/(2 | 07-30-2015 |
20150280727 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A multiplying digital-to-analog converter (MDAC) with capacitive load reset on an operational amplifier and a pipeline analog-to-digital converter using the MDAC are disclosed. The MDAC includes an operational amplifier and first and second switched-capacitor networks sharing the operational amplifier. The operational amplifier is further coupled with first capacitive load cells when the first switched-capacitor network is coupled to the operational amplifier, and the first capacitive load cells are reset when the first switched-capacitor network is disconnected from the operational amplifier. The operational amplifier is further coupled with second capacitive load cells when the second switched-capacitor network is coupled to the operational amplifier, and the second capacitive load cells are reset when the second switched-capacitor network is disconnected from the operational amplifier. | 10-01-2015 |
20150333755 | SAMPLING CIRCUIT FOR SAMPLING SIGNAL INPUT AND RELATED CONTROL METHOD - A sampling circuit for sampling a signal input includes a signal generation circuit, a sampling switch and a control circuit. The signal generation circuit is arranged for generating a first control signal. The sampling switch has a control node, and is arranged for determining a sampling time of the signal input according to a signal level at the control node. The control circuit is arranged for controlling the signal level at the control node, wherein when the signal level at the control node corresponds to a first level, and before a signal level of the first control signal is changed in order to adjust the signal level at the control node to a second level, the control circuit couples the first control signal to the control node. | 11-19-2015 |