Liaw, TW
Been-Wei Liaw, Taichung City TW
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20150354852 | AIR CONDITIONING APPARATUS - An air conditioning apparatus includes a casing having an inlet and an outlet, an airflow import device, a nozzle, two valves disposed at two ends of the nozzle, a vacuum pump connected through the nozzle, a connecting device, a heater, a humidifier, and an airflow export device. The airflow import and export devices are disposed at positions near the inlet and the outlet inside the casing. The nozzle includes an intake portion, a throat, and an exhaust portion connected sequentially and coaxially. A cross-sectional area of the intake portion decreases gradually from one end away from the throat to the other end close to the throat. A cross-sectional area of the throat is smaller than that of the exhaust portion. The connecting device is connected to the intake portion and the exhaust portion. The heater and the humidifier are disposed between the nozzle and the outlet. | 12-10-2015 |
20150362198 | DEHUMIDIFICATION APPARATUS AND DEHUMIDIFICATION METHOD - A dehumidification apparatus suitable for collecting gas of an exterior and excluding moisture from the gas is provided. The dehumidification apparatus includes an intake tube, a throat tube, an exhaust tube, and a communication device. The intake tube has a first end portion and a second end portion opposite to each other, wherein the cross-section of the intake tube is convergent from the first end portion to the second end portion. The throat tube is connected to the second end portion. The exhaust tube is connected to the throat tube, wherein the throat tube is located between the second end portion and the exhaust tube, and the cross-section of the throat tube is less than the cross-section of the exhaust tube. The communication device is connected between the intake tube and the exhaust tube. A dehumidification method is also provided. | 12-17-2015 |
Been-Yang Liaw, New Taipei TW
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20110227113 | LEAD FRAME HAVING UL REFLECTIVE COATING - A lead frame ( | 09-22-2011 |
20110230064 | ELECTRICAL CONNECTOR AND ASSEMBLY THEREOF - An electrical connector assembly includes an electrical connector, a chip located and a printed circuit board located at opposite sides of the anisoptropic conductive film. The electrical connector has an anisoptropic conductive film and a loading mechanism. The anisoptropic conductive film includes an adhesive and a number of conductive particles dispersed in the adhesive. The anisoptropic conductive film has conductivity only in a thicknesswise direction by pressing. The loading mechanism can exert pressure on the anisoptropic conductive film so that the chip and the printed circuit board electrically couples with each other. | 09-22-2011 |
20110291152 | LED LEAD FRAME WITH WATER-REPELLENT LAYER - An LED lead frame includes a housing having a cavity for receiving an LED chip, and a pair of conductive leads mounted with the housing. Each lead includes an embedded section retained in the housing. The embedded section is plated with a silver layer thereon and a water-repellent layer disposed on the silver layer. | 12-01-2011 |
20120061810 | LED LEAD FRAME HAVING DIFFERENT MOUNTING SURFACES - An LED lead frame comprises an insulative housing including a top surface, a bottom surface, and four side surfaces connected the top surface and the bottom surface, and a cavity recessed from the top surface. A pair of conductive leads each has a portion embedded into the insulative housing and another portion exposed out of the insulative housing. The another portion includes an end portion extending downwardly along one of the side surface, a bottom soldering portion extending continuously from the end portion along the bottom surface, and a pair of side soldering portions extending upwardly from two ends of the bottom soldering portion along another two opposite side surfaces. The bottom soldering portion and the side soldering portions can be used as an alternative mounting surface. | 03-15-2012 |
20120100758 | SOCKET CONNECTOR WITH CONTACT TERMINAL HAVING OXIDATION-RETARDING PREPARATION ADJACENT TO SOLDER PORTION PERFECTING SOLDER JOINT - Provided herewith a socket connector adapted to be mounted on a substrate having a conductive element is provided, and comprises an insulative housing, the housing having an exterior side adapted to face the substrate. A stamped contact is formed from a sheet of conductive material and is adapted to mate with a conductive component and extending substantially to the exterior side of the housing. The contact has a connection portion and wherein a substantially dried preparation of oxidation retarding and solder affinity deployed on the terminal portion before the contact assembled into the connector. The connector further includes a body of reflowable, electrically conductive material associated adjacent to the connection portion adjacent the exterior side of the housing. | 04-26-2012 |
20120106118 | LED LEAD FRAME HAVING INSERT-MOLDED ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An LED lead frame includes an insulative base having a cavity on one side. A pair of conductive leads each has an end exposed in the cavity and another end extended out of insulative base. An electrostatic discharge protection device is insert-molded in the insulative base with only one side thereof exposed out of the insulative base, and is electrically interconnecting with the conductive leads. | 05-03-2012 |
20120202384 | SOCKET CONNECTOR WITH CONTACT TERMINAL HAVING OXIDATION-RETARDING PREPARATION ADJACENT TO SOLDER PORTION PERFECTING SOLDER JOINT - An electrical connector having a fusible element for mounting on a substrate includes an insulative housing and a contact terminal retained in the insulative housing. The contact terminal includes a resilient contacting arm extending beyond a mating face of the insulative housing and a soldering portion for mating with the fusible element. A gelatinous flux is deployed on the fusible element, and/or on the soldering portion, and/or between the fusible element and the soldering portion, and then flux is dried to immovably fix the fusible element with respect to the soldering portion. The dried flux will be re-juvenile to clean and remove an oxidized layer originally existed on the soldering portion so as to achieve robust welding quality. Besides, a method for trimming an electrical connector to have robust welding properties is also disclosed. | 08-09-2012 |
Been-Yang Liaw, Tu-Cheng TW
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20080299802 | BGA socket having extensible solder ball so as to compensate warpage connector housing - A solder ball is adapted for a ball grid array socket and comprises a core portion ( | 12-04-2008 |
20090163069 | Burn-in socket with plated contacts - A burn-in socket for receiving an IC package comprises a socket body, a plurality of contacts mounted in the socket body and an actuator movably mounted upon the socket body. Each contact in the socket body includes a pair of clipping arms with tip portions at free ends thereof respectively. Solder balls attached to the bottom of the IC package are respectively clipped between the pair of the tip portions and thus the IC package should be brought into electrical contact with the contacts of the burn-in socket. The tip portion is plated with a Pd—Co layer for reducing the attachment of the Sn and preventing the impedance of the contacts to increase. Meanwhile, the IC package can be sucked up successfully without absorption from the contacts of the burn-in socket. | 06-25-2009 |
20090170350 | Electrical connector - An electrical connector is for electrically connecting an electronic package with a circuit substrate. The connector includes a housing with a plurality of conductive terminals received therein, a fastening device for securing the electronic package. The fastening device includes a pressing member for pressing and securing the electronic package and a retaining member for securing the pressing member. At least one of the pressing member, the retaining member are produced from ferrite stainless steel material, and has a layer of high temperature resistant organic thin film thereon. | 07-02-2009 |
20100029120 | REINFORCED BACKPLATE FOR USE WITH ELECTRICAL CONNECTOR ASSEMBLY HAVING INSULATIVE COATING THEREON - A connector assembly includes a PCB, an insulative housing mounted on the PCB with a plurality of contacts received therein, a retention module mounted on the PCB and surrounding the insulative housing, and a backplate mounted below the PCB for reinforcing the retention module. The backplate includes a base plate having an upper surface toward a backside surface of the PCB and an insulative coating deposited on the upper surface to prevent the backplate from short-circuiting electrical components of mounted on the backside surface of the PCB. | 02-04-2010 |
20110086558 | ELECTRICAL CONTACT WITH IMPROVED MATERIAL AND METHOD MANUFACTURING THE SAME - An electrical contact material includes a base material, a first number of plating layers forming a contact section and a second number of plating layers forming a soldering section, respectively. The second number of plating layers is provided on the base material and includes a Ni-plating layer directly on the base material and an organic antioxidant-plating layer on said Ni-plating layer. | 04-14-2011 |
Been Yu Liaw, Taipei County TW
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20100046168 | Heat dissipating device - A heat dissipating device includes a plurality of heat dissipating fins are sequentially connected together to form a continuous and cascaded heat dissipating fin set. The heat dissipating fin set having an outward radial shape. The heat dissipating fins comprise at least one local arc shape. Surfaces of the heat dissipating fins having projections and depressions to enlarge a heat dissipating area. Edges of the fins are formed with curved surface corners to prevent an operator from being cut and hurt. | 02-25-2010 |
20100135031 | Heat-dissipating module and heat-dissipating apparatus for light-emitting diode - The present invention disclosed a heat-dissipating module for a light-emitting diode (LED), comprising:a LED substrate having a plurality of extending feet; a heat-dissipating device having a center portion; wherein the plurality of extending feet are bent downwards by an angel to be placed into the center portion so that the extending feet are tightly combined with the heat-dissipating device. A heat-dissipating apparatus for a light-emitting diode (LED) includes a heat-dissipating device, a LED substrate, a ring, and an electrically controlled carrier assembly. The heat-dissipating device has a hollow center potion. The LED substrate having a plurality of extending feet is bent downwards at an angle of 90 degrees. The LED substrate is placed into the hollow center potion of the heat-dissipating device so that the extending feet can be tightly combined with the heat-dissipating device. The electrically controlled carrier assembly is disposed in a lower half portion of the center potion of the heat-dissipating device, for driving at least one LED. | 06-03-2010 |
Been-Yu Liaw, Sindian City TW
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20100188848 | ELECTRO-THERMAL SEPARATION LIGHT EMITTING DIODE LIGHT ENGINE MODULE - An electro-thermal separation light emitting diode light engine module includes a heat dissipater, an illuminating module and a printed circuit board. The illuminating module is provided on the heat dissipater and is provided with at least one contact end. The printed circuit board is transfixed with at least one hole for accepting the illuminating module and is provided with a circuit for electrically connecting the contact end. Therefore, the illuminating module can be cooled directly through the heat dissipater and can be connected electrically by the circuit of the printed circuit board, achieving the practical progressiveness by providing a better heat dissipation effect and reducing cost. | 07-29-2010 |
20100188860 | LOTUS BLOSSOM HEAT DISSIPATING DEVICE - The present invention relates to a lotus blossom heat dissipating device, wherein a heat dissipating device is structured from a circuit substrate and at least one heat dissipating plate, one side of which is connected to the back of the circuit substrate. The heat dissipating plate conducts away the heat produced by light-emitting elements, and a stacking method is used to additionally assemble a plurality of the heat dissipating plates. The circuit substrate is mounted with at least one light-emitting element, from which extend electric conducting electrical elements. The circuit substrate has a plurality of holes, the heat dissipating plates having coinciding holes corresponding to the plurality of holes, with the electrical elements penetrating the aforementioned holes. Accordingly, heat produced from the activated light-emitting elements is quickly conducted away through the heat dissipating plates, thereby providing a simple structure, and achieving the objective of saving on costs. | 07-29-2010 |
Been-Yu Liaw, Hsinchu TW
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20130120999 | ILLUMINATION APPARATUS - This disclosure discloses an illumination apparatus. The illumination apparatus comprises an inner cover comprising a top surface having a first length; a pedestal on which the inner cover is disposed comprising a top surface having a second length; and a holder supporting the pedestal; wherein the first length is greater than the second length. | 05-16-2013 |
20130121002 | ILLUMINATION APPARATUS - This disclosure discloses an illumination apparatus. The illumination apparatus comprises a cover comprising a second portion and a first portion, and a light source disposed within the cover. An average thickness of the first portion is greater than that of the second portion. | 05-16-2013 |
20140362565 | LIGHT EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises: a first electrode part; a second electrode part; a third electrode part, spaced apart from the first electrode part and the second electrode part; and a light-emitting unit partially covering the first electrode part and the second electrode part and fully covering the second electrode part, the light-emitting unit having a conductive structure contacting the second electrode part. | 12-11-2014 |
20150085468 | LIGHT-EMITTING DEVICE - An embodiment of the present invention discloses a light-emitting device. The light-emitting device includes a light source configured to emit a first light at a first high temperature; and an optical element, distant from the light source, configured to generate a second light in response to an irradiation of the first light, and reach a second high temperature higher than the first high temperature under the irradiation of the first light. | 03-26-2015 |
Ben-Jie Liaw, Taoyuan City TW
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20090081549 | Electrochemical Composition and Associated Technology - A composition for use in an electrochemical redox reaction is described. The composition may comprise a material represented by a general formula M | 03-26-2009 |
Ben-Jie Liaw, Taoyuan TW
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20080308773 | NOVEL COCRYSTALLINE METALLIC COMPOUNDS AND ELECTROCHEMICAL REDOX ACTIVE MATERIAL EMPLOYING THE SAME - The present invention includes an electrochemical redox active material. The electrochemical redox active material includes a cocrystalline metallic compound having a general formula A | 12-18-2008 |
20090152512 | NOVEL COCRYSTALLINE METALLIC COMPOUNDS AND ELECTROCHEMICAL REDOX ACTIVE MATERIAL EMPLOYING THE SAME - The present invention includes an electrochemical redox active material. The electrochemical redox active material includes a cocrystalline metallic compound having a general formula A | 06-18-2009 |
Chao-Wu Liaw, New Taipei City TW
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20140118679 | Liquid-crystal compound with negative dielectric anisotropy, liquid-crystal display, and optoelectronic device - Disclosed is a liquid-crystal compound with negative dielectric anisotropy, having the chemical formula: | 05-01-2014 |
20150124210 | LIQUID CRYSTAL COMPOUND WITH NEGATIVE DIELECTRIC ANISOTROPY, LIQUID CRYSTAL DISPLAY, AND OPTOELECTRONIC DEVICE - Disclosed is a liquid crystal compound with negative dielectric anisotropy, having a general formula as Formula 1. | 05-07-2015 |
Ching-An Liaw, Hsin-Chu TW
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20080300885 | Speech communication system for patients having difficulty in speaking or writing - A speech communication system for patients having difficulty in speaking or writing comprises a display screen, a controller, a host having a storage unit for storing specific software and connected with the display screen, and a speaker connected with the host. A plurality of choices is presented on the display screen in a nine-square form or an English keyboard form for patients to select according to their needs. The controller is used for patients having difficulty in speaking or writing to move a cursor on the display screen to select any choice they need. The speaker is designed to output speech sounds of words or simple sentences in different languages corresponding to the choices patients select via the controller and thus make it possible for patients to communicate with others. | 12-04-2008 |
Chi-Song Liaw, Kaohsiung City TW
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20150183910 | METHOD FOR PREPARING A FLAME RETARDANT MODIFIED ACRYLONITRILE-BASED COPOLYMER AND A FLAME RETARDANT FIBROUS MATERIAL - A method for preparing a flame retardant modified acrylonitrile-based copolymer, includes: prepolymerizing a first composition to obtain a first prepolymer solution including a first prepolymer; prepolymerizing a second composition to obtain a second prepolymer solution including a second prepolymer; and mixing the first and second prepolymer solutions and subjecting a mixture of the first and second prepolymers to polymerization to obtain a flame retardant modified acrylonitrile-based copolymer solution containing a flame retardant modified acrylonitrile-based copolymer. | 07-02-2015 |
Chorng-Wei Liaw, Hsinchu County TW
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20130200499 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device which includes the following components. A substrate with a first conductivity type has a cell region and a peripheral region thereon, wherein the peripheral region surrounds the cell region. An epitaxial layer having the first conductivity type is disposed on the substrate. A first spiral-shaped region having a second conductivity type is embedded in the epitaxial layer within the peripheral region and encircles the cell region. | 08-08-2013 |
Der-Jang Liaw, Taipei City TW
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20090023877 | Norbornene monomers with fluorene group and polymer material thereof - Norbornene monomers with fluorene group and polymer material thereof are disclosed. The norbornene monomers with fluorene group are prepared by Diels-Alder reation. The Norbomene monomers containing fluorene groups are highly active for ring-opening-metathesis polymerization (ROMP), and the molecular weight and PDI value of the obtained polymers are controllable. | 01-22-2009 |
20090043059 | Norbornene monomers with an epoxy group and polymer material thereof - Norbornene monomers with epoxy groups and polymer materials thereof are disclosed. The Norbornene monomers with epoxy groups are prepared by Diels-Alder reaction. The Norbornene monomers with epoxy groups are highly active for ring-opening-metathesis polymerization (ROMP), and the molecular weight and PDI value of the obtained polymers are controllable. | 02-12-2009 |
20110092657 | Novel Polymer and Copolymer and Method of Making the Same - The present invention discloses a polymer and a copolymer and a method of making the same. The monomer of the polymer of the present invention includes a bi-triphenylamine functional group having a first end and a second end; a fluorene functional group bonded to the first end; and at least two phenyl isopropyl group bonded to the second end. | 04-21-2011 |
20110275781 | Nitro compound, amine compound, polyimide and polyimide copolymer derived therefrom - A polyimide represented by formula (6) is provided. The polyimide is fabricated by performing a polycondensation reaction with a amine compound shown in formula (4) and a dianhydride compound shown in formula (5) as monomers. In formulas (5) and (6), Ar represents aromatic group, and n represents a positive integer. | 11-10-2011 |
20110275783 | Nitro compound, amine compound and polyamide derived therefrom - A polyamide represented by formula (6) is provided. The polyamide is fabricated by performing a polycondensation reaction with amine compound shown in formula (4) and an acid or derivative thereof shown in formula (5) as monomers. In formulas (5) and (6), X represents aromatic groups or aliphatic groups. In formula (5), R represents OH group or halogen. | 11-10-2011 |
20120017994 | CONJUGATED POLYMER, METHOD FOR PREPARING THE SAME, AND OPTOELECTRONIC DEVICE EMPLOYING THE SAME - The invention provides a conjugated polymer, a method for preparing the same, and optoelectronic devices employing the same. The conjugated polymer includes a structure represented by Formula (I), | 01-26-2012 |
20120277402 | DINITRO COMPOUND, DIAMINE COMPOUND, POLYAMIDE, AND OPTOELECTRONIC DEVICE - A dinitro compound, a diamine compound, a polyamide (PA) derived therefrom, and an optoelectronic device are provided. The PA is fabricated by performing a polycondensation reaction using the foregoing diamine compound and a diacyl chloride compound shown in formula (3) as monomers, and thus represented by formula (4). In formulas (3) and (4), X represents an aromatic group or an aliphatic group. The resultant novel PA can be applied to an optoelectronic device. Since the foregoing compounds have carbazole and pyridine groups, the PA is characterized by excellent solubility, a high glass transition temperature, thermal stability, excellent optical properties, and acidichromism. | 11-01-2012 |
Der-Jang Liaw, Taipei TW
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20090247717 | NEW DINITRO COMPOUND AND ITS CORRESPONDING DIAMINE CONTAINING HETEROCYCLIC THERMAL STABLE COMPOUND AND ORGANOSOLUBLE POLYIMIDE AND POLYIMIDE COPOLYMER - A polyimide shown in formula (4) is provided. The polyimide is fabricated by performing a polycondensation reaction with diamine compound shown in formula (2) and various commercial or synthesized dianhydride compounds shown in formula (3) as monomers. In addition, polyimide copolymers are synthesized by various ratios of diamines shown in formulas (2), (7) and (8-1) to (8-7) and a dianhydride compound shown in formula (6). In formulas (3) and (4), Ar represents aromatic groups. In formula (6), X represents aromatic groups or alicyclic groups. In formula (7), n=1 to 10. | 10-01-2009 |
20100087659 | NORBORNENE COMPOUNDS WITH CROSS-LINKABLE GROUPS AND THEIR DERIVATIVES - The present invention provided a norbornene compound with cross-linkable groups and their derivative polymers, wherein said cross-linkable groups were olefin or epoxy groups. Norbornene polymers with cross-linkable side chain and their block copolymers as well as modified derivatives were prepared via living ring-open metathesis polymerization method. The resulting polymers with excellent solubility and optic properties had narrow molecular weight distribution, well-controlled molecular weight, small refraction index and high transparency. They were also suitable for preparing hybrid materials with high thermal stability and chemical resistance. | 04-08-2010 |
20110092666 | Pyrene-containing norbornene methylene amine and polymer thereof, and method for manufacturing the polymer - The present invention discloses a pyrene-containing norbornene methylene amine which can be synthesized by 5-(amino methyl)bicycle[2.2.1]hept-2-ene (NBMA) and 1-bromopyrene. The pyrene-containing norbornene methylene amine can be used as a monomer for synthesizing a polymer containing pyrene side chain via Ring-Opening Metathesis Polymerization (ROMP). The polymer has good transmittance, optical and thermal properties. | 04-21-2011 |
Der-Jang Liaw, Tai-Chung City TW
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20120095163 | Polymerization method for acrylic latex without emulisifier - The present invention provides a polymerization method for acrylic latex without emulsifier, in which a reaction system is formed from 40˜60 wt % of pure water and 2˜9 wt % of carboxylic acid monomers with carbon-carbon double bond polymerizable functional groups (A), and 40˜50 wt % of methyl methacrylate or acrylate monomers (B), and 0.2˜2.0 wt % of inorganic alkaline solution is first used to adjust the pH value of the reaction system to within a pH range of 9.0˜13.0, then 0.2˜1.0 wt % of peroxide sulfates are used as initiators, and emulsification polymerization is carried out. At the end of the reaction, organic amine compounds are used to adjust the pH value of the obtained aqueous resin latex to within the pH range 7.0˜9.5. Particle diameters of the manufactured aqueous resin latex are approximately 100˜30 nm, uniformly distributed and have excellent outward appearance. Moreover, acid value is low at 3.5˜6.5 mgKOH/g, and Its specific gravity is approximately 1.07, slightly greater than that of water; storage stability is excellent, with good permeability that facilitates construction. Moreover, water resisting property as a dry film coating is good, tensile strength is excellent, and provides superior abrasion performance. | 04-19-2012 |
Der-Jang Liaw, Taichung City TW
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20140179878 | DINITRO MONOMER, DIAMINE MONOMER, POLYIMIDE AND MODIFIED POLYIMIDE - A polyimide including a structure shown as Formula II is provided, | 06-26-2014 |
Jane-Sunn Liaw, Taichung City TW
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20100071405 | TWO-STAGE EXPANSION COOLING SYSTEM AND EVAPORATOR THEREOF - An evaporator, applicable to a two-stage expansion cooling system, is used for receiving a high-pressure liquid working fluid. The evaporator includes a thermal-conductive block having a channel system. The channel system includes a high-pressure channel, a low-pressure channel, and a second stage expansion channel. The second stage expansion channel has an input end and an output end. The input end is communicated with the high-pressure channel. The output end is communicated with the low-pressure channel, and has a cross-sectional area smaller than that of the low-pressure channel. The high-pressure liquid working fluid flows into the thermal-conductive block from the high-pressure channel, and then enters the second stage expansion channel through the input end. A part of the high-pressure liquid working fluid flowing out of the output end expands into a saturated low-pressure liquid working fluid and enters the low-pressure channel. | 03-25-2010 |
20150159935 | APPARATUS WITH DEHUMIDIFICATION AND DEFROSTING ABILITIES AND CONTROLLING METHOD THEREOF - An apparatus with dehumidification and defrosting abilities comprises a compressor, an indoor heat exchanger, an outdoor heat exchanger, a four-way valve and a means for refrigerant flow controlling. The compressor is coupled to the four-way valve. The four-way valve is coupled to the outdoor heat exchanger. The indoor heat exchanger is coupled to the four-way valve. The means for refrigerant flow controlling is respectively coupled to the indoor heat exchanger, the outdoor heat exchanger and the four way valve, to control mixing a low-temperature refrigerant and a high-temperature before flowing into the indoor heat exchanger, or to control mixing a low-temperature refrigerant and a high-temperature refrigerant before flowing into the compressor, or control mixing a low-temperature refrigerant and a high-temperature refrigerant before flowing into the outdoor heat exchanger. | 06-11-2015 |
Jhon Jhy Liaw, Zhubdong Township TW
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20150371701 | MEMORY CHIP AND LAYOUT DESIGN FOR MANUFACTURING SAME - An embedded synchronous random access memory (SRAM) chip, includes a first single-port (SP) SRAM macro and a second SP macro. The first macro includes a first periphery circuit, and a plurality of first SRAM cells. The second macro includes a second periphery circuit, and a plurality of second SRAM cells. Further, each cell of the plurality of first SRAM cells is electrically connected to a write-assist circuitry, wherein the write assist circuitry is configured to assist the write cycle capability of each cell of the plurality of first SRAM cells. Further, each cell of the plurality of second SRAM cells do not include write assist circuitry. | 12-24-2015 |
Jhon Jhy Liaw, Zhudong Township TW
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20100193877 | Memory Array Structure With Strapping Cells - A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells. | 08-05-2010 |
20100213552 | Cell Structure for Dual Port SRAM - An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected. | 08-26-2010 |
20110069527 | ROM CELL AND ARRAY STRUCTURE - A semiconductor memory cell array includes an elongated continuous active region. First and second pass transistors are formed in the elongated continuous active region and form part of first and second adjacent memory cells, respectively, of a column of memory cells in the array. An isolation transistor is formed in the elongated continuous active region between the first and second pass transistors and biased in an off state. First and second word lines are coupled to the gates of the pass transistors for applying a reading voltage. The array includes a differential bit line pair including first and second bit lines, a first logic value being encoded into the memory cells by connecting the pass transistors to the first bit line and a second logic value being encoded into the memory cells by connecting the pass transistors to the second bit line. | 03-24-2011 |
20110075470 | EMBEDDED SRAM STRUCTURE AND CHIP - An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is defined by a first X-pitch and a first Y-pitch, the X-pitch being longer than the Y-pitch. A plurality of logic transistors are formed outside of the first SRAM array, the plurality of logic transistors including at least first and second logic transistor having first and second gate pitches defined between their source and drain contacts. The second gate pitch is the minimum logic gate pitch for the plurality of logic transistors. The first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one. | 03-31-2011 |
20110133285 | SRAM Structure with FinFETs Having Multiple Fins - A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor. | 06-09-2011 |
20110182098 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE SAME - An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a direction a first longitudinal direction. | 07-28-2011 |
20110195564 | Memory Cell Layout - A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved. | 08-11-2011 |
20110222332 | Fully Balanced Dual-Port Memory Cell - The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU | 09-15-2011 |
20110317477 | CELL STRUCTURE FOR DUAL-PORT SRAM - The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12. | 12-29-2011 |
20110317485 | STRUCTURE AND METHOD FOR SRAM CELL CIRCUIT - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a first and a second pull-up devices; a first and a second pull-down devices configured with the first and second pull-up devices to form two cross-coupled inverters for data storage; and a first and second pass-gate devices configured with the two cross-coupled inverters to form a port for data access, wherein the first and second pull-down devices each includes a first channel doping feature of a first doping concentration, and the first and second pass-gate devices each includes a second channel doping feature of a second doping concentration greater than the first doping concentration. | 12-29-2011 |
20120001197 | LAYOUT FOR MULTIPLE-FIN SRAM CELL - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region. | 01-05-2012 |
20120149171 | Shallow Trench Isolation with Improved Structure and Method of Forming - A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width. | 06-14-2012 |
20120223395 | ROM CELL CIRCUIT FOR FINFET DEVICES - The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a power line, and each cell of a second subset of ROM cells has a source electrically isolated. | 09-06-2012 |
20120319212 | SRAM Structure with FinFETs Having Multiple Fins - A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor. | 12-20-2012 |
20130077375 | LAYOUT FOR SEMICONDUCTOR MEMORIES - A semiconductor memory includes a first conductive layer including a first pair of bit lines coupled to a first bit cell and a second conductive layer including a second pair of bit lines coupled to the first bit cell. The first and second conductive layers are vertically separated from each other. | 03-28-2013 |
20130121087 | SEMICONDUCTOR MANUFACTURING METHOD - A memory bit cell includes a latch, a write port coupled to the latch, and a read port coupled to the latch. The write port includes a first set of devices having a first threshold voltage and a second set of devices having a second threshold voltage that is greater than the first threshold voltage. The read port includes a third set of devices having a third threshold voltage that is less than the first threshold voltage. | 05-16-2013 |
20130122709 | INVERSE SPACER PROCESSING - A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature. | 05-16-2013 |
20130141962 | Methods and Apparatus for finFET SRAM Arrays in Integrated Circuits - Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y | 06-06-2013 |
20130141963 | Methods and Apparatus for FinFET SRAM Cells - Methods and apparatus for providing finFET SRAM cells. An SRAM cell structure is provided including a central N-well region and a first and a second P-well region on opposing sides of the central N-well region, having an area ratio of the N-well region to the P-well regions between 80-120%, the SRAM cell structure further includes at least one p-type transistor formed in the N-well region and having a gate electrode comprising a gate and a gate dielectric over a p-type transistor active area in the N-well region; and at least one n-type transistor formed in each of the first and second P-well regions and each n-type transistor having a gate electrode comprising a gate and a gate dielectric over an n-type transistor active area in the respective P-well region. Methods for operating the SRAM cell structures are disclosed. | 06-06-2013 |
20130154027 | Memory Cell - A memory cell and array and a method of forming a memory cell and array are disclosed. An embodiment is a memory cell comprising first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively. | 06-20-2013 |
20130181297 | SRAM Cells and Arrays - Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction. | 07-18-2013 |
20130194859 | METHOD AND APPARATUS FOR SWITCHING POWER IN A DUAL RAIL MEMORY - A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column. | 08-01-2013 |
20130235652 | STRUCTURE AND METHOD FOR A SRAM CIRCUIT - The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size; and a second SRAM cell having a second cell size greater than the first cell size. The first SRAM cell includes first n-type field effect transistors (nFETs) each having a first gate stack. The second SRAM cell includes second nFETs each having a second gate stack different from the first gate stack. | 09-12-2013 |
20130242633 | Apparatus for ROM Cells - A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a first second-level contact formed on the first first-level contact, wherein the first second-level contact shifts in a first direction with reference to the first first-level contact. The ROM cell further comprises a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is aligned with the first first-level contact and a second second-level formed on the second first-level contact, wherein the second second-level contact shifts in a second direction with reference to the second first-level contact, and wherein the first direction is opposite to the second direction. | 09-19-2013 |
20130242644 | MEMORY CELL AND MEMORY ARRAY - A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters. | 09-19-2013 |
20130256764 | GATE STACK OF FIN FIELD EFFECT TRANSISTOR - The description relates to a gate stack of a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a substrate including a first surface and an insulation region covering a portion of the first surface, where a top of the insulation region defines a second surface. The FinFET further includes a fin disposed through an opening in the insulation region to a first height above the second surface, where a base of an upper portion of the fin is broader than a top of the upper portion, wherein the upper portion has first tapered sidewalls and a third surface. The FinFET further includes a gate dielectric covering the first tapered sidewalls and the third surface and a conductive gate strip traversing over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction of the fin. | 10-03-2013 |
20130258749 | Apparatus for High Speed ROM Cells - A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line. | 10-03-2013 |
20130258759 | Methods and Apparatus for SRAM Cell Structure - An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure. | 10-03-2013 |
20130270652 | Apparatus for FinFETs - A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin. | 10-17-2013 |
20130272056 | Apparatus for SRAM Cells - A memory cell comprises a first word line in a first interconnect layer, a first VSS line, a first bit line, a power source line, a second bit line and a second VSS line formed a second interconnect layer, a second word line in a third interconnect layer. The memory cell further comprises a word line strap structure formed between the power source line and the second bit line, wherein the word line strap structure couples the first word line and the second word line. | 10-17-2013 |
20130292777 | Structure for FinFETs - An SRAM array is formed by a plurality of FinFETs formed by fin lines. Each fin line is formed in a substrate, wherein a bottom portion of the fin line is enclosed by an isolation region and an upper portion of the fin line protrudes above a top surface of the isolation region. From a first cross sectional view of the SRAM array, each fin line is of a rectangular shape. From a second cross sectional view of the SRAM array, the terminals of each fin line is of a tapered shape. | 11-07-2013 |
20130334595 | STRUCTURE AND METHOD FOR A FIELD EFFECT TRANSISTOR - Provided is one embodiment of a semiconductor structure that includes a STI feature, wherein the STI feature is a continuous feature and includes a first portion in a first region and a second portion in a second region, and the first portion is recessed relative to the second portion; an active region bordered by the STI feature; a gate stack disposed on the active region and extended in a first direction to the first region of the STI feature; source and drain features formed in the active region and interposed by the gate stack; and a channel formed in the active region and spanned between the source and drain features in a second direction being different from the first direction. The channel includes top portion having a width W in the first direction and two side portions each having a height H less than the width W. | 12-19-2013 |
20130334614 | STRUCTURE AND METHOD FOR FINFET DEVICE - The present disclosure provides one embodiment of a field effect transistor (FET) structure. The FET structure includes shallow trench isolation (STI) features formed in a semiconductor substrate; a plurality of semiconductor regions defined in the semiconductor substrate and isolated from each other by the STI features; and a multi-fin active region of a first semiconductor material disposed on one of the semiconductor regions of the semiconductor substrate. | 12-19-2013 |
20140001562 | Integrated Circuit Having FinFETS with Different Fin Profiles | 01-02-2014 |
20140022852 | DATA INVERSION FOR DUAL-PORT MEMORY - A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch. | 01-23-2014 |
20140035056 | SRAM Cell Connection Structure - A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor. The conductive feature further includes a second leg having a second extending direction. The first longitudinal direction and the second extending direction are un-perpendicular and un-parallel to each other. The second leg interconnects the drain of the first pull-up transistor and a gate of the second pull-up transistor. | 02-06-2014 |
20140097506 | FIN FIELD EFFECT TRANSISTOR, AND METHOD OF FORMING THE SAME - The description relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a fin having a first height above a first surface of a substrate, where a portion of the fin has first tapered sidewalls, and the fin has a top surface. The FinFET further includes an insulation region over a portion of the first surface of the substrate, where a top of the insulation region defines a second surface. The FinFET further includes a gate dielectric over the first tapered sidewalls and the top surface. The FinFET further includes a conductive gate strip over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction perpendicular to the first height, and a first width between the second tapered sidewalls in the longitudinal direction is greater at a location nearest to the substrate than a second width at a location farthest from the substrate. | 04-10-2014 |
20140131813 | Cell Layout for SRAM FinFET Transistors - An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The at least one active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells. | 05-15-2014 |
20140133218 | Memory Cell - A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively. | 05-15-2014 |
20140151811 | SRAM Cell Comprising FinFETs - A Static Random Access Memory (SRAM) cell includes a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET, and a first pull-down FinFET and a second pull-down FinFET forming cross-latched inverters with the first pull-up FinFET and the second pull-up FinFET. A first pass-gate FinFET is connected to drains of the first pull-up FinFET and the first pull-down FinFET. A second pass-gate FinFET is connected to drains of the second pull-up FinFET and the second pull-down FinFET, wherein the first and the second pass-gate FinFETs are p-type FinFETs. A p-well region is in a center region of the SRAM cell and underlying the first and the second pull-down FinFETs. A first and a second n-well region are on opposite sides of the p-well region. | 06-05-2014 |
20140151812 | Contact Plugs in SRAM Cells and the Method of Forming the Same - A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening. | 06-05-2014 |
20140153321 | Methods and Apparatus for FinFET SRAM Arrays in Integrated Circuits - Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit are provided. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y | 06-05-2014 |
20140153322 | SRAM Cell Comprising FinFETs - A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals. | 06-05-2014 |
20140153323 | Methods for Operating SRAM Cells - A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other. | 06-05-2014 |
20140231921 | APPARATUS FOR HIGH SPEED ROM CELLS - A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line. | 08-21-2014 |
20140254246 | Dual-port SRAM Systems - Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit. Various layout schemes for the dual-port SRAM cell are further disclosed. A gate electrode serves as the gate for a pull-down transistor and a pull-up transistor, a gate of a first partial dummy transistor, and a gate of a second partial dummy transistor. A butt contact connects a long contact to the gate electrode. The long contact further connects to a drain of a pull-down transistor, a drain of a pull-up transistor, a drain of a first pass gate, and a drain of a second pass gate, wherein the first pass gate and the second pass gate share an active region. | 09-11-2014 |
20140347908 | SEMICONDUCTOR MEMORY AND METHOD OF MAKING THE SAME - A semiconductor cell comprises a plurality of metal layers. A first layer comprises a VDD conductor, a bit-line, and a complimentary bit-line. Each of the VDD conductor, the bit-line, and the complementary bit-line extend in a first direction. A second layer comprises a first VSS conductor and a first word-line. The VSS conductor and the first word-line extend in a second direction different than the first direction. A third layer comprises a second VSS conductor. The second VSS conductor extends in the first direction. A fourth layer comprises a second word-line. The second word-line extends in the second direction. The first word-line is electrically coupled to the second word-line. | 11-27-2014 |
20140369112 | SEMICONDUCTOR MEMORY - A semiconductor memory is disclosed that includes a first data line, a second data line, a first coupling line and a second coupling line. The first coupling line is configured to capacitively couple the first coupling line with the first data line. The second coupling line is configured to capacitively couple the second coupling line with the second data line. | 12-18-2014 |
20140374831 | Embedded SRAM and Methods of Forming the Same - A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes. | 12-25-2014 |
20150016173 | ROM Chip Manufacturing Structures - An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure. | 01-15-2015 |
20150029785 | METHODS FOR OPERATING A FINFET SRAM ARRAY - A method of operating an SRAM array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply CVdd may be applied to terminals of the cross coupled inverter pair. The first cell positive voltage supply CVdd may be varied relative to the word line voltage during a selected operation of the plurality of bit cells | 01-29-2015 |
20150115334 | Gate Device Over Strained Fin Structure - A method for forming a semiconductor device includes forming a fin structure on a substrate, forming a shallow trench isolation region adjacent the fin structure so that an upper portion of the fin structure is exposed, forming a dummy gate over the exposed fin structure, forming an interlayer dielectric layer around the dummy gate, removing the dummy gate to expose the fin structure, and after removing the dummy gate, introducing a strain into a crystalline structure of the exposed fin structure. | 04-30-2015 |
20150194190 | METHOD AND APPARATUS FOR SWITCHING POWER IN A DUAL RAIL MEMORY - A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column. | 07-09-2015 |
20150194205 | Dual-port SRAM Systems - Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises: a data latch storage unit comprising a first terminal and a second terminal; a first dummy circuit coupled to the first terminal of the data latch storage unit, the first dummy circuit comprising a first partial dummy transistor and a second partial dummy transistor, wherein the first partial dummy transistor is formed in a first active area of a substrate and the second partial dummy transistor is formed in a second active area of the substrate; and a first gate electrode extending over an edge of the first active area and over an edge of the second active area, wherein the edges of the first active area and the second active area are disposed within a width of the first gate electrode. | 07-09-2015 |
20150200010 | Memory Cell - Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh. | 07-16-2015 |
20150206890 | Cell Layout for SRAM FinFET Transistors - An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells. | 07-23-2015 |
20150221655 | SRAM Cell Connection Structure - A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor. The conductive feature further includes a second leg having a second extending direction. The first longitudinal direction and the second extending direction are un-perpendicular and un-parallel to each other. The second leg interconnects the drain of the first pull-up transistor and a gate of the second pull-up transistor. | 08-06-2015 |
20150248521 | Methods and Apparatus for SRAM Cell Structure - An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure. | 09-03-2015 |
20150255462 | Structure for FinFETs - A FinFET device comprises a well over a substrate, an isolation region over the well and a fin line over the well and surrounded by the isolation region, wherein the fin line is wrapped by a first gate electrode structure to form a first transistor and an end of the fin line is of a tapered shape. | 09-10-2015 |
20150310908 | MEMORY ARRAY - A memory array includes a first memory cell and a second memory cell aligned along a column direction. Each of the first memory cell and the second memory cell includes a pair of cross-coupled inverters, a first switch on a first side, along the column direction, of the pair of cross-coupled inverters, a second switch aligned with the first switch along the column direction, on a second side of the pair of cross-coupled inverters opposing to the first side, a third switch on the first side of the pair of cross-coupled inverters, and a fourth switch aligned with the third switch along the column direction, on the second side of the pair of cross-coupled inverters. The memory array also includes a first data line, a first complementary data line, a second data line and a second complementary data line. | 10-29-2015 |
20150318289 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes a plurality of memory cells At least one of the memory cells includes a plurality of transistors with vertical-gate-all-around configurations and a plurality of active blocks. A portion of at least one of the active blocks serves as a source or a drain of one of the transistors. | 11-05-2015 |
20150318290 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes an array of memory cells. At least one of the memory cells includes a plurality of transistors with vertical-gate-all-around configurations and a plurality of active blocks. A portion of one of the active blocks serves as a source or a drain of one of the transistors. The active blocks in any adjacent two of the memory cells are isolated from each other. | 11-05-2015 |
20150357327 | ROM Chip Manufacturing Structures - An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure. | 12-10-2015 |
Jhon Jhy Liaw, Hsinchu TW
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20110143514 | MRAM cell structure - Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure. | 06-16-2011 |
20120170358 | MRAM cell structure - Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around | 07-05-2012 |
20140232009 | MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF - A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and a second landing pad is arranged at a first level. A second conductive layer is coupled to the first conductive layer and arranged at a second level different from the first level. The second conductive layer is routed to define the first voltage line and the second voltage line. A third conductive layer is coupled to the second conductive layer and arranged at a third level different from the first level and the second level. The third conductive layer is routed to define the word line. | 08-21-2014 |
Jhon Jhy Liaw, Hsinchu County TW
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20120001232 | ROM CELL CIRCUIT FOR FINFET DEVICES - The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a Vss line, and each cell of a second subset of ROM cells has a source electrically isolated. Each cell of the first subset of ROM cells includes a drain contact having a first contact area and a source contact having a second contact area at least 30% greater than the first contact area. | 01-05-2012 |
20130200395 | LAYOUT FOR MULTIPLE-FIN SRAM CELL - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region. | 08-08-2013 |
20130235640 | SEMICONDUCTOR MEMORY AND METHOD OF MAKING THE SAME - A semiconductor memory includes a first bit cell within an integrated circuit (IC), and a second bit cell within the same IC. The first bit cell has a first layout, and the second bit cell has a second layout that differs from the first layout. | 09-12-2013 |
20130280903 | Memory Cell Layout - A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved. | 10-24-2013 |
20140185365 | Dual-Port SRAM Connection Structure - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD-11 and PD-12) of the first inverter; and a second contact feature contacting second two pull-down devices (PD-21 and PD-22) of the second inerter. | 07-03-2014 |
20150021701 | MEMORY CELL ARRAY - A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line. | 01-22-2015 |
20150235905 | STRUCTURE AND METHOD FOR FINFET DEVICE - A method of forming a fin field effect transistor (FinFET) structure including forming a plurality of shallow trench isolation (STI) features in a semiconductor substrate, thereby defining a plurality of bulk-semiconductor areas separated from each other by the STI features. The method then forms a first hard mask layer on the semiconductor substrate, the first hard mask layer being patterned to have a plurality of openings over one of the bulk-semiconductor areas. A second semiconductor material is then grown on the semiconductor substrate within the plurality of openings of the first hard mask layer, thereby forming a multi-fin active region having multiple fin features within the one of the bulk-semiconductor areas. | 08-20-2015 |
20150243667 | Structure and Method for FinFET SRAM - Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure. | 08-27-2015 |
20150303270 | CONNECTION STRUCTURE FOR VERTICAL GATE ALL AROUND (VGAA) DEVICES ON SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed. | 10-22-2015 |
20150340083 | DUAL-PORT SRAM CONNECTION STRUCTURE - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD- | 11-26-2015 |
Jhon-Jhy Liaw, Taiwan TW
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20080217701 | Design solutions for integrated circuits with triple gate oxides - An integrated circuit includes a first core circuit and a second core circuits. The first core circuit includes a first MOS device, wherein a first gate dielectric of the first MOS device has a first thickness. The second core circuit includes a second MOS device, wherein a second gate dielectric of the second MOS device has a second thickness less than the first thickness. A first power supply line having a first power supply voltage is connected to the first and the second core circuits a first power supply voltage. | 09-11-2008 |
Jhon-Jhy Liaw, Shin Chu TW
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20090286395 | Butted Source Contact and Well Strap - A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region. | 11-19-2009 |
Jiahorng Liaw, Taipei City TW
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20140072801 | PEPTIDE NANOTUBE DEVICE AND MANUFACTURING METHOD THEREOF - A peptide nanotube (PNT) device and method of manufacturing thereof are disclosed herein. The PNT device comprises PNTs composed of cyclo-(D-Trp-Tyr) peptide and a matrix, including biomolecules, complexed with the PNTs. The PNT device is biodegradable and biocompatible, as well as capable of being uptake by mammalian cells. Wherein, the biomolecules comprise peptides, proteins, nucleic acids including DNA, shRNA and siRNA, and drugs. The method for manufacturing PNT device comprises: dissolving a cyclo-(D-Trp-Tyr) peptide powder in a solvent to be a solution in a container; incubating the solution at a predetermined temperature for a predetermined time for the solvent to evaporate to obtain PNTs formed of cyclo-(D-Trp-Tyr) peptide; and mixing the PNTs with a matrix including biomolecules to obtain the PNT device. | 03-13-2014 |
Jian-Shiou Liaw, Taichung City TW
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20120151782 | HAND TOOL HAVING A RECIPROCALLY DRIVING MECHANISM - A hand tool having a reciprocally driving mechanism includes a driver, a body and a blade assembly. The driver has a driving shaft and a trigger. The driving shaft is controlled by the trigger and has a gear portion. The body has a driving gear having a teeth portion disposed on a top of the driving gear for engaging the gear portion. The driving gear has a stub eccentrically disposed on a bottom of the driving gear for driving a driving unit to move and to relatively drive a driven rod. The driven rod is connected with the blade assembly. The driving shaft is able to drive the blade assembly to reciprocally move for providing a higher torsion, a higher driving force, and a higher cutting speed, such that the hand tool is suitable for cutting a thicker workpiece. | 06-21-2012 |
Ming Jiun Liaw, Miaoli TW
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20100165174 | AUTOMATIC FOCUSING METHOD AND DEVICE IN HIGH-NOISE ENVIRONMENT - An automatic focusing method and device in a high-noise environment are used for determining a focusing distance between a digital imaging device and an object to be photographed. The automatic focusing method includes the steps of capturing M pre-photographed images at different object distances respectively; loading the pre-photographed images; superposing every N (N07-01-2010 | |
Ming Jiun Liaw, Mialoi County TW
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20100165177 | AUTOMATIC FOCUSING METHOD IN HIGH-NOISE ENVIRONMENT AND DIGITAL IMAGING DEVICE USING THE SAME - An automatic focusing method in a high-noise environment and a digital imaging device using the same are used for determining an object distance. The method includes taking two digital images at a farthest object distance and taking two digital images at a nearest object distance, under a first exposure condition and a second exposure condition; capturing digital images under the first exposure condition at a plurality of different object distances other than the farthest and nearest object distances; selecting at least two images captured at adjacent object distances to create a composite image; calculating an object distance of the composite image; calculating high-frequency signals of the second farthest object distance image, the second nearest object distance image, and the composite image in the focusing frame; determining from the images an object distance corresponding to the maximum high-frequency signal; and moving an automatic focusing lens to the object distance. | 07-01-2010 |
20100310162 | COLOR INTERPOLATION METHOD FOR DIGITAL IMAGE - A color interpolation method for a digital image is described, includes the following steps. Edge information is generated according to the Bayer pattern. A Bayer pattern image is processed by a horizontal band-pass filter and a vertical band-pass filter to generate a horizontal edge signal and a vertical edge signal. A weight process implements a weight adjustment on the horizontal edge signal and the vertical edge signal to generate a luminance signal and outputs the luminance signal to a subtraction unit. The subtraction unit carries out an operation according to the Bayer pattern image and an output result of the weight process to generate a chrominance pattern. The chrominance pattern is compensated through a chrominance interpolation process, so as to generate image signal patterns of different colors. The image signal patterns of different colors are output to an adder for an add operation, thereby outputting a complete color image. | 12-09-2010 |
Ming-Jiun Liaw, Miaoli County TW
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20090316019 | TONE ADJUSTMENT METHOD FOR DIGITAL IMAGE AND ELECTRONIC APPARATUS USING THE SAME - A tone adjustment method for a digital image and an electronic apparatus using the same are presented. The method includes steps. A digital image is loaded. A detail image layer and a primary image layer are generated according to the digital image. A tone mapping procedure is performed on the primary image layer, for generate a tone mapping layer. A detail gain lookup table is loaded and then a corresponding gain is looked up according to each pixel value in the primary image layer, for generate a detail gain adjustment layer. A detail gain control procedure is performed and then a detail gain adjustment is performed on the detail gain adjustment layer and the detail image layer, for generate a gain correction layer. The gain correction layer and the tone mapping layer are combined, and then a combined layer is output, thereby completing the tone adjustment for the digital image. | 12-24-2009 |
20090322936 | AUTO FOCUSING METHOD FOR FACE DETECTION OF DIGITAL IMAGING DEVICE - A auto focusing method for face detection of a digital imaging device is described, in which high-frequency information of a focusing area is increased according to a size, a position of a face of a person to be shot, and an image area at least covering the face and body of the person, thereby improving a focusing success ratio. | 12-31-2009 |
20130154514 | VOLTAGE-CONTROLLED LIGHT DIFFUSING MODULE, FLASH LAMP MODULE AND CONTROLLING METHOD THEREOF BASED ON FACE INFORMATION - A voltage-controlled light diffusing module, a flash lamp module and a controlling method thereof are provided. The voltage-controlled light diffusing module includes a light diffuser, a driving circuit and an information processing unit. The information processing unit receives face information for deciding a driving voltage of the driving circuit, so as to change transmission of the light diffuser. | 06-20-2013 |
20130169758 | THREE-DIMENSIONAL IMAGE GENERATING DEVICE - A three-dimensional (3D) image generating device including a first memory unit, a first (master) processor, and a second (slave) processor is provided. The first processor and the second processor respectively include a first image processing unit and a second image processing unit. The first processor further includes a data access unit. The first image processing unit and the second image processing unit respectively receive images representing a first human eye and a second human eye and generate a first image and a second image through image processing. The data access unit receives the first image from the first image processing unit and writes it into the first memory unit according to a predetermined 3D image format. The second image processed by the second image processing unit is transmitted to the data access unit and written into the first memory unit according to the predetermined 3D image format. | 07-04-2013 |
20130278819 | FLASH LIGHT DEVICE - The invention provides a flash light device, which includes a light source, a light diffuser and a light diffuser's driving unit. The light diffuser's driving unit provides the light diffuser with a required driving voltage according to a voltage information, in which the voltage information is determined according to an original image without light-complementing of the light source and a pre-flash image with light-complementing of the light source. | 10-24-2013 |
20140029929 | AUTO-FOCUS METHOD - An auto-focus (AF) method adapted for an image capturing device includes following steps. When a first press signal generated by a user pressing a button of the image capturing device is detected, a local peak searching method is applied to perform an AF procedure. It is determined whether a second press signal generated by the user pressing the button is detected. If not, it is determined whether a first released signal generated by the user releasing the button is detected. The continuous pressing count is calculated according to the first released signal and the first press signal that are continuously generated. Whether the continuous pressing count is greater than a first threshold is determined. If yes, a global peak searching method is applied to perform the AF procedure. If not, the local peak searching method is still applied to perform the AF procedure. | 01-30-2014 |
20150213589 | IMAGE CAPTURING DEVICE AND METHOD FOR CALIBRATING IMAGE DEFORMATION THEREOF - An image capturing device and a method for calibrating image deformation thereof are provided. The image capturing device has a first image sensor and a second image sensor and the method includes following steps. A plurality of image groups are captured through the first image sensor and the second image sensor. Each of the image groups includes a first image and a second image, and the image groups include a reference image group. Whether an image deformation occurs on a first reference image and a second reference image in the reference image group is detected. If it is detected that the image deformation occurs on the reference image group, a current calibration parameter is updated according to a plurality of feature point comparison values corresponding to the image groups. The current calibration parameter is used for performing an image rectification on each of the first images and the second images. | 07-30-2015 |
20150215607 | IMAGE CAPTURING DEVICE AND METHOD FOR CALIBRATING IMAGE DEFORMATION THEREOF - A method for calibrating image deformation of an image capturing device having a first and second lens, a focusing actuator, and a prestored first focusing step-to-focusing distance relation includes the following steps. A plurality of image sets are captured by the first and second lens, where each of the image sets includes a first and second image, and the images sets include a reference image set. It is detected whether the reference image set is deformed. When the reference image set is detected to be deformed, the first focusing step-to-focusing distance relation is calibrated according to a focusing step and a focusing distance corresponding to each of the image sets, where the focusing step corresponding to each of the image sets is the number of steps that the focusing actuator is required to move the first and second lens to a focusing position to generate each of the image sets. | 07-30-2015 |
20150215615 | IMAGE CAPTURING DEVICE AND METHOD FOR CALIBRATING IMAGE DEFECTION THEREOF - A method for calibrating image defection of an image capturing device having a first and second lens, a focusing actuator, and a prestored first focusing step-to-focusing distance relation includes the following steps. A plurality of image sets are captured by the first and second lens, where each of the image sets includes a first and second image, and the images sets include a reference image set. It is detected whether the reference image set is defective. When the reference image set is detected to be defective, the first focusing step-to-focusing distance relation is calibrated according to a focusing step and a focusing distance corresponding to each of the image sets, where the focusing step corresponding to each of the image sets is the number of steps that the focusing actuator is required to move the first and second lens to a focusing position to generate each of the image sets. | 07-30-2015 |
20150269732 | OBSTACLE DETECTION DEVICE - An obstacle detection device is provided, which includes a storage unit, a quasi-vertical edge detection module, an intersection determination module, a position determination module, and an obstacle detection module. The quasi-vertical edge detection module receives an input image and performs a quasi-vertical edge detection procedure on the input image to obtain a plurality of quasi-vertical edges. The intersection determination module determines whether the quasi-vertical edges intersect a predetermined virtual horizontal. If one of the quasi-vertical edges intersects the predetermined virtual horizontal, the position determination module determines whether an end of one of the quasi-vertical edges intersecting the predetermined virtual horizontal is located in a detection zone. If one end of one of the quasi-vertical edges intersecting the predetermined virtual horizontal is located in the detection zone, the obstacle detection module determines that an obstacle exists and issues a warning. | 09-24-2015 |
20150278633 | OBJECT DETECTION SYSTEM - An object detection system including a storage unit, image acquisition module, feature searching module, calculation module, and confirmation module is provided. The image acquisition module obtains a first, second, and third image respectively corresponding to a first, second, and third timepoint of a video sequence from the storage unit, where time difference between the first and second timepoint is less than or equal to that between the second and third timepoint. The feature searching module searches for at least one feature from the first image. When the feature is within a near-distance detected region, the calculation module calculates a motion vector of the feature according to the first and second image; otherwise, it calculates the motion vector of the feature according to the third and one of the first and second image. The confirmation module confirms the existence of a moving object according to the motion vector of the feature. | 10-01-2015 |
Ming-Jiun Liaw, Hsinchu TW
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20080224979 | METHOD FOR IMPROVING IMAGE QUALITY OF A DISPLAY DEVICE WITH LOW-TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR - The Low-Temperature Poly-Silicon thin film transistor display device of the invention arrayed with a plurality of gate lines and data lines and a switch unit and a pixel unit are located in the intersection of scan line and the data line. The device comprises a gate driven unit a data driven unit and a control unit wherein the gate driven unit provides a plurality of gate voltages to the gate lines to drive the switch unit, the data driven unit sends the corresponding video data to the gate lines, and the control unit controls the transmitting sequence of the video data to the data lines. The method of the invention includes the steps of: gate driven unit providing every N scanning signals to the scan lines and then the data driven unit switching the transmitting sequence of the video data. | 09-18-2008 |
Shien-Kuei Liaw, Taoyuan County TW
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20150188640 | COOLERLESS FIBER LIGHT SOURCE DEVICES FOR HARSH ENVIRONMENTS - A robust broadband ASE (amplified spontaneous emission) fiber light source device outputs a light beam which is little affected by temperature and radiation. The light source device is a single-pass backward or double-pass backward architecture, and has a coolerless pump laser and temperature compensated bandpass reflector. The light source device may have a high pass filtering element disposed between the wavelength division multiplexer thereof and the optical isolator thereof, so as to compensate the effect of the temperature to the mean wavelength of the light beam. The specific band of the temperature compensated bandpass reflector which reflects the light beam, and the band which the high pass filtering element transmits the light beam are within the band which the ASE unit amplifies the light beam, and the high pass filtering element mainly absorbs the light beam outside the specific band. | 07-02-2015 |
Shien-Kuei Liaw, Pingzhen City TW
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20120033688 | Single longitudinal mode fiber laser apparatus - The present invention provides a single frequency fiber laser apparatus. The fiber laser apparatus includes a Faraday rotator mirror. A piece of erbium doped fiber is inside the laser cavity. A wavelength selective coupler is connected to the erbium doped fiber. A pump source is coupled via the wavelength selective coupler. At least one sub-ring cavity component and/or an absorb component are inserted into the cavity for facilitating suppressing laser side modes to create a single longitudinal mode fiber laser. A partial reflectance fiber Bragg grating (FBG) is used as the front cavity end for this fiber laser. | 02-09-2012 |
20130149197 | Biotechnology Detecting Device with Optical Fibers and LEDs - A biotechnology detection device with optical fibers comprises a first optical fiber connected to a light source, and a prism having a first surface and a second surface. The first surface is connected to the first optical fiber and coated with an anti-reflective layer to be passed through by short-wavelength light; a second optical fiber connected to the second surface of the prism. The end of the second optical fiber is to be coated with test sample blended with a fluorescent agent, wherein the fluorescent agent emits long-wavelength light after being excited by short-wavelength light. The second prism surface is coated with a high reflective layer to reflect part of the long-wavelength light. A third optical fiber is connected to the second prism surface to convey part of the long-wavelength light. A detector is connected to the third optical fiber for detecting part of the long-wavelength light. | 06-13-2013 |
Shien-Kuei Liaw, Yangmei Township TW
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20080267226 | Broadband fiber laser - A broadband fiber laser provides a lasing cavity including a reflective mirror and at least one fiber Bragg grating for further providing a lasing signal to resonate and be amplified therein. Alternatively, the wavelength of the fiber laser can be either fixed or tunable by varying the central wavelength of the fiber Bragg grating and/or by adjusting the switching status of an optical switch pair. | 10-30-2008 |
20100008386 | Broadband fiber laser - A broadband fiber laser provides a lasing cavity including a reflective minor and at least one fiber Bragg grating for further providing a lasing signal to resonate and be amplified therein. Alternatively, the wavelength of the fiber laser can be either fixed or tunable by varying the central wavelength of the fiber Bragg grating and/or by adjusting the switching status of an optical switch pair. | 01-14-2010 |
20100132931 | THERMAL MODULE FOR LIGHT SOURCE - The present invention discloses a thermal module for light source, which comprises a heat-conducting part and a heat-dissipating part engaged therewith. The heat-conducting part is provided with a heat-receiving portion to receive the heat generated by a light source, a joint portion to join with the heat-dissipating part. The heat-dissipating part is provided with a plurality of fin-shaped heat-dissipating sheets for heat dissipation and to join with the joint portion of the heat-conducting part. | 06-03-2010 |
20100316372 | SIGNAL SWITCHING MODULE FOR OPTICAL NETWORK MONITORING AND FAULT LOCATING - The present invention provides an optical signal-selection switch module which is used in a method for simultaneous real-time status monitoring and troubleshooting of a high-capacity single-fiber hybrid passive optical network that is based on wavelength-division-multiplexing techniques. | 12-16-2010 |
20100316373 | BIDIRECTIONAL MULTI-WAVELENGTH OPTICAL SIGNAL ROUTING AND AMPLIFICATION MODULE - The present invention provides a bidirectional optical signal traffic-directing and amplification module which is used in a method for simultaneous real-time status monitoring and troubleshooting of a high-capacity single-fiber hybrid passive optical network that is based on wavelength-division-multiplexing techniques. | 12-16-2010 |
Shi-Mo Liaw, Kaohsiung City TW
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20080226426 | Punch/binding machine and binding module thereof - The present invention relates to a punch/binding machine and a binding module thereof. The punch/binding machine includes a transmission device, a body, and a binding module. The transmission device receives an external force. The body is used to support the transmission device. The binding module includes a fixing rod, a fixed comb plate, an upper board, a guide element, a moving seat, and a lower board. Two ends of the fixing rod are fixed on the body. The fixed comb plate has a plurality of fixing combs, and each of the fixing combs has a flute. The upper board has a plurality of slot apertures for the fixing combs to pass through. The guide element is located on one side of the upper board in order to push a plastic comb into the flutes of the fixing combs. The moving seat has a plurality of shifting rods for pulling the plastic comb. At least one end of the moving seat is connected to the transmission device, so as to be driven by the transmission device. The lower board is located below the moving seat for providing the moving seat to slide on the surface thereof. Thereby, the binding module is formed by stacking three plates, which has a small number of components and is easily assembled. | 09-18-2008 |
Shin-Chih Liaw, Tayuan TW
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20100059910 | APPARATUS FOR RECYCLING METAL FROM METAL IONS CONTAINING WASTE SOLUTION - An apparatus for recycling metals from metal ions containing waste solution includes a conveying device, a reducing agent supplier and a solution supplier. The conveying device includes a first ferromagnetic conveyor belt, a first roller, and a second roller. The first and second rollers are substantially horizontally arranged, and the second roller is arranged at a lower position relative to the first roller and spaced from the first roller. The ferromagnetic conveyor belt is wrapped around the first and second rollers. The reducing agent supplier is used for supplying a reducing agent onto the first conveyor belt, the ferromagnetic conveyor belt is capable of conveying the reducing agent from the second roller to the first roller. The solution supplier is configured for supplying the waste solution onto the first conveyor belt. | 03-11-2010 |
20100170639 | APPARATUS FOR WET PROCESSING SUBSTRATE - An exemplary apparatus for wet processing a substantially rectangular substrate includes a conveyor, a supporting mechanism, an adjusting mechanism, a processing module and a dosing system. The conveyor is configured for conveying the substrate to a wet process work station. The supporting mechanism is configured for supporting the substrate away from the conveyor. The adjusting mechanism is configured for adjusting the orientation of the substrate. The processing module is configured for obtaining an area of a surface of the substrate. The dosing system communicates with the processing unit, and is configured for dispensing a corresponding amount of wet processing liquid to the substrate to wet process the substrate according to the area of the surface of the substrate from the processing module. | 07-08-2010 |
Shi-Shen Liaw, Taipei City TW
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20100223839 | SYSTEMS AND PROCESSES FOR PRODUCING BIO-FUELS FROM LIGNOCELLULOSIC MATERIALS - A selective pyrolysis process for the production of bio-oils enriched in pyrolytic sugars and phenols and conversion of these compounds into second generation bio-fuels is disclosed herein. One embodiment of the process comprises pre-treating a biomass with superheated steam or gases in a selected range of temperatures, followed by fast pyrolysis using synthesis gas as a carrier, and a two-step condensation operation. The aqueous phase from the second condenser can then be reformed to produce hydrogen or can be gasified together with the charcoal to produce syngas. | 09-09-2010 |
Shu-Liang Liaw, Taoyuan County TW
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20120329168 | DRUG DETECTION METHOD AND APPARATUS - A drug detection apparatus for identifying whether a gas sample contains an acidic gas includes a reactor having a gas inlet, a detection reagent containing an oxidant and a reductant, and a catalyst triggering a chemical adsorption with the oxidant and the reductant. A drug detection method applied to a drug detection apparatus is also disclosed. The drug detection apparatus and method can detect the acidic gases from drugs immediately, sensitively and selectively, thereby improving the efficiency of suspect inspection of drug smuggling in airports. | 12-27-2012 |
Shu-Liang Liaw, Taipei City TW
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20130169949 | CHANGED OPTICAL PATH MEASURING DEVICE FOR COMPONENT CONCENTRATION OF WATER AND MEASURING METHOD THEREOF - Measuring device of the present invention includes a plurality of measuring sites for generating a plurality of optical paths and various dilutions. The range for concentration measurement and the measurement accuracy are enhanced due to the plurality of optical path length, and the interference on the measurement ranges and results caused by the concentration or the turbidity of suspended solid is reduced and removed by water sample dilution, and thus the characteristic wavelengths of the components in the water are measured. Next, the information of spectrum database is used to determine the ingredients which may exist in the water (qualitative analysis), and UV-VIS-NIR absorbance spectrum analysis is used to obtain the concentration of the respective ingredients in the water at the same time (quantitative analysis). | 07-04-2013 |
20150070702 | CHANGED OPTICAL PATH MEASURING DEVICE FOR COMPONENT CONCENTRATION OF WATER AND MEASURING METHOD THEREOF - Measuring device of the present invention includes a plurality of measuring sites for generating a plurality of optical paths and various dilutions. The range for concentration measurement and the measurement accuracy are enhanced due to the plurality of optical path length, and the interference on the measurement ranges and results caused by the concentration or the turbidity of suspended solid is reduced and removed by water sample dilution, and thus the characteristic wavelengths of the components in the water are measured. Next, the information of spectrum database is used to determine the ingredients which may exist in the water (qualitative analysis), and UV-VIS-NIR absorbance spectrum analysis is used to obtain the concentration of the respective ingredients in the water at the same time (quantitative analysis). | 03-12-2015 |
Tay-Jang Liaw, Yang-Mei TW
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20080291431 | APPARATUS FOR MONITORING OPTICAL OBSTRUCTIONS IN AN OPTICAL SPLIT NETWORK AND METHOD THEREOF - An apparatus and method for monitoring optical fiber obstructions in an optical split network is described. The monitoring apparatus comprises a broadband-monitoring light source module, an optical circulator, an optical spectral analyzer, a high-density multi-wavelength ODTR, a controlling computer, a wavelength division multiplexer, a specific wavelength optical filter, a monitoring-waveband reflector, and an optical channel selector. The monitoring apparatus utilizes the specific wavelength optical filter and the monitoring-waveband reflector to collectively construct an optical split network optical fiber obstruction monitoring apparatus for the passive optical network having multiple split routes by filtering, reflecting, and transmitting coming lights, so as to achieve the purposes of locating the obstructed split routes and obstruction locations at the same time. | 11-27-2008 |
Tin-Yu Liaw, Hsinchu County TW
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20140109671 | Apparatus of Digital Environment Monitor Having High-Pressure Chamber Easy in Maintenance - A digital apparatus is provided for monitoring environment. The apparatus has a high-pressure chamber easy in maintenance. By using a supporting unit, the chamber is stably set in a container. In addition, the supporting unit reduces problem of saturated-humidity absorption so that wastage of utilities and rate of fake signals are both decreased. Thus, the chamber is prevented from mist and vapor for keeping good function. | 04-24-2014 |
Tsung-Jen Liaw, New Taipei City TW
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20150260357 | COLOR-MIXING LIGHT-EMITTING DIODE MODULE - The present invention provides a color-mixing light-emitting diode module. According to the present invention, a first light-emitting chip and two second light-emitting chips are disposed on a holder. The first light-emitting chip emits red light and the plurality of second light-emitting chips emit white light. The red light and the white light are mixed, giving mixed light with high color rendering and brightness. Objects illuminated by the mixed light will exhibit colors closest to their original colors as perceived by eyes. Furthermore, by arranging the first and second light-emitting chips in matrix, the color rendering of the light-emitting diode module can be adjusted and improved. | 09-17-2015 |
Vincent Shuang-Pung Liaw, Taipei TW
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20140286480 | METHOD OF PROCESSING TELEPHONE VOICE OUTPUT, SOFTWARE PRODUCT PROCESSING TELEPHONE SOUND, AND ELECTRONIC DEVICE WITH TELEPHONE FUNCTION - A method of processing telephone voice output is applied in an electronic device with telephone function. When any one of the two communicators is a hearing-impaired user, at least one of the electronic devices will obtain the corresponding voice adjustment parameters according to the receiver identification of the hearing-impaired user. Therefore, the voice adjusting program is able to process the voice in advance based on the voice adjustment parameters to help the hearing-impaired user hear better. | 09-25-2014 |
20140358530 | METHOD OF PROCESSING A VOICE SEGMENT AND HEARING AID - A method of processing a voice segment includes checking whether a voice segment is a vowel segment. If the voice segment is not a vowel segment, then the process checks whether the voice segment is a high frequency consonant or a low frequency consonant. If the voice segment is a high frequency consonant, then the voice segment will be processed to lower its frequency. | 12-04-2014 |
20150049879 | METHOD OF AUDIO PROCESSING AND AUDIO-PLAYING DEVICE - A method of audio processing lowers the frequency of a high frequency audio area of an input audio in order to generate a lowered frequency audio area. The lowered frequency audio area is combined with the input audio to generate an output audio such that the output audio comprises the high frequency audio area, a low frequency audio area, and a lowered frequency audio area. | 02-19-2015 |
20150163600 | METHOD AND COMPUTER PROGRAM PRODUCT OF PROCESSING SOUND SEGMENT AND HEARING AID - A method of processing a sound segment is used in a hearing aid. If the sound segment is a high-frequency type, the high-frequency portion of the sound segment will be processed with a frequency lowering process. If the sound segment is a mixed-frequency type (between high-frequency and low-frequency), the energy of at least some portion of the high-frequency portion of the sound segment will be decreased and then processed with a frequency lowering process. | 06-11-2015 |
20150201057 | METHOD OF PROCESSING TELEPHONE VOICE OUTPUT AND EARPHONE - A method of processing telephone voice output is used in an earphone. This method includes obtaining a corresponding adjustment parameter according to the phone identification information of the hearing-impaired so as to make the processing module in the earphone process the voice according to the adjustment parameter in advance and enable the hearing-impaired to hear more clearly. | 07-16-2015 |
Yi-Ching Liaw, Changhua County TW
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20090172010 | DATA CLASSIFICATION SYSTEM AND METHOD FOR BUILDING CLASSIFICATION TREE FOR THE SAME - A data classification system is provided. The data classification system includes a fetch unit, a classification tree module, and a data repository. The fetch unit is adapted for receiving data including at least one datum, and fetching a data information contained in the data. The classification tree module is adapted for classifying the data in a manner of a tree structure according to the data information, and building a classification tree thereby. The data repository is adapted for storing the classification tree and the data. Therefore, the present invention provides a hierarchical structure which is adapted to accelerate a speed for searching data. | 07-02-2009 |
Yi-Ching Liaw, Chu-Tung TW
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20090269072 | METHODS FOR ALLOCATING TRANSMISSION BANDWIDTHS OF A NETWORK - Methods for allocating transmission bandwidths of a network are adapted to a network including an office terminal and peripheral terminals. The peripheral terminals communicate with the office terminal by time division multiplexing during a sequence of transmitting cycles. The method includes receiving requested bandwidths from uploading messages delivered from the peripheral terminals, arranging an uploading order of the peripheral terminals based on the uploading messages to obtain a transmitting sequence, adjusting the uploading order of each of the peripheral terminals in the transmitting sequence based on a size of the requested bandwidth to obtain a modified transmitting sequence, and arranging a modified uploading order of the peripheral terminals based on the modified transmitting sequence. Therefore, the transmission bandwidth allocation is fairer, and delay is reduced. Upstream order of each terminal is transferred based on its requested bandwidth, thereby effectively reducing the average delay. | 10-29-2009 |
Yuan Terng Liaw, Taichung TW
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20140117173 | Lock for musical instrument stand - A height adjustable stand for musical instrument includes a connecting housing including a sleeve secured to the stand, a bifurcation extending out of the sleeve and including a top opening communicating with a slot therein, and two limit surfaces on both sides of the opening respectively; two opposite hooks each pivotably secured to the bifurcation and including a coupling member including a spring receptacle, a lever, an inclined surface adjacent to the receptacle, and a latch, and a curved member extending from the coupling member; a torsion spring biased between the spring receptacles; and a lock pivotably supported in the opening and including a first part, a second part at an angle with respect to the first part, and a protrusion on a bottom of the first part. Pressing of the first part moves the protrusion out of the slot to unlock the hooks. | 05-01-2014 |
Yue-Gie Liaw, Miaoli County TW
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20140159047 | MANUFACTURING PROCESS OF OXIDE INSULATING LAYER AND FLEXIBLE STRUCTURE OF LTPS-TFT (LOW-TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR) DISPLAY - The present invention provides a manufacturing process of oxide insulating layer and flexible structure of LTPS-TFT display. The manufacturing process firstly provides a substrate, which is a soft material sheet; and then an a-Si layer is formed on the substrate, and oxygen ion implantation process of a certain depth is conducted onto the a-Si layer; finally, ELA process is conducted to transform a-Si layer into a Poly-Si layer and an oxide insulating layer; of which the oxide insulating layer is a silica insulating layer and located within the Poly-Si layer for subsequently producing LTPS-TFT; the structure comprises of a substrate, Poly-Si layer and oxide insulating layer within the Poly-Si layer. | 06-12-2014 |
Yuhhung Liaw, Taipei TW
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20140215480 | TASK SCHEDULING BASED ON THERMAL CONDITIONS OF LOCATIONS OF PROCESSORS - Provided is a computer system including a first processor disposed in a first zone, a second processor disposed in a second zone, a prioritizing unit, and a scheduling unit. The prioritizing unit prioritizes the first processor and the second processor based on the thermal conditions of the first zone and the second zone, respectively. The scheduling unit schedules a task to one of the first processor and the second processor according to the priority provided by the prioritizing unit. | 07-31-2014 |
20140298344 | TASK SCHEDULING BASED ON THERMAL CONDITIONS OF LOCATIONS OF PROCESSORS - A method of prioritizing processing units in a system for task scheduling includes, for each processing unit of a plurality of processing units in the system, determining a value that represents a thermal condition of a location of the processing unit. It is determined which of the plurality of processing units is not fully loaded and is in a location with a most favorable thermal condition based on the value of the processing unit that represents thermal conditions of the location of the processing unit. A task is scheduled to the processing unit determined to be not fully loaded and in a location with a most favorable thermal condition based on the value of the processing unit that represents thermal conditions of the location of the processing unit. | 10-02-2014 |
Yung-Haw Liaw, Hsin-Chu City TW
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20150191816 | METHOD FOR CONTROLLING EXHAUST FLOW IN WAFER PROCESSING MODULE - Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes placing the wafer into a processing assembly and heating the wafer. The method also includes producing an exhaust flow from the processing assembly via a fluid-conduit assembly. The method further includes detecting an exhaust pressure of the exhaust flow in the fluid-conduit assembly and producing a first signal and a second signal corresponding to the exhaust pressure. In addition, the method includes regulating the exhaust flow in response to the first signal and controlling the processing assembly in response to the second signal. | 07-09-2015 |