Patent application number | Description | Published |
20090087977 | LOW TEMPERATURE CONFORMAL OXIDE FORMATION AND APPLICATIONS - The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer. | 04-02-2009 |
20090140418 | METHOD FOR INTEGRATING POROUS LOW-K DIELECTRIC LAYERS - Described herein are methods for integrating low-k dielectric layers with various interconnect structures. In one embodiment, a method for restoring a porous dielectric layer includes forming an opening in the porous low-k dielectric layer. The method further includes forming an opening in a barrier layer. The method further includes depositing a restoring dielectric layer to seal a surface layer of pores of the porous dielectric layer. In one embodiment, the restoring dielectric layer is non-porous and hydrophobic to prevent the porous dielectric layer from adsorbing moisture and consequently increasing the dielectric constant of the porous dielectric layer. The method further includes performing a clean operation on the interconnect structure prior to metallization. The method further includes depositing, masking, and etching a metal layer. | 06-04-2009 |
20090263972 | BORON NITRIDE AND BORON-NITRIDE DERIVED MATERIALS DEPOSITION METHOD - A method and apparatus are provided to form spacer materials adjacent substrate structures. In one embodiment, a method is provided for processing a substrate including placing a substrate having a substrate structure adjacent a substrate surface in a deposition chamber, depositing a spacer layer on the substrate structure and substrate surface, and etching the spacer layer to expose the substrate structure and a portion of the substrate surface, wherein the spacer layer is disposed adjacent the substrate structure. The spacer layer may comprise a boron nitride material. The spacer layer may comprise a base spacer layer and a liner layer, and the spacer layer may be etched in a two-step etching process. | 10-22-2009 |
20090269923 | ADHESION AND ELECTROMIGRATION IMPROVEMENT BETWEEN DIELECTRIC AND CONDUCTIVE LAYERS - A method and apparatus for processing a substrate is provided. The method of processing a substrate includes providing a substrate comprising a conductive material, performing a pre-treatment process on the conductive material, flowing a silicon based compound on the conductive material to form a silicide layer, performing a post treatment process on the silicide layer, and depositing a barrier dielectric layer on the substrate. | 10-29-2009 |
20090317628 | METHODS AND APPARTUS TO PREVENT CONTAMINATION OF A PHOTORESIST LAYER ON A SUBSTRATE - In one aspect, a method is provided which includes ( | 12-24-2009 |
20090325381 | PREVENTION AND REDUCTION OF SOLVENT AND SOLUTION PENETRATION INTO POROUS DIELECTRICS USING A THIN BARRIER LAYER - A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch. | 12-31-2009 |
20100096687 | NON-VOLATILE MEMORY HAVING SILICON NITRIDE CHARGE TRAP LAYER - A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device. | 04-22-2010 |
20100096688 | NON-VOLATILE MEMORY HAVING CHARGE TRAP LAYER WITH COMPOSITIONAL GRADIENT - A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device. | 04-22-2010 |
20100098884 | BORON FILM INTERFACE ENGINEERING - Methods of depositing boron-containing liner layers on substrates involve the formation of a bilayer including an initiation layer which includes barrier material to inhibit the diffusion of boron from the bilayer into the underlying substrate. | 04-22-2010 |
20100099236 | GAPFILL IMPROVEMENT WITH LOW ETCH RATE DIELECTRIC LINERS - A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench. | 04-22-2010 |
20100099247 | FLASH MEMORY WITH TREATED CHARGE TRAP LAYER - A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device. | 04-22-2010 |
20100151671 | NOVEL AIR GAP INTEGRATION SCHEME - Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material. | 06-17-2010 |
20100233633 | ENGINEERING BORON-RICH FILMS FOR LITHOGRAPHIC MASK APPLICATIONS - Methods for processing a substrate with a boron rich film are provided. A patterned layer of boron rich material is deposited on a substrate and can be used as an etch stop. By varying the chemical composition, the selectivity and etch rate of the boron rich material can be optimized for different etch chemistries. The boron rich materials can be deposited over a layer stack substrate in multiple layers and etched in a pattern. The exposed layer stack can then be etched with multiple etch chemistries. Each of the boron rich layers can have a different chemical composition that is optimized for the multiple etch chemistries. | 09-16-2010 |
20110298099 | SILICON DIOXIDE LAYER DEPOSITED WITH BDEAS - A silicon dioxide layer is deposited onto a substrate using a process gas comprising BDEAS and an oxygen-containing gas such as ozone. The silicon dioxide layer can be part of an etch-resistant stack that includes a resist layer. In another version, the silicon dioxide layer is deposited into through holes to form an oxide liner for through-silicon vias. | 12-08-2011 |
20110315992 | PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION OF CRYSTALLINE GERMANIUM - In a method of depositing a crystalline germanium layer on a substrate, a substrate is placed in the process zone comprising a pair of process electrodes. In a deposition stage, a crystalline germanium layer is deposited on the substrate by introducing a deposition gas comprising a germanium-containing gas into the process zone, and forming a capacitively coupled plasma of the deposition gas by coupling energy to the process electrodes. In a subsequent treatment stage, the deposited crystalline germanium layer is treated by exposing the crystalline germanium layer to an energized treatment gas or by annealing the layer. | 12-29-2011 |
20120097330 | DUAL DELIVERY CHAMBER DESIGN - A substrate processing system includes a thermal processor or a plasma generator adjacent to a processing chamber. A first processing gas enters the thermal processor or plasma generator. The first processing gas then flows directly through a showerhead into the processing chamber. A second processing gas flows through a second flow path through the showerhead. The first and second processing gases are mixed below the showerhead and a layer of material is deposited on a substrate under the showerhead. | 04-26-2012 |
20120164827 | FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS - A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias. | 06-28-2012 |
20120164829 | FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS - A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. | 06-28-2012 |
20120196155 | RESIST FORTIFICATION FOR MAGNETIC MEDIA PATTERNING - A method and apparatus for forming magnetic media substrates is provided. A patterned resist layer is formed on a substrate having a magnetically susceptible layer. A conformal protective layer is formed over the patterned resist layer to prevent degradation of the pattern during subsequent processing. The substrate is subjected to an energy treatment wherein energetic species penetrate portions of the patterned resist and conformal protective layer according to the pattern formed in the patterned resist, impacting the magnetically susceptible layer and modifying a magnetic property thereof. The patterned resist and conformal protective layers are then removed, leaving a magnetic substrate having a pattern of magnetic properties with a topography that is substantially unchanged. | 08-02-2012 |
20120208366 | PREVENTION AND REDUCTION OF SOLVENT AND SOLUTION PENETRATION INTO POROUS DIELECTRICS USING A THIN BARRIER LAYER - A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch. | 08-16-2012 |
20120248617 | MULTILAYERED LOW k CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES - The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride. | 10-04-2012 |
20120289049 | COPPER OXIDE REMOVAL TECHNIQUES - A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H | 11-15-2012 |
20130005146 | MULTILAYERED LOW k CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES - The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride. | 01-03-2013 |
20130130405 | APPARATUS AND METHODS FOR SILICON OXIDE CVD RESIST PLANARIZATION - Embodiments of the present invention provide methods and apparatus for forming a patterned magnetic layer for use in magnetic media. According to embodiments of the present application, a silicon oxide layer formed by low temperature chemical vapor deposition is used to form a pattern in a hard mask layer, and the patterned hard mask is used to form a patterned magnetic layer by plasma ion implantation. | 05-23-2013 |
20130183835 | LOW TEMPERATURE PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION OF CONFORMAL SILICON CARBON NITRIDE AND SILICON NITRIDE FILMS - Methods and apparatus for forming conformal silicon nitride films at low temperatures on a substrate are provided. The methods of forming a silicon nitride layer include performing a deposition cycle including flowing a processing gas mixture into a processing chamber having a substrate therein, wherein the processing gas mixture comprises precursor gas molecules having labile silicon to nitrogen, silicon to carbon, or nitrogen to carbon bonds, activating the precursor gas at a temperature between about 20° C. to about 480° C. by preferentially breaking labile bonds to provide one or more reaction sites along a precursor gas molecule, forming a precursor material layer on the substrate, wherein the activated precursor gas molecules bond with a surface on the substrate at the one or more reaction sites, and performing a plasma treatment process on the precursor material layer to form a conformal silicon nitride layer. | 07-18-2013 |
20130189841 | ENGINEERING DIELECTRIC FILMS FOR CMP STOP - A method for forming an integrated circuit is provided. In one embodiment, the method includes forming a stop layer comprising carbon doped silicon nitride on a gate region on a substrate, the gate region having a poly gate and one or more spacers formed adjacent the poly gate, forming a dielectric layer on the stop layer, and removing a portion of the dielectric layer above the gate region using a CMP process, wherein the stop layer is a strain inducing layer having a CMP removal rate that is less than the CMP removal rate of the dielectric layer and equal to or less than the CMP removal rate of the one or more spacers. | 07-25-2013 |
20130192524 | Continuous Substrate Processing System - A processing chamber having a plurality of movable substrate carriers stacked therein for continuously processing a plurality of substrates is provided. The movable substrate carrier is capable of being transported from outside of the processing chamber, e.g., being transferred from a load luck chamber, into the processing chamber and out of the processing chamber, e.g., being transferred into another load luck chamber. Process gases delivered into the processing chamber are spatially separated into a plurality of processing slots, and/or temporally controlled. The processing chamber can be part of a multi-chamber substrate processing system. | 08-01-2013 |
20130192761 | Rotary Substrate Processing System - A substrate processing system for processing multiple substrates is provided and generally includes at least one processing platform and at least one staging platform. Each substrate is positioned on a substrate carrier disposed on a substrate support assembly. Multiple substrate carriers, each is configured to carry a substrate thereon, are positioned on the surface of the substrate support assembly. The processing platform and the staging platform, each includes a separate substrate support assembly, which can be rotated by a separate rotary track mechanism. Each rotary track mechanism is capable of supporting the substrate support assembly and continuously rotating multiple substrates carried by the substrate carriers and disposed on the substrate support assembly. Each substrate is thus processed through at least one shower head station and at least one buffer station, which are positioned at a distance above the rotary track mechanism of the processing platform. Each substrate can be transferred between the processing platform and the staging platform and in and out the substrate processing system. | 08-01-2013 |
20130196078 | Multi-Chamber Substrate Processing System - A substrate processing system for processing multiple substrates is provided and generally includes at least one substrate processing platform and at least one substrate staging platform. The substrate processing platform includes a rotary track system capable of supporting multiple substrate support assemblies and continuously rotating the substrate support assemblies, each carrying a substrate thereon. Each substrate is positioned on a substrates support assembly disposed on the rotary track system and being processed through at least one shower head station and at least one buffer station, which are positioned atop the rotary track system of the substrate processing platform. Multiple substrates disposed on the substrate support assemblies are processed in and out the substrate processing platform. The substrate staging platform includes at least one dual-substrate processing station, each dual-substrate processing station includes two substrate support assemblies for supporting two substrates thereon. | 08-01-2013 |
20130230986 | ADHESION IMPROVEMENT FOR LOW K DIELECTRICS TO CONDUCTIVE MATERIALS - Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed thereon, introducing a reducing compound or a silicon based compound, exposing the conductive material to the reducing compound or the silicon based compound, and depositing a silicon carbide layer without breaking vacuum. | 09-05-2013 |
20130333923 | MODULATED COMPOSITIONAL AND STRESS CONTROLLED MULTILAYER ULTRATHIN CONFORMAL SiNx DIELECTRICS USED IN NANO DEVICE FABRICATION - A layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers is deposited on a substrate. A plasma nitridation process is carried out on the layer. These steps are repeated for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained. Such steps can be used to provide a multilayer silicon nitride dielectric formed on a substrate having an upper surface of dielectric material with Cu and other conductors embedded within, and a plurality of steps. The multilayer silicon nitride dielectric has a plurality of individual layers each having a thickness from 0.5 nanometers to 2.4 nanometers, and the multilayer silicon nitride dielectric conformally covers the steps of the substrate with a conformality of at least seventy percent. A multilayer silicon nitride dielectric, and a multilevel back end of line interconnect wiring structure using same, are also provided. | 12-19-2013 |
20140023794 | Method And Apparatus For Low Temperature ALD Deposition - Provided are methods and apparatus for low temperature atomic layer deposition of a densified film. A low temperature film is formed and densified by exposure to one or more of a plasma or radical species. The resulting densified film has superior properties to low temperature films formed without densification. | 01-23-2014 |
20140147700 | RESIST FORTIFICATION FOR MAGNETIC MEDIA PATTERNING - A method and apparatus for forming magnetic media substrates is provided. A patterned resist layer is formed on a substrate having a magnetically susceptible layer. A conformal protective layer is formed over the patterned resist layer to prevent degradation of the pattern during subsequent processing. The substrate is subjected to an energy treatment wherein energetic species penetrate portions of the patterned resist and conformal protective layer according to the pattern formed in the patterned resist, impacting the magnetically susceptible layer and modifying a magnetic property thereof. The patterned resist and conformal protective layers are then removed, leaving a magnetic substrate having a pattern of magnetic properties with a topography that is substantially unchanged. | 05-29-2014 |
20140273438 | CU/BARRIER INTERFACE ENHANCEMENT - Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer. | 09-18-2014 |
20140273516 | VBD AND TDDB IMPROVEMENT THRU INTERFACE ENGINEERING - Methods for the repair of damaged low k films are provided. In one embodiment, the method comprises providing a substrate having a low k dielectric film deposited thereon, and exposing a surface of the low k dielectric film to an activated carbon-containing precursor gas to form a conformal carbon-containing film on the surface of the low k dielectric film, wherein the carbon-containing precursor gas has at least one or more Si—N—Si linkages in the molecular structure. | 09-18-2014 |
20140273524 | Plasma Doping Of Silicon-Containing Films - Provided are methods for the deposition and doping of films comprising Si. Certain methods involve depositing a SiN, SiO, SiON, SiC or SiCN film and doping the Si-containing film with one or more of C, B, O, N and Ge by a plasma implantation process. Such doped Si-containing films may have improved properties such as reduced etch rate in acid-based clean solutions, reduced dielectric constant and/or improved dielectric strength. | 09-18-2014 |
20140273529 | PEALD of Films Comprising Silicon Nitride - Provided are methods of for deposition of SiN films via PEALD processes. Certain methods pertain to exposing a substrate surface to a silicon precursor to provide a silicon precursor at the substrate surface; purging excess silicon precursor; exposing the substrate surface to an ionized reducing agent; and purging excess ionized reducing agent to provide a film comprising SiN, wherein the substrate has a temperature of 23° C. to about 550° C. | 09-18-2014 |
20140273530 | Post-Deposition Treatment Methods For Silicon Nitride - Provided are methods post deposition treatment of films comprising SiN. Certain methods pertain to providing a film comprising SiN; and exposing the film to an inductively coupled plasma, capacitively coupled plasma or a microwave plasma to provide a treated film with a modulated film stress and/or wet etch rate in dilute HF. Certain other methods comprise depositing a PEALD SiN film followed by exposure to a plasma nitridation process or a UV treatment to provide a treated film. | 09-18-2014 |
20140349480 | COBALT SELECTIVITY IMPROVEMENT IN SELECTIVE COBALT PROCESS SEQUENCE - Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. Embodiments described herein control selectivity of deposition by preventing damage to the dielectric surface, repairing damage to the dielectric surface, such as damage which can occur during the cobalt deposition process, and controlling deposition parameters for the cobalt layer. | 11-27-2014 |