| Patent application number | Description | Published |
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| 20090112960 | System and Method for Providing a Double Adder for Decimal Floating Point Operations - A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The sums of the corresponding digits and the carry out indicators in a carry chain are stored in an intermediate result register. Each of the sums in the intermediate result register is incremented by one. A selection between each of the sums and the sums incremented by one is performed. Input to the selecting includes the carry chain, and the output from the selecting includes a final sum of the first operand and the second operand. The final sum is stored in an output register. | 04-30-2009 |
| 20090132627 | Method for Performing Decimal Floating Point Addition - A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second register. An operation, either addition or subtraction, associated with the first operand and the second operand is received. Three concurrent calculations are performed on the first operand and the second operand. The three concurrent calculations include: applying the operation to the first operand and the second operand based on a first assumption; applying the operation to the first operand and the second operand based on a second assumption; and applying the operation to the first operand and the second operand based on a third assumption. A final result is selected from the first result, the second result and the third result. | 05-21-2009 |
| 20090132628 | Method for Performing Decimal Division - A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers. | 05-21-2009 |
| 20090132629 | Method for Providing a Decimal Multiply Algorithm Using a Double Adder - A method for performing decimal multiplication including storing a multiplier and a multiplicand in operand registers, the multiplier including one or more digits. A running sum is stored in a shifter and initialized to zero. The method includes performing for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand and adding the partial product to the running sum. The running sum is output as the result of multiplying the multiplier and the multiplicand. The performing and outputting are implemented by a mechanism that includes one or more two cycle adders connected to the operand registers, multiplicand multiples circuitry connected to the operand registers, and a result digits register connected to the two cycle adders. | 05-21-2009 |
| 20090210659 | PROCESSOR AND METHOD FOR WORKAROUND TRIGGER ACTIVATED EXCEPTIONS - A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw. | 08-20-2009 |
| 20090240753 | METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS - A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format. | 09-24-2009 |
| Patent application number | Description | Published |
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| 20080233514 | POSITIVE PHOTORESIST COMPOSITION WITH A POLYMER INCLUDING A FLUOROSULFONAMIDE GROUP AND PROCESS FOR ITS USE - A positive photoresist composition comprises a radiation sensitive acid generator, and a polymer that includes a first repeating unit derived from a sulfonamide monomer including a fluorosulfonamide functionality, a second repeating unit having a pendant acid-labile moiety, and a third repeating unit having a lactone functionality. The positive photoresist composition may be used to form patterned features on a substrate, such as those used in the manufacture of a semiconductor device. | 09-25-2008 |
| 20080286686 | FLUORINATED HALF ESTER OF MALEIC ANHYDRIDE POLYMERS FOR DRY 193 NM TOP ANTIREFLECTIVE COATING APPLICATION - The present invention discloses a composition suitable for use as a top antireflective coating and barrier layer for 193 nm lithography. The inventive composition is soluble in aqueous base solutions and has low refractive index at 193 nm. The inventive composition comprises an aqueous base-soluble polymer having a backbone and a fluorinated half ester moiety. The fluorinated half ester moiety is pendant from the backbone. The present invention also discloses a method of forming a patterned layer on a substrate by using the inventive composition in lithography. | 11-20-2008 |
| 20090181319 | AROMATIC FLUORINE-FREE PHOTOACID GENERATORS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Fluorine-free photoacid generators and photoresist compositions containing fluorine-free photoacid generators are enabled as alternatives to PFOS/PFAS photoacid generator-containing photoresists. The photoacid generators are characterized by the presence of a fluorine-free aromatic sulfonate anionic component having one or more electron withdrawing groups. The photoacid generators preferably contain a fluorine-free onium cationic component, more preferably a sulfonium cationic component. The photoresist compositions preferably contain an acid sensitive imaging polymer having a lactone functionality. The compositions are especially useful for forming material patterns using 193 nm (ArF) imaging radiation. | 07-16-2009 |
| 20090291392 | WET DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITION AND METHOD FOR USE THEREOF - The present invention discloses an antireflective coating composition for applying between a substrate surface and a positive photoresist composition. The antireflective coating composition is developable in an aqueous alkaline developer. The antireflective coating composition comprises a polymer, which comprises at least one monomer unit containing one or more moieties selected from the group consisting of a lactone, maleimide, and an N-alkyl maleimide; and at least one monomer unit containing one or more absorbing moieties. The polymer does not comprise an acid labile group. The present invention also discloses a method of forming and transferring a relief image by using the inventive antireflective coating composition in photolithography. | 11-26-2009 |
| 20100297557 | Coating compositions suitable for use with an overcoated photoresist - Organic coating compositions, particularly antireflective coating compositions, are provided that can be developed with an aqueous alkaline developer, including in a single step during development of an overcoated photoresist layer. Preferred coating compositions comprise a tetrapolymer that comprises at least four distinct functional groups. | 11-25-2010 |
