Patent application number | Description | Published |
20100078416 | METHOD OF LASER MICRO-MACHINING STAINLESS STEEL WITH HIGH COSMETIC QUALITY - A process to laser micro-machine a metal part with a high cosmetic quality surface, including applying a protective coating layer to at least one surface of the part to physically isolate the surface from air prior to micro-machining the part with a laser, and sacrificing the protective layer to block/consume oxygen in air by carbonization and oxidation due to strong laser irradiation. The protective coating applied to at least one of a front side high quality cosmetic surface and a back side surface of the part. The coating layer being highly transparent to an applied laser beam, having a thickness of between approximately 5 mil and approximately 10 mil, inclusive, and having sufficient adhesion strength to adhere to the part without delaminating during processing. The laser can be selected from a nano-second pulse width laser and a micro-second pulse width laser to process the part. | 04-01-2010 |
20100078418 | METHOD OF LASER MICRO-MACHINING STAINLESS STEEL WITH HIGH COSMETIC QUALITY - A process to laser micro-machine a metal part with a high cosmetic quality surface includes applying a protective coating layer to at least one surface of the part before micro-machining the part with a laser. The protective coating applied to the high quality cosmetic surface can have a thickness of between about 5 mil and about 10 mil, inclusive and have sufficient adhesion strength to adhere to the part without delaminating during processing. The protective coating applied to the machining surface of the part can be a metallic material, such as a metallic foil or tape. | 04-01-2010 |
20100147813 | METHOD FOR LASER PROCESSING GLASS WITH A CHAMFERED EDGE - A laser machining process is described for laser machining glass or glass-like materials. This process machines articles or features in articles with chamfered edges in one manufacturing operation. Chamfered edges are desirable in glass and glass-like materials because they resist fracturing or chipping and eliminate sharp edges. Producing articles or features in articles in one manufacturing operation is desirable because it can save time and expense by eliminating the need to transfer the article to a separate machine for chamfering after laser machining. Alternatively, it can permit use of less expensive equipment because the same laser used for machining can be used to form the chamfer instead of having a separate process perform the chamfering. Producing chamfers with laser machining results in high quality chamfers without the need for a separate polishing or finishing step. | 06-17-2010 |
20100252540 | METHOD AND APPARATUS FOR BRITTLE MATERIALS PROCESSING - An improved method for laser machining features in brittle materials | 10-07-2010 |
20100252959 | METHOD FOR IMPROVED BRITTLE MATERIALS PROCESSING - An improved method for laser machining features in brittle materials such as glass is presented, wherein a tool path related to a feature is analyzed to determine how many passes are required to laser machine the feature using non-adjacent laser pulses. Laser pulses applied during subsequent passes are located so as to overlap previous laser spot locations by a predetermined overlap amount. In this way no single spot receives excessive laser radiation caused by immediately subsequent laser pulses being applied adjacent to a previous pulse location. | 10-07-2010 |
20120152918 | REDUCING BACK-REFLECTION IN LASER MICROMACHINING SYSTEMS - Systems and methods reduce or prevent back-reflections in a laser processing system. A system includes a laser source to generate an incident laser beam, a laser beam output to direct the incident laser beam toward a work surface along a beam path, and a spatial filter. The system further includes a beam expander to expand a diameter of the incident laser beam received through the spatial filter, and a scan lens to focus the expanded incident laser beam at a target location on a work surface. A reflected laser beam from the work surface returns through the scan lens to the beam expander, which reduces a diameter of the reflected beam and increases a divergence angle of the reflected laser beam. The spatial filter blocks a portion of the diverging reflected laser beam from passing through the aperture and returning to the laser beam output. | 06-21-2012 |
20120248075 | LASER DIRECT ABLATION WITH PICOSECOND LASER PULSES AT HIGH PULSE REPETITION FREQUENCIES - Laser direct ablation (LDA) produces patterns cut into a dielectric layer for the formation of electrically conductive traces with controlled signal propagation characteristics. LDA processing includes selecting a dose fluence for removing a desired depth of material along a scribe line on a surface of a workpiece, selecting a temporal pulsewidth for each laser pulse in a series of laser pulses, and selecting a pulse repetition frequency for the series of laser pulse. The pulse repetition frequency is based at least in part on the selected temporal pulsewidth to maintain the selected dose fluence along the scribe line. The selected pulse repetition frequency provides a predetermined minimum overlap of laser spots along the scribe line. The LDA process further includes generating a laser beam including the series of laser pulses according to the selected dose fluence, temporal pulsewidth, and pulse repetition frequency. | 10-04-2012 |
Patent application number | Description | Published |
20080218413 | MILLIMETER-WAVE COMMUNICATION STATIONS WITH DIRECTIONAL ANTENNAS AND METHODS FOR FAST LINK RECOVERY - Embodiments of millimeter-wave communication stations with directional antennas and methods for fast link recovery are generally described herein. Other embodiments may be described and claimed. In some embodiments, a transmitting station retransmits a packet in an adjacent direction when an acknowledgement is not received from a receiving station after a number of retransmission attempts. In other embodiments, a receiving station changes its reception to an adjacent direction when a packet is not received from a transmitting station after a number of missed reservations. | 09-11-2008 |
20090232116 | MECHANISM TO AVOID INTERFERENCE AND IMPROVE CHANNEL EFFICIENCY IN MMWAVE WPANS - Briefly, a mechanism to avoid interference and improve channel efficiency in mmWave Wireless Personal Area Networks (WPANs) is disclosed. According to an embodiment of the present invention, neighbor devices can identify whether a certain high rate channel is being used or not through a communication on another channel, and thus avoidance actions may be taken by neighbor devices even if they do not receive signals from the high rate channel. | 09-17-2009 |
20090233554 | Mitigation of internetwork interference - When a device in one wireless network receives interfering transmissions from an overlapping neighboring network, the neighboring network may be notified of the interference so that non-interfering schedules can be worked out. In one embodiment, the device receiving the interference may broadcast its own communications schedule. Device(s) in the interfering network may pick up that schedule, and pass it on to their controller, which can rearrange its own network schedule to be non-interfering. In another embodiment, the device receiving the interference may notify its own network controller with the pertinent information, and that controller may contact the controller of the interfering network to coordinate non-interfering schedules. | 09-17-2009 |
20090233635 | Discovering neighbors in wireless personal area networks - A neighbor discovery protocol enables a network coordinator to provide time periods during which different classes of devices produce training sequences. The coordinator can transmit information about these time periods in a plurality of different directions so that in-range devices with directional antenna systems receive the communication. The coordinator can also compile interference reports during the neighbor discovery period and thereafter. These reports may be useful in determining whether or not spatial reuse is appropriate between two particular nodes in a given link, in a particular direction. | 09-17-2009 |
20100157952 | Dynamic CTA adjustment across superframes in a wireless network - In a wireless communications network, various embodiments of the invention provide a technique for requesting an extension or truncation of the previously assigned channel time allocation (CTA), and extending that extension or truncation across multiple superframes without having to make further requests. The request may be made by transmitting an Information Element (IE) that indicates how many superframes the request applies to. | 06-24-2010 |
20100321402 | DISPLAY UPDATE FOR A WIRELESS DISPLAY DEVICE - Embodiments of partial update for a wireless display device include providing an update information message identifying a location of the partial update and the changed image data. A display source identifies changes in image data stored in a frame buffer, generates an update information message to identify the location of the changed image data and to provide the changed image data. A display sink receives the update information message and merges the changed image data with image data stored in a local frame buffer. | 12-23-2010 |
20130017849 | MITIGATION OF INTERNETWORK INTERFERENCE - When a device in one wireless network receives interfering transmissions from an overlapping neighboring network, the neighboring network may be notified of the interference so that non-interfering schedules can be worked out. In one embodiment, the device receiving, the interference may broadcast its own communications schedule. Device(s) in the interfering network may pick up that schedule, and pass it on to their controller, which can rearrange its own network schedule to be non-interfering. In another embodiment, the device receiving the interference may notify its own network controller with the pertinent information, and that controller may contact the controller of the interfering network to coordinate non-interfering schedules. | 01-17-2013 |
20130179929 | WIRELESS VIDEO CLOCK SYNCHRONIZATION TO ENABLE POWER SAVING - In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained. | 07-11-2013 |
20130314386 | DISPLAY UPDATE FOR A WIRELESS DISPLAY DEVICE - Embodiments of partial update for a wireless display device include providing an update information message identifying a location of the partial update and the changed image data. A display source identifies changes in image data stored in a frame buffer, generates an update information message to identify the location of the changed image data and to provide the changed image data. A display sink receives the update information message and merges the changed image data with image data stored in a local frame buffer. | 11-28-2013 |
20150023306 | MECHANISM TO AVOID INTERFERENCE AND IMPROVE CHANNEL EFFICIENCY IN MMWAVE WPANS - Briefly, a mechanism to avoid interference and improve channel efficiency in mmWave Wireless Personal Area Networks (WPANs) is disclosed. According to an embodiment of the present invention, neighbor devices can identify whether a certain high rate channel is being used or not through a communication on another channel, and thus avoidance actions may be taken by neighbor devices even if they do not receive signals from the high rate channel. | 01-22-2015 |
20150139119 | MASTER STATION AND METHOD FOR HEW COMMUNICATION USING A TRANSMISSION SIGNALING STRUCTURE FOR A HEW SIGNAL FIELD - Embodiments of a transmission signaling structure for HEW are defined to carry packet information to configure OFDMA receivers for demodulation of a specific portion of the packet and/or to configure receivers for transmission using specific OFDMA and MU-MIMO resources. In some embodiments, the specific portion of the packet comprises one or more minimum bandwidth units of one or more 20 MHz channels. Each 20 MHz bandwidth structure may comprise several minimum bandwidth units to allow each 20 MHz channel to have a have smaller granularity than 20 MHz. | 05-21-2015 |
20150327121 | METHOD, APPARATUS, AND COMPUTER READABLE MEDIA FOR ACKNOWLEDGEMENT IN WIRELESS NETWORKS - Embodiments of a system and method for communicating acknowledgments in a wireless network are generally described herein. In some embodiments, a method of wirelessly communicating acknowledgements includes receiving a first signal on a first subchannel from a second wireless device. The method may include transmitting a block acknowledgement of the first signal on a subchannel. The first wireless communication device may not receive a block acknowledgement request to transmit the block acknowledgement. In some embodiments, a method of communicating block acknowledgements includes transmitting a first transmission to a first wireless device on a first subchannel and a second transmission to a second wireless device on a second subchannel. The method may include receiving a first block acknowledgement from the first wireless device and a second block acknowledgement from second wireless device. The first and second block acknowledgement may be received on one of the first and second subchannels. | 11-12-2015 |
Patent application number | Description | Published |
20080270786 | APPARATUS AND METHOD FOR DIRECT ANONYMOUS ATTESTATION FROM BILINEAR MAPS - A method and apparatus for direct anonymous attestation from bilinear maps. In one embodiment, the method includes the creation of a public/private key pair for a trusted membership group defined by an issuer; and assigning a unique secret signature key to at least one member device of the trusted membership group defined by the issuer. In one embodiment, using the assigned signature key, a member may assign a message received as an authentication request to prove membership within a trusted membership group. In one embodiment, a group digital signature of the member is verified using a public key of the trusted membership group. Accordingly, a verifier of the digital signature is able to authenticate that the member is an actual member of the trusted membership group without requiring of the disclosure of a unique identification information of the member or a private member key to maintain anonymity of trusted member devices. Other embodiments are described and claimed. | 10-30-2008 |
20080270790 | APPARATUS AND METHOD FOR ENHANCED REVOCATION OF DIRECT PROOF AND DIRECT ANONYMOUS ATTESTATION - In some embodiments, a method and apparatus for enhanced revocation of direct proof and direct anonymous attestation are described. In one embodiment a trusted hardware device verifies that membership of the device within a trusted membership group is not revoked according to a revocation list received with a challenge request from a verifier. Once such verification is performed, the device convinces the verifier of possessing cryptographic information without revealing unique, device identification information of the trusted hardware device or the cryptographic information. In one embodiment, the trusted hardware device computes a digital signature on a message received with the challenge request to the verifier if membership of the anonymous hardware device within a trusted membership group is verified. In one embodiment, the verifier authenticates the digital signature according to a public key of the trusted membership group to enable a trusted member device to remain anonymous to the verifier. Other embodiments are described and claimed. | 10-30-2008 |
20080307223 | APPARATUS AND METHOD FOR ISSUER BASED REVOCATION OF DIRECT PROOF AND DIRECT ANONYMOUS ATTESTATION - In some embodiments, a method and apparatus for issuer based revocation of direct proof and direct anonymous attestation are described. In one embodiment, a trusted hardware device convinces a verifier that the trusted hardware device possesses cryptographic information without revealing unique, device identification information of the trusted hardware device or the cryptographic information. Once the verifier is convinced that the hardware device possesses the cryptographic information, the verifier may issue a denial of revocation request to the trusted hardware device, including a base value B | 12-11-2008 |
20100082973 | Direct anonymous attestation scheme with outsourcing capability - A Direct Anonymous Attestation (DAA) scheme using elliptic curve cryptography (ECC) and bilinear maps. A trusted platform module (TPM) may maintain privacy of a portion of a private membership key from an issuer while joining a group. Moreover, the TPM can outsource most of the computation involved in generating a signature to a host computer. | 04-01-2010 |
20100169650 | STORAGE MINIMIZATION TECHNIQUE FOR DIRECT ANONYMOUS ATTESTATION KEYS - A storage minimization technique for direct anonymous attestation (DAA) keys is presented. In one embodiment, the method includes deriving a random portion of a (DAA) private key from a device's fuse key, computing a point on an elliptical curve from the derived random portion and a master private key, and storing only one coordinate of the point in fuses within the device. Other embodiments are described and claimed. | 07-01-2010 |
20120023334 | METHODS FOR ANONYMOUS AUTHENTICATION AND KEY AGREEMENT - Methods for anonymous authentication and key exchange are presented. In one embodiment, a method includes initiating a two-way mutual authentication between a device and a remote entity. The device remains anonymous to the remote entity after performing the authentication. The method also includes establishing a mutually shared session key for use in secure communication, wherein the initiating and the establishing are in conjunction with direct anonymous attestation (DAA). | 01-26-2012 |
20120137137 | METHOD AND APPARATUS FOR KEY PROVISIONING OF HARDWARE DEVICES - Keying materials used for providing security in a platform are securely provisioned both online and offline to devices in a remote platform. The secure provisioning of the keying materials is based on a revision of firmware installed in the platform. | 05-31-2012 |
20120159155 | Direct Anonymous Attestation Scheme with Outsourcing Capability - A Direct Anonymous Attestation (DAA) scheme using elliptic curve cryptography (ECC) and bilinear maps. A trusted platform module (TPM) may maintain privacy of a portion of a private membership key from an issuer while joining a group. Moreover, the TPM can outsource most of the computation involved in generating a signature to a host computer. | 06-21-2012 |
20120284518 | METHOD OF ANONYMOUS ENTITY AUTHENTICATION USING GROUP-BASED ANONYMOUS SIGNATURES - Methods for anonymous authentication and key exchange are presented. In one embodiment, a method includes initiating a two-way mutual authentication between a first entity and a second entity. The first entity remains anonymous to the second entity after performing the authentication. The method also includes establishing a mutually shared session key for use in secure communication between the entities, wherein the initiating and the establishing are in conjunction with direct anonymous attestation (DAA). | 11-08-2012 |
20130080771 | APPARATUS AND METHOD FOR DIRECT ANONYMOUS ATTESTATION FROM BILINEAR MAPS - A method and apparatus for direct anonymous attestation from bilinear maps. In one embodiment, the method includes the creation of a public/private key pair for a trusted membership group defined by an issuer; and assigning a unique secret signature key to at least one member device of the trusted membership group defined by the issuer. In one embodiment, using the assigned signature key, a member may assign a message received as an authentication request to prove membership within a trusted membership group. In one embodiment, a group digital signature of the member is verified using a public key of the trusted membership group. Accordingly, a verifier of the digital signature is able to authenticate that the member is an actual member of the trusted membership group without requiring of the disclosure of a unique identification information of the member or a private member key to maintain anonymity of trusted member devices. Other embodiments are described and claimed. | 03-28-2013 |
20130147511 | Offline Device Authentication and Anti-Counterfeiting Using Physically Unclonable Functions - The output of a physically unclonable function (PUF) may be processed to reduce its size. The post-processing result is served as a device intrinsic unclonable identifier and is signed by the device manufacturer to create a certificate stored on board the same device that includes the physically unclonable function. This scheme may not require online verification and complex error correction on PUFs in some cases. | 06-13-2013 |
20140082362 | METHOD OF ANONYMOUS ENTITY AUTHENTICATION USING GROUP-BASED ANONYMOUS SIGNATURES - Methods for anonymous authentication and key exchange are presented. In one embodiment, a method includes initiating a two-way mutual authentication between a first entity and a second entity. The first entity remains anonymous to the second entity after performing the authentication. The method also includes establishing a mutually shared session key for use in secure communication between the entities, wherein the initiating and the establishing are in conjunction with direct anonymous attestation (DAA). | 03-20-2014 |
20140089659 | Method and apparatus for key provisioning of hardware devices - Keying materials used for providing security in a platform are securely provisioned both online and offline to devices in a remote platform. The secure provisioning of the keying materials is based on a revision of firmware installed in the platform. | 03-27-2014 |
20140091832 | INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS - An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed. | 04-03-2014 |
20140095883 | HARDENING OF DIRECT ANONYMOUS ATTESTATION FROM SIDE-CHANNEL ATTACK - Various embodiments are generally directed to hardening the performance of calculations of a digital signature system for authenticating computing devices against side-channel attacks. An apparatus comprises a processor circuit and an interface operative to communicatively couple the processor circuit to a network; a storage communicatively coupled to the processor circuit and arranged to store instructions operative on the processor circuit to digitally sign a message to create a first signature using a modular arithmetic operation arranged to compensate for a value of a variable greater than a modulus without use of a branching instruction; and transmit the first signature to a verifying server via the network. Other embodiments are described and claimed herein. | 04-03-2014 |
20140185795 | FUSE ATTESTATION TO SECURE THE PROVISIONING OF SECRET KEYS DURING INTEGRATED CIRCUIT MANUFACTURING - Embodiments of an invention for fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing are disclosed. In one embodiment, an apparatus includes a storage location, a physically unclonable function (PUF) circuit, a PUF key generator, an encryption unit, and a plurality of fuses. The storage location is to store a configuration fuse value. The PUF circuit is to provide a PUF value. The PUF key generator is to generate a PUF key based on the PUF value. The encryption unit is to encrypt the configuration fuse value using the PUF key. The PUF key and the configuration fuse value are to be provided to a key server. The key server is to determine that the configuration fuse value indicates that the apparatus is a production component, and, in response, provide a fuse key to be stored in the plurality of fuses. | 07-03-2014 |
20140189365 | SECURE KEY DERIVATION AND CRYPTOGRAPHY LOGIC FOR INTEGRATED CIRCUITS - A processor of an aspect includes root key generation logic to generate a root key. The root key generation logic includes a source of static and entropic bits. The processor also includes key derivation logic coupled with the root key generation logic. The key derivation logic is to derive one or more keys from the root key. The processor also includes cryptographic primitive logic coupled with the root key generation logic. The cryptographic primitive logic is to perform cryptographic operations. The processor also includes a security boundary containing the root key generation logic, the key derivation logic, and the cryptographic primitive logic. Other processors, methods, and systems are also disclosed. | 07-03-2014 |
20140189890 | DEVICE AUTHENTICATION USING A PHYSICALLY UNCLONABLE FUNCTIONS BASED KEY GENERATION SYSTEM - At least one machine accessible medium having instructions stored thereon for authenticating a hardware device is provided. When executed by a processor, the instructions cause the processor to receive two or more device keys from a physically unclonable function (PUF) on the hardware device, generate a device identifier from the two or more device keys, obtain a device certificate from the hardware device, perform a verification of the device identifier, and provide a result of the device identifier verification. In a more specific embodiment, the instructions cause the processor to perform a verification of a digital signature in the device certificate and to provide a result of the digital signature verification. The hardware device may be rejected if at least one of the device identifier verification and the digital signature verification fails. | 07-03-2014 |
20140201540 | SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS - Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor. | 07-17-2014 |
20140205090 | METHOD AND SYSTEM FOR SECURELY COMPUTING A BASE POINT IN DIRECT ANONYMOUS ATTESTATION - A method and system computes a basepoint for use in a signing operation of a direct anonymous attestation scheme. The method and system includes computing a basepoint at a host computing device and verifying the base point at a trusted platform module (TPM) device. | 07-24-2014 |
20140218067 | GROUPING OF PHYSICALLY UNCLONABLE FUNCTIONS - A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits are more repeatable than the individual PUF elements. The value K may be selected such that (K+ | 08-07-2014 |
20140270177 | HARDENING INTER-DEVICE SECURE COMMUNICATION USING PHYSICALLY UNCLONABLE FUNCTIONS - Embodiments of an invention for hardened inter-device secure communication using physically unclonable functions are disclosed. In one embodiment, an apparatus includes a first storage location, a second storage location, a physically unclonable function (PUF) circuit, a PUF key generator, and an encryption unit. The first storage location is to store an embedded key. The second storage location is to store a fuse key. The PUF circuit is to provide a PUF value. The PUF key generator is to generate a PUF key based on the PUF value. The encryption unit is to receive from a key server a global key encrypted using the embedded key, decrypt the global key using the embedded key, encrypt the global key using the PUF key, and store the global key encrypted using the PUF key in the second storage location. | 09-18-2014 |
20150092939 | DARK BITS TO REDUCE PHYSICALLY UNCLONABLE FUNCTION ERROR RATES - Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array. | 04-02-2015 |
20150095654 | CRYPTOGRAPHIC KEY GENERATION BASED ON MULTIPLE BIOMETRICS - In an embodiment, an apparatus includes a processor including a first core. The first core includes multi-biometric logic to output first biometric data w | 04-02-2015 |
20150178143 | USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION - Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit. | 06-25-2015 |
20150188717 | PHYSICALLY UNCLONABLE FUNCTION REDUNDANT BITS - Embodiments of an invention for using physically unclonable function redundant bits are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and redundancy logic. The PUF cell array includes a plurality of redundant cells and is to provide a raw PUF value. The redundancy logic is to generate a redirection list to be used to replace each of one or more bits of the raw PUF value with a redundant bit value from one of the redundant cells. | 07-02-2015 |
Patent application number | Description | Published |
20080219590 | Method and system for correlating physical model representation to pattern layout - One embodiment of the present invention provides a system that reduces computational complexity in simulating an image resulting from an original mask and an optical transmission system. During operation, the system obtains a set transmission cross coefficient (TCC) kernel functions based on the optical transmission system, and obtains a set of transmission functions for a representative pattern which contains features representative of the original mask. The system constructs a new set of kernel functions based on the TCC kernel functions and the transmission functions for the representative pattern, wherein responses to the new kernel functions in a resulting image corresponding to the representative pattern are substantially uncorrelated with one another. The system further produces an intensity distribution of a resulting image corresponding to the original mask based on the new kernel functions, thereby facilitating prediction of a layout that can be produced from the original mask. | 09-11-2008 |
20080235651 | Method and apparatus for determining an optical model that models the effects of optical proximity correction - One embodiment provides a system that can enable a designer to determine the effects of subsequent processes at design time. During operation, the system may receive a test layout and an optical model that models an optical system, but which does not model the effects of subsequent processes, such as optical proximity correction (OPC). The system may generate a first dataset using the test layout and the optical model. Next, the system may apply OPC to the test layout, and generate a second dataset using the corrected test layout and the optical model. The system may then use the first dataset and the second dataset to adjust the optical model to obtain a second optical model that models the effects of subsequent processes. | 09-25-2008 |
20080276211 | Method and apparatus for determining a process model using a 2-D-pattern detecting kernel - One embodiment provides a system for determining an improved process model that models one or more semiconductor manufacturing processes. During operation, the system can receive a first process model. Next, the system can receive a 2-D-pattern detecting kernel which can detect 2-D patterns. The system can then receive a second set of empirical data which is associated with 2-D patterns in a test layout. Next, the system can determine an improved process model using the first process model, the 2-D-pattern detecting kernel, the test layout, and the second set of empirical data. | 11-06-2008 |
20100086196 | METHOD AND APPARATUS FOR DETERMINING AN OPTICAL THRESHOLD AND A RESIST BIAS - One embodiment of the present invention provides techniques and systems for determining modeling parameters for a photolithography process. During operation, the system can receive a layout. Next, the system can determine an iso-focal pattern in the layout. The system can then determine multiple aerial-image-intensity values in proximity to the iso-focal pattern by convolving the layout with multiple optical models, wherein the multiple optical models model the photolithography process's optical system under different focus conditions. Next, the system can determine a location in proximity to the iso-focal pattern where the aerial-image-intensity values are substantially insensitive to focus variations. The system can then use the location and the associated aerial-image-intensity values to determine an optical threshold and a resist bias. The optical threshold and the resist bias can then be used for modeling the photolithography process. | 04-08-2010 |
20100115486 | ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD - One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target patterns in response to changes in focus condition of the lithography system. Note that the contours of the target patterns substantially coincide with the edges of set of the polygons. Next, the system computes a cost-covariance field (CCF field) based on the focus-sensitive cost function, wherein the CCF field is a two-dimensional (2D) map representing changes to the focus-sensitive cost function due to an addition of a pattern at a given location within the post-OPC mask layout. Finally, the system generates assist features for the post-OPC mask layout based on the CCF field. | 05-06-2010 |
20110202891 | EVALUATING THE QUALITY OF AN ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD - One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target patterns in response to changes in focus condition of the lithography system. Note that the contours of the target patterns substantially coincide with the edges of set of the polygons. Next, the system computes a cost-covariance field (CCF field) based on the focus-sensitive cost function, wherein the CCF field is a two-dimensional (2D) map representing changes to the focus-sensitive cost function due to an addition of a pattern at a given location within the post-OPC mask layout. Finally, the system generates assist features for the post-OPC mask layout based on the CCF field. | 08-18-2011 |
Patent application number | Description | Published |
20080213597 | Formaldehyde-Free Adhesives and Lignocellulosic Composites Made from the Adhesives - A first variant of an adhesive composition for making a lignocellulosic composite includes soy protein and/or lignin; at least one substantially formaldehyde-free curing agent that includes at least one amine, amide, imine, imide, or nitrogen-containing heterocyclic functional group that can react with at least one functional group of the soy protein; and at least one compound selected from a boron compound, a group IA oxide or hydroxide, or a group IIA oxide or hydroxide. A second variant of an adhesive composition includes a first component selected from soy protein and/or lignin; and at least one substantially formaldehyde-free curing agent selected from a reaction product of epichlorohydrin with ethylenediamine, a reaction product of epichlorohydrin with bis-hexamethylenetriamine, or a reaction product of epichlorohydrin with hexamethylenediamine. | 09-04-2008 |
20130078464 | VEGETABLE OIL-BASED PRESSURE SENSITIVE ADHESIVES - A pressure sensitive adhesive construct comprising:
| 03-28-2013 |
20130302631 | SOY ADHESIVES AND COMPOSITES MADE FROM THE ADHESIVES - A formaldehyde-free aqueous adhesive composition comprising (a) soy protein and (b) magnesium oxide or a mixture of magnesium oxide and magnesium hydroxide, wherein components (a) and (b) together constitute at least 50 weight percent of the composition, excluding the weight of the water. | 11-14-2013 |
20140314905 | CHEWING GUM BASE CONTAINING SUBSTITUTED POLYSACCHARIDES AND CHEWING GUM PRODUCTS MADE THERE FROM - A chewing gum base comprises food acceptable substituted polysaccharides wherein substituents on the saccharide units in the polysaccharides produce a degree of substitution of at least I.0. The polysaccharides may have branches with an average length of 1 to 15 saccharide units per branch. The polysaccharides may be linked saccharide units such as allose, altrose, mannose, gulose, idose, galactose, 3,6 anhydro galactose, glucuronic acid, mannuronic acid, galacturonic acid, aldobiouronic acid, fucose, rhamnose, arabinose, xylose, talose, acyl substituted glucose, fructose, lactose and combinations thereof. | 10-23-2014 |
20140342153 | VEGETABLE OIL-BASED PRESSURE-SENSITIVE ADHESIVES - One embodiment is a pressure sensitive adhesive construct comprising:
| 11-20-2014 |
20140345797 | PRESSURE SENSITIVE ADHESIVES BASED ON FATTY ACIDS - A method for making a pressure sensitive adhesive comprising:
| 11-27-2014 |
20140349109 | PRESSURE SENSITIVE ADHESIVES BASED ON CARBOXYLIC ACIDS AND EPOXIDES - A method for making a pressure sensitive adhesive comprising:
| 11-27-2014 |
Patent application number | Description | Published |
20080315831 | AC-TO-DC ADAPTER FOR MOBILE SYSTEM - Disclosed herein are approaches for providing an adapter that may operate efficiently to provide a DC voltage to systems requiring different voltages. | 12-25-2008 |
20080315833 | BATTERY PULSE CHARGING METHOD AND APPARATUS - Disclosed herein are some embodiments for safely charging a mobile system battery pack, even when the power source (e.g., adapter) voltage is at a relatively high level that would otherwise result in excessive charge current. | 12-25-2008 |
20080315842 | POWER ADAPTER DETECTION - According to some embodiments, an apparatus for power adapter detection is disclosed. The apparatus includes a first detection module to detect if a first signal from a power adapter is present and in a first voltage range, a second detection module to detect if a second signal from the power adapter is present and in a second voltage range, and a third module to permit a system to be powered by the power adapter if the first signal is present and in the first voltage range and if the second signal is present and in the second voltage range. | 12-25-2008 |
20080320320 | MOBILE POWER CONTROL APPARATUS AND METHOD - Disclosed herein are approaches for reducing the difference in voltage between a DC power source and a system supply voltage for a mobile system, for example, to reduce over-voltages, inrush currents, and power conversion inefficiencies when a DC source such as an adapter is connected to the mobile system. | 12-25-2008 |
20090088992 | Intelligent battery safety management - A method and apparatus for intelligent battery safety management. Some embodiments of a method for managing battery operation may include receiving a battery pack in a device, where the battery pack is rechargeable and includes a battery cell. In some embodiments data may be collected regarding the operation of the battery cell in the device, and the collected data may be compared with a set of battery reference data. In some embodiments a determination may be made whether the battery cell is non-authentic or defective based at least in part on the comparison between the collected data and the battery reference data. | 04-02-2009 |
20090167312 | SHORT CIRCUIT DETECTION FOR BATTERIES - A method and apparatus for short circuit detection for batteries. Some embodiments of a method include receiving a battery pack in a system, where the battery pack is rechargeable and includes multiple battery cell blocks, each cell block including one or more battery cells. The voltages of the plurality of cell blocks are monitored. Upon shutting down the system, the voltages of the plurality of cell blocks are logged to generate a set of logged voltage values. Upon restarting the system, the current voltage values of the cell blocks are measured. A determination whether any of the battery cells of the battery pack has developed a short circuit is made based at least in part on a comparison of the current voltage values with the set of the logged voltage values. | 07-02-2009 |
20100153757 | BALANCING POWER SUPPLY AND DEMAND - A method and apparatus to balance adapter power supply and computing device power demand. In one embodiment, power to/from battery pack(s) maybe controlled by adjusting the output voltage of the power adapter via the current input to the power adapter through a feedback pin to meet power demand of electrical loads. Another embodiment provides a way to adjust the activities of the electrical loads such that neither adapter power rating nor the electrical load power limit is exceeded while avoiding system shutdown. | 06-17-2010 |
20120169295 | BATTERY PULSE CHARGING METHOD AND APPARATUS - Disclosed herein are some embodiments for safely charging a mobile system battery pack, even when the power source (e.g., adapter) voltage is at a relatively high level that would otherwise result in excessive charge current. | 07-05-2012 |
20120253714 | BATTERY VOLTAGE MEASUREMENT - An apparatus is provided that includes a first circuit to determine when a battery current falls below a threshold, a second circuit to measure a battery voltage and current in response to the first circuit determining that the battery current falls below the threshold, and a third circuit to store the measured battery voltage and current. | 10-04-2012 |
20130154568 | Balancing Power Supply and Demand - A method and apparatus to balance adapter power supply and computing device power demand. In one embodiment, power to/from battery pack(s) maybe controlled by adjusting the output voltage of the power adapter via the current input to the power adapter through a feedback pin to meet power demand of electrical loads. Another embodiment provides a way to adjust the activities of the electrical loads such that neither adapter power rating nor the electrical load power limit is exceeded while avoiding system shutdown. | 06-20-2013 |
20150105925 | Balancing Power Supply and Demand - A method and apparatus to balance adapter power supply and computing device power demand. In one embodiment, power to/from battery pack(s) maybe controlled by adjusting the output voltage of the power adapter via the current input to the power adapter through a feedback pin to meet power demand of electrical loads. Another embodiment provides a way to adjust the activities of the electrical loads such that neither adapter power rating nor the electrical load power limit is exceeded while avoiding system shutdown. | 04-16-2015 |
20150180262 | BATTERY PULSE CHARGING METHOD AND APPARATUS - Disclosed herein are some embodiments for safely charging a mobile system battery pack, even when the power source (e.g., adapter) voltage is at a relatively high level that would otherwise result in excessive charge current. | 06-25-2015 |
Patent application number | Description | Published |
20090125909 | Device, system, and method for multi-resource scheduling - A method, apparatus and system for selecting a highest prioritized task for executing a resource from one of a first and second expired scheduling arrays, where the first and second expired scheduling arrays may prioritize tasks for using the resource, and where tasks in the first expired scheduling array may be prioritized according to a proportionality mechanism and tasks in the second expired scheduling array may be prioritized according to an importance factor determined, for example, based on user input, and executing the task. Other embodiments are described and claimed. | 05-14-2009 |
20110153926 | Controlling Access To A Cache Memory Using Privilege Level Information - In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed. | 06-23-2011 |
20140013086 | ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS - A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register. | 01-09-2014 |
20140082630 | PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM - In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed. | 03-20-2014 |
20140189306 | ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION - An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled. | 07-03-2014 |
20140201505 | PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR - A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions. | 07-17-2014 |
20140310504 | Systems and Methods for Flag Tracking in Move Elimination Operations - Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation. | 10-16-2014 |
20140337604 | MINIMIZING BANDWIDTH TO TRACK RETURN TARGETS BY AN INSTRUCTION TRACING SYSTEM - A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The processing device further includes a retirement unit comprising an instruction tracing module to initiate instruction tracing for instructions executed by the processing device, determine whether the target address of the RET instruction was mispredicted, determine a value of call depth counter (CDC) maintained by the instruction tracing module, and when the target address of the RET instruction was not mispredicted and when the value of the CDC is greater than zero, generate an indication that the RET instruction branches to a next linear instruction after the corresponding CALL instruction. | 11-13-2014 |
20150095627 | TWO LEVEL RE-ORDER BUFFER - In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution. | 04-02-2015 |
Patent application number | Description | Published |
20130007325 | SECURE HANDLING OF INTERRUPTED EVENTS - Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed. | 01-03-2013 |
20140096068 | DEVICE AND METHOD FOR SECURE USER INTERFACE GESTURE PROCESSING USING PROCESSOR GRAPHICS - A device and method for securely rendering content on a gesture-enabled computing device includes initializing a secure execution environment on a processor graphics of the computing device. The computing device transfers view rendering code and associated state data to the secure execution environment. An initial view of the content is rendered by executing the view rendering code in the secure execution environment. A gesture is recognized, and an updated view of the content is rendered in the secure execution environment in response to the gesture. The gesture may include a touch gesture recognized on a touch screen, or a physical gesture of the user recognized by a camera. After the updated view of the content is rendered, the main processor of the computing device may receive updated view data from the secure execution environment. | 04-03-2014 |
20140115702 | ENCRYPTED DATA INSPECTION IN A NETWORK ENVIRONMENT - Technologies are provided in example embodiments for analyzing an encrypted network flow. The technologies include monitoring the encrypted network flow between a first node and a second node, the network flow initiated from the first node; duplicating the encrypted network flow to form a copy of the encrypted network flow; decrypting the copy of the encrypted network flow using a shared secret, the shared secret associated with the first node and the second node; and scanning the network flow copy for targeted data. | 04-24-2014 |
20140189194 | LOW OVERHEAD PAGED MEMORY RUNTIME PROTECTION - Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission information is provided through an Extended Page Table (EPT). Other embodiments are also described. | 07-03-2014 |
20140310809 | PREVENTING MALICIOUS INSTRUCTION EXECUTION - Systems and techniques for preventing malicious instruction execution are described herein. A first instance of an instruction for a graphics processing unit (GPU) may be received. The instruction may be placed in a target list. A notification that the instruction caused a problem with the GPU may be received. The instruction may be moved from the target list to a black list in response to the notification. A second instance of the instruction may be received. The second instance of the instruction may be prevented from executing on the GPU in response to the instruction being on the black list. | 10-16-2014 |
20140365742 | SYSTEMS AND METHODS FOR PREVENTING UNAUTHORIZED STACK PIVOTING - An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address. | 12-11-2014 |
Patent application number | Description | Published |
20090007150 | Method and Apparatus for Improving the Efficiency of Interrupt Delivery at Runtime in a Network System - Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered may either run the target application/thread or be located in the same socket as the processor that runs the target application/thread. The processor affinity of the application/thread may be pushed down at runtime to a network device, a chipset, a memory control hub (“MCH”), or an input/output hub (“IOH”), which will facilitate delivery of the interrupt using that affinity information. | 01-01-2009 |
20090323692 | Hashing packet contents to determine a processor - The disclosure includes a description of an apparatus having circuitry to determine a first hash value for a first packet tuple of a first packet traveling in a first direction of a duplex connection and determine a processor for the first packet from a set of multiple processors based, at least in part, on the first hash value. The apparatus includes circuitry to determine a second hash value for a second packet tuple of a second packet traveling in a second direction of the duplex connection and determine the same processor for the second packet from the set of multiple processors based, at least in part, on the second hash value. | 12-31-2009 |
20110142050 | HASHING PACKET CONTENTS TO DETERMINE A PROCESSOR - The disclosure includes a description of an apparatus having circuitry to determine a first hash value for a first packet tuple of a first packet traveling in a first direction of a duplex connection and determine a processor for the first packet from a set of multiple processors based, at least in part, on the first hash value. The apparatus includes circuitry to determine a second hash value for a second packet tuple of a second packet traveling in a second direction of the duplex connection and determine the same processor for the second packet from the set of multiple processors based, at least in part, on the second hash value. | 06-16-2011 |
20110153935 | NUMA-AWARE SCALING FOR NETWORK DEVICES - The present disclosure describes a method and apparatus for network traffic processing in a non-uniform memory access architecture system. The method includes allocating a Tx/Rx Queue pair for a node, the Tx/Rx Queue pair allocated in a local memory of the node. The method further includes routing network traffic to the allocated Tx/Rx Queue pair. The method may include designating a core in the node for network traffic processing. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 06-23-2011 |
20120254492 | TRAFFIC CLASS BASED ADAPTIVE INTERRUPT MODERATION - An apparatus which comprises two or more moderation timers associated with an interrupt vector is presented. In one embodiment, the apparatus comprises two or more interrupt vectors and moderation timers are set with different interrupt rates. An interrupt vector logic unit sends an interrupt vector if there is an interrupt event from the queue associated with a moderation timer and the moderation timer expires. | 10-04-2012 |
20120331083 | RECEIVE QUEUE MODELS TO REDUCE I/O CACHE FOOTPRINT - A method according to one embodiment includes the operations of configuring a primary receive queue to designate a first plurality of buffers; configuring a secondary receive queue to designate a second plurality of buffers, wherein said primary receive queue is sized to accommodate a first network traffic data rate and said secondary receive queue is sized to provide additional accommodation for burst network traffic data rates; selecting a buffer from said primary receive queue, if said primary receive queue has buffers available, otherwise selecting a buffer from said secondary receive queue; transferring data from a network controller to said selected buffer; indicating that said transferring to said selected buffer is complete; reading said data from said selected buffer; and returning said selected buffer, after said reading is complete, to said primary receive queue if said primary receive queue has space available for the selected buffer, otherwise returning said selected buffer to said secondary receive queue. | 12-27-2012 |
20130173895 | METHOD AND APPARATUS FOR IMPROVING THE EFFICIENCY OF INTERRUPT DELIVERY AT RUNTIME IN A NETWORK SYSTEM - Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered may either run the target application/thread or be located in the same socket as the processor that runs the target application/thread. The processor affinity of the application/thread may be pushed down at runtime to a network device, a chipset, a memory control hub (“MCH”), or an input/output hub (“IOH”), which will facilitate delivery of the interrupt using that affinity information. | 07-04-2013 |
20130262718 | Adaptive Queuing of a Cache for a Processing Element - Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure. | 10-03-2013 |
20130326000 | NUMA-AWARE SCALING FOR NETWORK DEVICES - The present disclosure describes a method and apparatus for network traffic processing in a non-uniform memory access architecture system. The method includes allocating a Tx/Rx Queue pair for a node, the Tx/Rx Queue pair allocated in a local memory of the node. The method further includes routing network traffic to the allocated Tx/Rx Queue pair. The method may include designating a core in the node for network traffic processing. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 12-05-2013 |
20140040514 | ADAPTIVE INTERRUPT MODERATION - Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate. | 02-06-2014 |
20140280709 | FLOW DIRECTOR-BASED LOW LATENCY NETWORKING - Generally, this disclosure relates to low latency networking. A system may include processor circuitry comprising at least one processor; memory circuitry configured to store an application, a receive queue and a networking stack comprising a network device driver; a network controller comprising a flow director, the network controller configured to couple the host device to at least one link partner and the flow director configured to store one or more selected received packets in the receive queue, the selecting based, at least in part, on a packet flow identifier; and a network device driver configured to identify the receive queue in response to a polling request comprising the packet flow identifier; poll the receive queue; and process each received packet stored in the receive queue. | 09-18-2014 |
20150186307 | ADAPTIVE INTERRUPT MODERATION - Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate. | 07-02-2015 |