Patent application number | Description | Published |
20100251068 | STORAGE CONTROLLER WITH ENCODING/DECODING CIRCUIT PROGRAMMABLE TO SUPPORT DIFFERENT ECC REQUIREMENTS AND RELATED METHOD THEREOF - One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit. | 09-30-2010 |
20100332734 | FLASH MEMORY DEVICES AND METHODS FOR CONTROLLING A FLASH MEMORY DEVICE - A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array. | 12-30-2010 |
20100332887 | STORAGE CONTROL DEVICE HAVING CONTROLLER OPERATED ACCORDING TO DETECTION SIGNAL DERIVED FROM MONITORING POWER SIGNAL AND RELATED METHOD THEREOF - One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range. | 12-30-2010 |
20100332922 | METHOD FOR MANAGING DEVICE AND SOLID STATE DISK DRIVE UTILIZING THE SAME - A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner. | 12-30-2010 |
20120207191 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package. | 08-16-2012 |
20140189415 | MEDIA PERIPHERAL INTERFACE, ELECTRONIC DEVICE WITH MEDIA PERIPHERAL INTERFACE, AND COMMUNICATION METHOD BETWEEN PROCESSOR AND PERIPHERAL DEVICE - A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured. | 07-03-2014 |
20150140939 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package. | 05-21-2015 |
20150155905 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the RF unit and the first memory are packaged in a single semiconductor device. | 06-04-2015 |