Leijten
Jeroen Leijten, Hulsel NL
Patent application number | Description | Published |
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20150278132 | SYSTEM AND METHOD FOR MEMORY ACCESS - A memory controller performs DMA operations on arbitrary sized elements unbounded by the word size of the host memory or processor, which performs operations based on an element that represents an atomic data unit such as a pixel. In this manner, a corresponding coding effort is not concerned with computing and locating word boundaries and accommodating unused bits of data conventionally used for accommodating word boundaries on pixel data for video rendering, for example. An element in memory corresponds to a rendered atomic data item, such as a pixel. The controller determines an element precision indicative of a size of the element, and identifies a unit of memory based on a memory location and a packed representation of a plurality of the elements relative to the memory location. The unit has a height and width, defining elements arranged in a grid, and an element position is based on coordinates. | 10-01-2015 |
Jeroen Anton Johan Leijten, Hulsel NL
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20090281784 | Method And Apparatus For Designing A Processor - A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics. | 11-12-2009 |
20100185835 | Data Processing Circuit With A Plurality Of Instruction Modes, Method Of Operating Such A Data Circuit And Scheduling Method For Such A Data Circuit - A data processing circuit has an execution circuit ( | 07-22-2010 |
20120179894 | Data Processing Circuit With A Plurality Of Instruction Modes, Method Of Operating Such A Data Circuit And Scheduling Method For Such A Data Circuit - A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command. | 07-12-2012 |
20120265972 | METHOD AND APPARATUS AND RECORD CARRIER - Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S | 10-18-2012 |
Jeroen Anton Johan Leijten, Eindhoven NL
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20100153691 | LOWER POWER ASSEMBLER - A method for processing data using a time-stationary multiple-instruction word processing apparatus, arranged to execute a plurality of instructions in parallel, said method comprising the following steps: generating a set of multiple-instruction words (INS(i), INS(i+1), INS(i+2)), wherein each multiple-instruction word comprises a plurality of instruction fields, wherein each instruction field encodes control information for a corresponding resource of the processing apparatus, and wherein bit changes between an instruction field related to a no-operation instruction, and a corresponding instruction field of an adjacent multiple-instruction word are minimised; storing input data in a register file (RF | 06-17-2010 |