Patent application number | Description | Published |
20090319631 | COMPOSING, BROWSING, REPLYING, FORWARDING E-MAIL - Method for composing, browsing, replying, forwarding e-mail's in an e-mail system and an e-mail client that can reduce e-mail traffic by not sending the original e-mail content in replying or forwarding e-mail's. In accordance with this invention, each e-mail has a Global-ID and each reply e-mail has a Reply-to-ID which corresponds to the Global-ID of the original e-mail, thereby the content of the original e-mail is not contained in the reply e-mail. During browsing e-mail's, the original e-mail is retrieved from repositories which stores sent and received e-mail's, and is incorporated into the browsed e-mail. | 12-24-2009 |
20090319632 | COMPOSING, BROWSING, REPLYING, FORWARDING E-MAIL - Method for composing, browsing, replying, forwarding e-mail's in an e-mail system and an e-mail client that can reduce e-mail traffic by not sending the original e-mail content in replying or forwarding e-mail's. In accordance with this invention, each e-mail has a Global-ID and each reply e-mail has a Reply-to-ID which corresponds to the Global-ID of the original e-mail, thereby the content of the original e-mail is not contained in the reply e-mail. During browsing e-mail's, the original e-mail is retrieved from repositories which stores sent and received e-mail's, and is incorporated into the browsed e-mail. | 12-24-2009 |
20110221351 | Active matrix organic electroluminescence device and a method of manufacture - The present invention discloses an active matrix organic electroluminescence device comprising a thin-film transistor, an organic electroluminescence device, and an interlayer deposited between the thin-film transistor and the organic electroluminescence device, wherein the interlayer is made of cationic ultraviolet-curing adhesive comprising epoxy resin or modified epoxy resin, diluting agent, cationic photo initiator. The interlayer solves poor adhesiveness between the driving circuit and the organic electroluminescence device, and improves the moisture and oxygen proof ability. The preparation method is simple, effective, and able to lower the cost and difficulty, and greatly improve the yield rate. | 09-15-2011 |
20120098058 | Semiconductor Device and Associated Fabrication Method - A semiconductor device and a method for forming the semiconductor device wherein the semiconductor comprises: a trench MOSFET, formed on a semiconductor initial layer, comprising a well region, wherein the semiconductor initial layer has a first conductivity type and wherein the well region has a second conductivity type; an integrated Schottky diode next to the trench MOSFET, comprising a anode metal layer contacted to the semiconductor initial layer; a trench isolation structure, coupled between the trench MOSFET and integrated Schottky diode, configured to resist part of lateral diffusion from the well region; wherein the well region comprises an overgrowth part which laterally diffuses under the trench isolation structure and extends out of it. | 04-26-2012 |
20120104467 | SELF-ALIGNED CONTACT STRUCTURE TRENCH JFET - According to one embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region near a bottom portion of the trench and an interlayer dielectric layer (ILDL) above the P-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, an N+ source region above the channel region extending between a top of each trench, and a source metal above the N+ source region. In another embodiment, a self-aligned trench structure JFET includes a silicon substrate, two or more trenches having an N-type polysilicon gate region near a bottom portion of the trench and an ILDL above the N-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, a P+ source region above the channel region extending between a top of each trench, and a source metal above the P+ source region. | 05-03-2012 |
20120161225 | INTEGRATED MOSFET DEVICES WITH SCHOTTKY DIODES AND ASSOCIATED METHODS OF MANUFACTURING - The present technology discloses a semiconductor die integrating a MOSFET device and a Schottky diode. The semiconductor die comprises a MOSFET area comprising the active region of MOSFET, a Schottky diode area comprising the active region of Schottky diode, and a termination area comprising termination structures. Wherein the Schottky diode area is placed between the MOSFET area and the termination area such that the Schottky diode area surrounds the MOSFET area. | 06-28-2012 |
20120241862 | LDMOS DEVICE AND METHOD FOR MAKING THE SAME - The embodiments of the present disclosure disclose a LDMOS device and the method for making the LDMOS device. The LDMOS device comprises at least one capacitive region formed in the drift region. Each capacitive region comprises a polysilicon layer and a thick oxide layer separating the polysilicon layer from the drift region. The LDMOS device in accordance with the embodiments of the present disclosure can improve the breakdown voltage while a low on-resistance is maintained. | 09-27-2012 |
20120280311 | TRENCH-GATE MOSFET DEVICE AND METHOD FOR MAKING THE SAME - The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device. | 11-08-2012 |
20130043534 | HIGH DENSITY LATERAL DMOS AND ASSOCIATED METHOD FOR MAKING - The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication. | 02-21-2013 |
20130153999 | TRENCH GATE MOSFET DEVICE - A trench gate MOSFET device has a drain region, a drift region, a trench gate having a gate electrode and a poly-silicon region, a super junction pillar juxtaposing the trench gate, a body region and a source region. By the interaction among the trench gate, the drift region and the super junction pillar, the break down voltage of the trench gate MOSFET device may be relatively high while the on-state resistance of the trench gate MOSFET device may be maintained relatively small. | 06-20-2013 |
20130234245 | SEMICONDUCTOR DEVICE AND ASSOCIATED FABRICATION METHOD - A super junction structural semiconductor device with a substantially rectangle-shaped first region, and a second region surrounding the periphery of the first region; trench gate MOSFET units in the first region comprising a plurality of trench gate regions and a first plurality of pillars; a body region between the trench gate regions and the first plurality of pillars; a second plurality of pillars in the second region extending along a corresponding side of the first region comprising a plurality of lateral pillars and a plurality of longitudinal pillars, wherein in a corner part of the second region, ends of the plurality of lateral pillars and ends of the plurality of longitudinal pillars are stagger and separated apart from each other. | 09-12-2013 |
20130328122 | SPLIT TRENCH-GATE MOSFET WITH INTEGRATED SCHOTTKY DIODE - A split trench-gate MOSFET device and method for forming this device is disclosed. The device has a trench gate structure, comprising a shield electrode and two gate electrodes, wherein a substantial portion of shield electrode region is lower than the gate electrode region, and wherein a portion of the shield electrode region extends to the top surface between the two gate electrodes. The device further comprises a source metal layer, contacting to an initial layer, a well region, the shield electrode and a source region at the top surface, wherein the contact between the source metal layer and the initial layer forms a Schottky diode. | 12-12-2013 |
20140015017 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND THE ASSOCIATED METHOD OF MANUFACTURING - The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer. | 01-16-2014 |
20140117415 | JUNCTION FIELD EFFECT TRANSISTORS AND ASSOCIATED FABRICATION METHODS - A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region. | 05-01-2014 |
20140117416 | SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING - A semiconductor device having a trench-gate MOSFET and a vertical JFET formed in a semiconductor layer. In the semiconductor device, a gate region of the vertical JFET may be electrically coupled to a source region of the trench-gate MOSFET, and a drain region of the vertical JFET and a drain region of the trench-gate MOSFET may share a common region in the semiconductor layer. | 05-01-2014 |
20140159143 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND ASSOCIATED FABRICATION METHOD - A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device. | 06-12-2014 |