Lee, Zhubei City
An-Shih Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120134602 | METHOD AND APPARATUS FOR IMAGE CONVERSION - An image conversion device is disclosed, having an image converting circuit for receiving a first and a second image frames of a first format and generating a third and a fourth image frames of a second format; and a signal generating circuit coupled with the image converting circuit for generating a plurality of first synchronization signals having a substantially fixed period and one or more second synchronization signals for the third and the fourth image frames, wherein each of the second synchronization signals is synchronized with one of the first synchronization signals and the third image frame contains at least one more first synchronization signal than the fourth image frame. | 05-31-2012 |
Chao-Tang Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140331223 | METHOD AND SYSTEM FOR SINGLE ROOT INPUT/OUTPUT VIRTUALIZATION VIRTUAL FUNCTIONS SHARING ON MULTI-HOSTS - In a method for SR-IOV Virtual Functions Sharing on Multi-Hosts, implemented in a management system, one or more fake devices are simulated in one or more hosts with each fake device corresponding to one of a plurality of SR-IOV virtual functions. Each of one or more configuration spaces is redirected from each SR-IOV virtual function to each fake device, respectively. Each of configuration space requests is redirected from a corresponding fake device to a corresponding SR-IOV virtual function when the configuration space request is received. And each of memory access operations is redirected from the corresponding SR-IOV virtual function to a mapped memory on a corresponding host with the corresponding fake device, and each of interrupts generated by one or more SR-IOV virtual machines is redirected to the corresponding fake device. | 11-06-2014 |
Chien-Hui Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20160113162 | COVER FILM - The present disclosure provides a cover film, including a conductive adhesive layer, an electromagnetic shielding layer formed on the conductive adhesive layer, and an insulating layer formed on the electromagnetic shielding layer. The electromagnetic shielding layer has a thickness of from 0.01 to 25 micrometers, such that the cover film can shield electromagnetic interference through the thinner interposed electromagnetic shielding layer. | 04-21-2016 |
Chien-Lung Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120243419 | METHOD FOR TESTING THE COMMUNICATION PERFORMANCE OF A PLURALITY OF WIRELESS SIGNAL ACCESS DEVICES - A method used for testing the communication performance of a plurality of wireless signal access devices, and the steps of the testing method of each wireless signal access device include: (a). booting up the wireless signal access device; (b). activating said the wireless signal access device to transmit or receive testing packets to test the communication performance of the wireless signal access device. The feature of the present invention lies in completing a step a of the next wireless signal access device before completing a step b of a first wireless signal access device, and starting the step b of the next wireless signal access device in an appropriate timing after completing the step b of the first wireless signal access device, thereby reaching the goal of reducing the test time. | 09-27-2012 |
Chien-Yuan Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100314709 | LATCH-UP PREVENTION STRUCTURE AND METHOD FOR ULTRA-SMALL HIGH VOLTAGE TOLERANT CELL - A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level. | 12-16-2010 |
20140268457 | HIGH VOLTAGE PROTECTION APPARATUS AND METHOD - An apparatus includes first and second switches. The first switch is for coupling a first node to a second node responsive to a first control signal having a first value, and for decoupling these nodes responsive to the first control signal having a second value. The second switch is for coupling the first node to a third node responsive to a second control signal having the first value, and for decoupling these nodes responsive to the second control signal having the second value. A load is coupled between the second and third nodes. A detection circuit coupled to the first node is configured to generate a signal indicating whether voltage at the first node exceeds a threshold. First and second modules are configured to set the first and second control signals to the second value responsive to the signal indicating that the voltage at the first node exceeds the threshold. | 09-18-2014 |
20150021713 | GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT - Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring. | 01-22-2015 |
20150077886 | Electrostatic Discharge Protection Circuit and Related Method - A device includes a first power transistor, a second power transistor electrically connected in series with the first power transistor, a first electrostatic discharge (ESD) detection circuit, and a first control circuit electrically connected to the first ESD detection circuit and the first power transistor. | 03-19-2015 |
20150294968 | FinFET AND TRANSISTORS WITH RESISTORS AND PROTECTION AGAINST ELECTROSTATIC DISCHARGE (ESD) - A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device. | 10-15-2015 |
Chi-Wei Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150357537 | SUBSTRATE STRUCTURE APPLICABLE TO VERTICAL LIGHT EMITTING ELEMENT AND VERTICAL LIGHT EMITTING ELEMENT THEREOF - The present invention discloses a substrate structure applicable to a vertical light emitting element and a vertical light emitting element thereof. The substrate structure comprises a transparent substrate and a reflective layer, and the reflective layer is used to improve a focus of a yellow light manufacturing process. The technique is applicable to PSS substrate and the substrate structure is used to produce the vertical light emitting element to increase the light emitting efficiency. | 12-10-2015 |
20150380603 | LIGHT-EMITTING ELEMENT SUBSTRATE AND LIGHT-EMITTING ELEMENT USING THE SAME - A light-emitting element substrate and a light-emitting element using the same are disclosed. The light-emitting element substrate includes a transparent substrate and an intermediate layer. The transparent substrate has a plurality of microstructures on a surface thereof, top portion of each microstructure is a plane structure, and an adjacent interval between the plane structures is between 0.5 μm and 2.5 μm, the plurality of microstructures have gaps therebetween, and the intermediate layer is covered on the plane structures for facilitating production of epitaxial layer. In an embodiment, the gaps of the plurality of microstructures are still reserved when the epitaxial layer is grown on the plurality of microstructures so as to improve light extraction efficiency of the light-emitting element using the light-emitting element substrate. | 12-31-2015 |
Chung-Li Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150201502 | Tool And Method Of Reflow - A tool and a method of reflow are provided. In various embodiments, the tool includes a chamber unit, a wafer lifting system, a heater, and an exhausting unit. The wafer lifting system is disposed in the chamber unit. The heater is coupled to the chamber unit, and configured to heat the wafer. The exhausting unit coupled to the chamber unit, and configured to exhaust gas in the chamber unit. The wafer lifting system is configured to receive and move the wafer in the chamber unit, and to provide a vertical distance between the heater and the wafer in the chamber unit | 07-16-2015 |
Chun-Sheng Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110205984 | Methods for Scheduling Channel Activities for Multiple Radio Access Technologies in a Communications Apparatus and Communications Apparatuses Utilizing the Same - An communications apparatus with multiple radio access technologies (RATs) is provided. A first RAT module transceives radio frequency (RF) signals in a first cellular network through the antenna. A second RAT module transceives RF signals in a second cellular network through the antenna. An arbiter receives a first and a second request from the first and second RAT module requesting permission to use the antenna for a first and a second channel activity, obtains a priority configuration for the first channel activity versus the second channel activity when the second channel activity collides with the first channel activity, and responds to one of the first and second RAT modules with an acknowledgement message and to the other of the first and second RAT modules with a rejection message based on the obtained priority configuration. | 08-25-2011 |
20110207453 | Methods for Coordinating Radio Activities in Different Radio Access Technologies and Apparatuses Utilizing the Same - An apparatus for coordinating radio activities in different radio access technologies (RATs) is provided. A first RAT module performs a first channel activity, related to a first RAT, for transmitting or receiving information to or from a first cellular network by using an antenna, and requests that a measurement activity, related to the first RAT, is to be performed for measuring signal power of a serving cell and/or at least one neighbor cell in the first cellular network by using the antenna. A second RAT module requests that a second channel activity, related to a second RAT, is to be performed for transmitting or receiving information to or from a second cellular network by using the antenna. An arbiter schedules performance of the measurement activity between the first and second channel activities. | 08-25-2011 |
20110207490 | Methods for Coordinating Radio Activities of Different Radio Access Technologies and Apparatuses Utilizing the Same - An apparatus for coordinating radio activities of different radio access technologies (RATs) includes a first RAT module, a second RAT module and an arbiter. The first RAT module receives and transmits radio frequency (RF) signals from and to a first cellular network through an antenna, and synchronizes transceiving timings with the first cellular network using a first clock. The second RAT module receives and transmits RF signals from and to a second cellular network through the antenna, and synchronizes transceiving timings with the second cellular network using a second clock. The arbiter coordinates a first radio activity requested by the first RAT module and a second radio activity requested by the second RAT module to avoid radio activity collision by using a third clock. | 08-25-2011 |
20120327790 | APPARATUSES AND METHODS FOR COORDINATING CIRCUIT SWITCHED (CS) SERVICES IN PACKET TRANSFER MODE (PTM) - A wireless communications device is provided with a baseband chip capable of coordinating operations between circuit-switched (CS) and packet-switched (PS) services with different subscriber identity cards. The baseband chip is configured to perform a packet switched (PS) data service associated with a second service network, sacrifice a portion of data transceiving from/to the second service network to monitor a channel associated with a first service network during the PS data service, so as to receive message from the first service network or maintain mobility in the first service network. | 12-27-2012 |
20130102340 | SURROUNDING CELL MONITORING METHOD - A surrounding cell monitoring method is applied in a mobile terminal wirelessly communicating with a first cell through a first target channel. The surrounding cell monitoring method includes the steps of: determining whether adjacent channel interference (ACI) of the target channel exists; determining whether a first power level of the adjacent channel is greater than a second power level of the target channel by a threshold difference when the ACI exists, when the ACI does exist; determining whether an adjacent BSIC of the adjacent channel can be decoded when the first power level is greater than the second power level by the threshold difference; and skipping an operation of decoding a target BSIC of the target channel when the adjacent BSIC of the adjacent channel can be decoded successfully. | 04-25-2013 |
Feng-Pin Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100156321 | Lamp Driving Device - A lamp driving device includes a DC power supply, a square wave switch, a square wave controller, a plurality of lamps, a starting transformer, and a common transformer; a plurality of starting transformers and a plurality of common transformers are disposed at both sides of the plurality of lamps respectively, the plurality of starting transformers and the plurality of common transformers can have their primary sides or secondary sides cascaded and connected to the square wave switch; the present invention can effectively control the output power to the lamps, reduce the size and the temperature of the device, and improve the overall efficiency by connecting the primary sides or secondary sides in series. | 06-24-2010 |
Hom-Ti Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120264181 | METHOD FOR PRODUCING BUTYRIC ACID, BUTANOL AND BUTYRATE ESTER - The present disclosure is directed to methods for producing butyric acid comprising fermenting a feedstock using a bacterium. The feedstock comprises lactic acid, or the feedstock comprises lactic acid and at least one carbohydrate. | 10-18-2012 |
20130150630 | METHOD FOR PREPARING PHENOLIC COMPOUNDS - In an embodiment of the disclosure, a method for preparing a phenolic compound is provided. The method includes providing a lignin depolymerization product, and hydrogenating the lignin depolymerization product under iron oxide and hydrogen gas to prepare a phenolic compound. The prepared phenolic compound is a crude phenolic composition including phenol, methylphenol, dimethylphenol or a combination thereof. | 06-13-2013 |
20140090640 | SUGAR PRODUCTS AND FABRICATION METHOD THEREOF - In an embodiment of the present disclosure, a sugar product and method for fabricating the same is provided. The method includes mixing an acid compound and lithium chloride, magnesium chloride, calcium chloride, zinc chloride or iron chloride or lithium bromide, magnesium bromide, calcium bromide, zinc bromide or iron bromide or heteropoly acid to form a mixing solution, adding a cellulosic biomass to the mixing solution for a dissolution reaction, and adding water to the mixing solution for a hydrolysis reaction to obtain a sugar product. The present disclosure also provides a sugar product fabricated from the method. | 04-03-2014 |
20140090641 | SUGAR PRODUCTS AND FABRICATION METHOD THEREOF - In an embodiment of the present disclosure, a method for fabricating a sugar product is provided. The method includes mixing formic acid and lithium chloride, magnesium chloride, calcium chloride, zinc chloride or iron chloride or lithium bromide, magnesium bromide, calcium bromide, zinc bromide or iron bromide or heteropoly acid to form a mixing solution, adding a cellulosic biomass to the mixing solution for a dissolution reaction, and adding water to the mixing solution for a hydrolysis reaction to obtain a sugar product. The present disclosure also provides a sugar product fabricated from the method. | 04-03-2014 |
20140106421 | Methods Of Producing Carboxylic Acids And/Or Alcohols - Carboxylic acids and/or alcohols are produced by a fermentation process comprising: growing an immobilized microorganism capable of producing carboxylic acids and/or alcohols in an aqueous medium and in the presence of an organic medium, and recovering the carboxylic acids and/or alcohols from the organic medium; wherein a mesh is placed at an interface of the organic medium and the aqueous medium; and further wherein the organic medium comprises at least one organic solvent and at least one extractant chosen from tri-alkylphosphine oxides and tri-alkylamines. | 04-17-2014 |
20140216442 | METHOD FOR PREPARING SUGARS - In an embodiment of the present disclosure, a method for preparing a sugar is provided. The method includes mixing an organic acid and a solid acid catalyst to form a mixing solution, adding a cellulosic biomass to the mixing solution to proceed to a dissolution reaction, and adding water to the mixing solution to proceed to a hydrolysis reaction to obtain a sugar. | 08-07-2014 |
20140261397 | METHOD OF SEPARATING CARBOHYDRATE - Disclosed is a method of separating carbohydrate, including: mixing formic acid with heteropoly acid, chloride or bromide of lithium, magnesium, calcium, zinc, or iron, or combinations thereof to form a mixing liquid. The method also includes dissolving a cellulose biomass by the mixing liquid to form a solution, mixing water and the solution to hydrolyze the cellulose biomass for forming a carbohydrate solution, and mixing an extractant and the carbohydrate solution to extract the formic acid out of the carbohydrate solution. The heteropoly acid, the chloride or bromide of lithium, magnesium, calcium, zinc, or iron, or combinations thereof in the carbohydrate solution is separated out of the carbohydrate solution by ion exclusion chromatography separation to obtain a carbohydrate. | 09-18-2014 |
Hsiao-Yi Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110133685 | CLASSIFIED SOLAR CHARGING METHOD - A classified solar charging method defines four magnitude classes of charging current in accordance with a combination selected from four magnitude classes of power production of a solar cell and four magnitude classes of capacity of each rechargeable battery of a rechargeable battery pack. In addition to the optimal charging current, the method simultaneously takes an operating temperature of the rechargeable battery into account upon using the solar cell to store energy in the rechargeable battery. Accordingly, the present invention can selectively charge overall, partial or single rechargeable battery based on the power production of the solar cell and the capacity of the rechargeable battery to enhance a charging efficiency and reduce a charging time. | 06-09-2011 |
20120287647 | ANTI-GLARE LENS AND TABLE LAMP WITH AN ANTI-GLARE LENS - A table lamp has a lamp stand, an adjusting arm, a lamp head and an anti-glare lens. The anti-glare lens is mounted on the lamp head and has a body. The body has a bottom, a light entering concave face, a light source region, a total reflection face and a light ejecting convex face. The bottom has a zero axis to divide the bottom equally. The light entering concave face is formed in the body. The light source region is formed in the body. The total reflection face is obliquely formed on and protrudes from the body and is formed with the bottom of the body. An angle between the zero axis and the total reflection face is between 90 and 180 degrees. The light ejecting convex face is formed on the body, is formed with the total reflection face and has at least one curvature. | 11-15-2012 |
Hsin-Chang Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140178804 | Stacked Mask - The present disclosure describes a mask. The mask includes a low thermal expansion material (LTEM) substrate, at least two absorber layers, and a spacer layer separating the two absorber layers. The first absorber layer is deposited over the LTEM substrate. The mask further includes a topcoat layer over the absorber layer. A thickness of the spacer layer is approximately equal to a height of a topography feature on a wafer substrate multiplied by the square of a demagnification of an objective lens. The absorber layers include staged patterns. | 06-26-2014 |
20140253898 | PELLICLE MOUNTING SYSTEM AND METHOD - A pellicle mounting method is provided. The method includes aligning a mounting apparatus with a top surface of a pellicle frame, the mounting apparatus having a continuous duct extending therethrough and a plurality of contact pins projecting from the mounting apparatus. The method also includes introducing a pressurizing fluid into the continuous duct that causes each of the plurality of contact pins to engage the top surface of the pellicle frame with a substantially equal force, a combined force of the plurality of contact pins urging a bottom surface of the pellicle frame against a top surface of a photomask, the combined force being adjustable based on a pressure within the continuous duct. Further, the method includes adjusting the pressure within the continuous duct until the pressure is approximately equal to a pre-determined optimal pressure. | 09-11-2014 |
20140272681 | Extreme Ultraviolet Light (EUV) Photomasks, and Fabrication Methods Thereof - Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarized process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber has a top portion wider than a bottom portion. | 09-18-2014 |
20140272683 | Method Of Fabricating Mask - A method for fabricating an extreme ultraviolet (EUV) mask includes providing a low thermal expansion material (LTEM) layer. A reflective multiple-layer (ML) is deposited over the LTEM layer. A flowable-photosensitive-absorption-layer (FPhAL) is spin coated over the reflective ML. The FPhAL is patterned by a lithography process to form a patterned absorption layer. | 09-18-2014 |
20140335446 | Systems and Methods for Lithography Masks - Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate Mo | 11-13-2014 |
20150104736 | REFLECTIVE MASK AND METHOD OF MAKING SAME - A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, a second absorption layer deposited inside the border ditch, and where the second absorption layer contacts the capping layer. In some instances, the border ditch crosses the capping layer and partially enters the reflective multilayer. | 04-16-2015 |
20150177612 | MASK AND METHOD FOR FORMING THE SAME - A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost. | 06-25-2015 |
20150205194 | Lithography Mask - The present disclosure provides a lithography mask comprising a substrate, a reflective multiplayer (ML) on the substrate, a barrier layer on the reflective ML, and an absorber layer over the barrier layer. In some embodiments, a thickness of the barrier layer is less than or equal to about 10 nm. In some embodiments, a portion of the absorber layer and a portion of the barrier layer are removed. The present disclosure also provides a method for fabricating a lithography mask, and a method for patterning a substrate using a lithography mask. | 07-23-2015 |
20150309401 | LITHOGRAPHY SYSTEM AND METHOD FOR PATTERNING PHOTORESIST LAYER ON EUV MASK - A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor. | 10-29-2015 |
20150309404 | PELLICLE STRUCTURE AND METHOD FOR FORMING THE SAME - A pellicle structure, a pellicle-mask structure, and a method for forming the pellicle structure are provided. The pellicle structure includes a pellicle film made of a carbon-based material. In addition, the pellicle film is configured to protect a mask structure in a lithography process. The pellicle-mask structure includes a mask substrate having a mask pattern formed over the mask substrate and the pellicle frame disposed on the mask substrate. The pellicle-mask structure further includes the pellicle film disposed on the pellicle frame. | 10-29-2015 |
20150331309 | RETICLE AND METHOD OF FABRICATING THE SAME - A reticle and a method of fabricating the reticle are provided. In various embodiments, the reticle includes a substrate, a patterned first attenuating layer, a patterned second attenuating layer, and a patterned third attenuating layer. The patterned first attenuating layer is disposed on the substrate. The patterned second attenuating layer is disposed on the patterned first attenuating layer. The patterned third attenuating layer is disposed on the patterned second attenuating layer. A first part of the patterned first attenuating layer, a first part of patterned second attenuating layer, and the patterned third attenuating layer are stacked on the substrate as a binary intensity mask portion. | 11-19-2015 |
20150371377 | METHOD AND SYSTEM FOR INSPECTION OF A PATTERNED STRUCTURE - A method and a system for inspection of a patterned structure are provided. In various embodiments, the method for inspection of a patterned structure includes transferring the patterned structure into a microscope. The method further includes acquiring a top-view image of the patterned structure by the microscope. The method further includes transferring the patterned structure out of the microscope and exporting the top-view image to an image analysis processor. The method further includes measuring a difference between a contour of the top-view image and a predetermined layout of the patterned structure by the image analysis processor. | 12-24-2015 |
Hsueh Yuan Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130011321 | EXHAUST GAS TREATMENT APPARATUS AND METHOD - An exhaust gas treatment apparatus comprises an ammonia absorption system and an ammonia conversion system. The ammonia absorption receives ammonia-containing tail gas generated by a semiconductor process, and removes dust from the tail gas, absorbs and decomposes ammonia gas from the tail gas, converts the ammonia gas into aqueous ammonia, and emits the tail gas without the dust and the ammonia to an external environment. The ammonia conversion system receives the ammonia solution from the ammonia absorption system, and converts it into gaseous ammonia, and then converts the gaseous ammonia to produce liquid ammonia by vaporization and cooling-pressurized liquefaction. After that, the liquid ammonia is purified by a purification system to formed hi-purity liquid ammonia. | 01-10-2013 |
Hung-Ta Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110154436 | Provider Management Methods and Systems for a Portable Device Running Android Platform - A provider management method conforming to an Android platform is provided. An authentication procedure is performed between a consumer and a provider, wherein the authentication procedure is performed via a binding unit, and the binding unit is an interface enabling inter-process communication conforming to the Android platform. | 06-23-2011 |
Jam-Wem Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100052059 | FINFET PROCESS COMPATIBLE NATIVE TRANSISTOR - Provided is a top-channel only finFET device. The methods and devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate. | 03-04-2010 |
20100103570 | Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection - Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit. | 04-29-2010 |
20100155776 | Forming ESD Diodes and BJTs Using FinFET Compatible Processes - A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT. | 06-24-2010 |
20100202184 | One-Time Programmable Fuse with Ultra Low Programming Current - A method of operating a FinFET fuse includes providing the FinFET fuse including a drain, a gate, a source, and a channel between the drain and the source; and applying a program voltage to one of the source and the drain of the FinFET fuse to cause a punch-through in the channel of the FinFET fuse. The method further includes determining a program state of the FinFET fuse. | 08-12-2010 |
20100296213 | ESD Protection for FinFETs - An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor. | 11-25-2010 |
20120037956 | Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection - Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit. | 02-16-2012 |
20120126329 | FINFET PROCESS COMPATIBLE NATIVE TRANSISTOR - Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate. | 05-24-2012 |
20120168906 | ESD Protection Device with Tunable Design Windows - An electrostatic discharge (ESD) device includes a high-voltage well (HVW) region of a first conductivity type; a first heavily doped region of a second conductivity type opposite the first conductivity type over the HVW region; and a doped region of the first conductivity type contacting the first heavily doped region and the HVW region. The doped region is under the first heavily doped region and over the HVW region. The doped region has a first impurity concentration higher than a second impurity concentration of the HVW region and lower than a third impurity concentration of the first heavily doped region. The ESD device further includes a second heavily doped region of the second conductivity type over the HVW region; and a third heavily doped region of the first conductivity type over and contacting the HVW region. | 07-05-2012 |
20120211869 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 08-23-2012 |
20130009204 | BIDIRECTIONAL DUAL-SCR CIRCUIT FOR ESD PROTECTION - An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal. | 01-10-2013 |
20130075854 | High Voltage ESD Protection Apparatus - An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus. | 03-28-2013 |
20130075863 | ESD Protection Apparatus - An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region. | 03-28-2013 |
20130083438 | ESD Protection for FinFETs - An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor. | 04-04-2013 |
20130093010 | High-Voltage Mosfets Having Current Diversion Region in Substrate Near Fieldplate - To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field plate can also help to reduce or “smooth” electric fields near the drain to help limit current crowding. In some embodiments, the current diversion region is a p-doped, n-doped, or intrinsic region that is at a floating voltage potential. This current diversion region can push current deeper into the substrate of the HV-MOSFET (relative to conventional HV-MOSFETs), thereby reducing current crowding during ESD events. By reducing current crowding, the current diversion region makes the HV-MOSFETs disclosed herein more impervious to ESD events and, therefore, more reliable in real-world applications. | 04-18-2013 |
20130093038 | Schottky Diode - An embodiment is a semiconductor structure. The semiconductor structure comprises a p-type region in a substrate; a first n-type well in the p-type region; a first p-type well in the p-type region; and a second p-type well in the first p-type well. A concentration of a p-type impurity in the first p-type well is less than a concentration of a p-type impurity in the second p-type well. Additional embodiments further comprise further n-type and p-type wells in the substrate. A method for forming a semiconductor structure is also disclosed. | 04-18-2013 |
20130277745 | ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE - An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type. | 10-24-2013 |
20130285112 | HIGH-TRIGGER CURRENT SCR - An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR. | 10-31-2013 |
20130285209 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 10-31-2013 |
20130307080 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 11-21-2013 |
20130334648 | Methods and Apparatus for High Voltage Diodes - High voltage diodes are disclosed. A semiconductor device is provided having a P well region; an N well region adjacent to the P well region and forming a p-n junction with the P well region; a P+ region forming an anode at the upper surface of the semiconductor substrate in the P well region; an N+ region forming a cathode at the upper surface of the semiconductor substrate in the N well region; and an isolation structure formed over the upper surface of the semiconductor substrate between the anode and the cathode and electrically isolating the anode and cathode including a first dielectric layer overlying a portion of the upper surface of the semiconductor substrate, and a second dielectric layer overlying a portion of the first dielectric layer and a portion of the upper surface of the semiconductor substrate. Methods for forming the devices are disclosed. | 12-19-2013 |
20130341676 | Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection - Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed. | 12-26-2013 |
20140035039 | ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE - An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type. | 02-06-2014 |
20140061848 | Schottky Isolated NMOS for Latch-Up Prevention - An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage. | 03-06-2014 |
20140062580 | Diode Formed of PMOSFET and Schottky Diodes - A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET. | 03-06-2014 |
20140094009 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 04-03-2014 |
20140131765 | ESD Devices Comprising Semiconductor Fins - A device includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. The device further includes a first node and a second node, and an Electro-Static Discharge (ESD) device coupled between the first node and the second node. The ESD device includes a semiconductor fin adjacent to and over a top surface of the insulation region. The ESD device is configured to, in response to an ESD transient on the first node, conduct a current from the first node to the second node. | 05-15-2014 |
20140145249 | Diode Structure Compatible with FinFET Process - An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process. | 05-29-2014 |
20140183518 | N-TYPE METAL OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR FOR ELECTROSTATIC DISCHARGE (ESD) - One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor. | 07-03-2014 |
20140183610 | Decoupling Capacitor for FinFET Compatible Process - A decoupling capacitor formed from a fin field-effect transistor (FinFET) and method of using the same are provided. An embodiment decoupling capacitor includes a fin field-effect transistor (FinFET) having a semiconductor substrate supporting a gate stack, a source, and a drain, a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail, and a second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail having a higher potential than the first power rail. | 07-03-2014 |
20140184277 | MULTI-GATE HIGH VOLTAGE DEVICE - A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors. | 07-03-2014 |
20140193959 | FinFET Body Contact and Method of Making Same - A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate. | 07-10-2014 |
20140217461 | BIDIRECTIONAL DUAL-SCR CIRTCUIT FOR ESD PROTECTION - An ESD protection circuit includes at least a first and a second silicon controlled rectifier (SCR) circuits. The first SCR circuit is coupled between the pad and the positive power supply terminal. The second SCR circuit is coupled between the pad and the ground terminal. At least one of the SCR circuits is configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal. | 08-07-2014 |
20140264604 | FinFET Having Source-Drain Sidewall Spacers with Reduced Heights - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. A gate stack is overlying a middle portion of the semiconductor fin. A fin spacer is on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height, wherein the first height is greater than about two times the second height. | 09-18-2014 |
20140367829 | ESD Protection Apparatus - An ESD protection apparatus comprises an n-type substrate with a first doping density, a low voltage n-type well in the substrate, a low voltage p-type well in the substrate, a first n-type semiconductor region over the low voltage n-type well and a second n-type semiconductor region over the low voltage p-type well, wherein the first semiconductor region and the second semiconductor region are separated by a first isolation region. | 12-18-2014 |
20140376133 | ESD PROTECTION CIRCUIT CELL - A device includes a first bidirectional PNP circuit coupled to a first output of an communication circuit, and a second bidirectional PNP circuit coupling to a second output of the communication circuit. The first and second bi-direction PNP circuits have coupled outputs and a first breakdown voltage. A third bidirectional PNP circuit is coupled to ground via the coupled outputs of the first bidirectional PNP circuit and of the second bidirectional PNP circuit. The third bidirectional PNP circuit has a second breakdown voltage. In some arrangements, a sum of the first breakdown voltage and the second breakdown voltage exceeds 60 volts. The communication circuit can be an automotive application circuit for a serial automotive communication application. The first and second bidirectional transistor circuits can form a part of a cell of an integrated circuit having an isolation structure to sustain high voltage. | 12-25-2014 |
20150069520 | Backside Contacts for Integrated Circuit Devices - A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region. | 03-12-2015 |
20150091066 | Double Sided NMOS/PMOS Structure and Methods of Forming the Same - A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric. | 04-02-2015 |
20150091092 | Dynamic Threshold MOS and Methods of Forming the Same - A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode. | 04-02-2015 |
20150097264 | DIODE STRING IMPLEMENTATION FOR ELECTROSTATIC DISCHARGE PROTECTION - A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional ( | 04-09-2015 |
20150115366 | CIRCULAR SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) DEVICE AND FUNCTIONAL DEVICE - One or more semiconductor devices with an electrostatic discharge (ESD) device and a functional device in a circular arrangement are provided herein. The semiconductor device comprises a first circular sector, a second circular sector, and at least two disconnect regions disposed between the first circular sector and the second circular sector. The first circular sector comprises at least one ESD device. The second circular sector comprises at least one functional device. A single semiconductor device having a circular arrangement or configuration thus has an ESD device and a functional device. | 04-30-2015 |
20150129971 | SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION - A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area. | 05-14-2015 |
20150130515 | Multi-Gate High Voltage Device - A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors. | 05-14-2015 |
20150137174 | Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection - Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed. | 05-21-2015 |
20150137264 | FinFET Body Contact and Method of Making Same - A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate. | 05-21-2015 |
20150187747 | CIRCUIT WITH INTER-LAYER VIAS AND INTRA-LAYER COUPLED TRANSISTORS - A circuit comprises a first layer comprising a first voltage line, a first transistor coupled with the first voltage line, a second transistor coupled with the first voltage line, and a first line coupling a drain of the first transistor with a gate of the second transistor. The circuit also comprises a second layer comprising a second voltage line, a third transistor coupled with the second voltage line, a fourth transistor coupled with the second voltage line, and a second line coupling a drain of the third transistor with a gate of the fourth transistor. The circuit further comprises an inter-layer interconnect structure coupling the first transistor with the third transistor, and the second transistor with the fourth transistor. | 07-02-2015 |
20150295088 | Diode Structure Compatible with FinFET Process - An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process. | 10-15-2015 |
20160027704 | Double Sided NMOS/PMOS Structure and Methods of Forming the Same - A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric. | 01-28-2016 |
Jiou-Kang Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110081740 | Low Stress Photo-Sensitive Resin with Sponge-Like Structure and Devices Manufactured Employing Same - System and method for forming a structure including a MEMS device structure. In order to prevent warpage of a substrate arising from curing process for a sacrificial material (such as a photoresist), and from subsequent high temperature process steps, an improved sacrificial material comprises (i) a polymer and (ii) a foaming agent or special function group. The structure can be formed by forming a trench in a substrate and filling the trench with a sacrificial material. The sacrificial material includes (i) a polymer and (ii) a foaming agent or special function group. After further process steps are completed, the sacrificial material is removed from the trench. | 04-07-2011 |
20110156245 | Method and Apparatus for Cooling an Integrated Circuit - An integrated circuit, a method of operating the integrated circuit, and a method of fabricating the integrated circuit are disclosed. According to one of the broader forms of the invention, a method and apparatus involve an integrated circuit that includes a heat transfer structure having a chamber that has a fluid disposed therein and that extends between a heat generating portion and a heat absorbing portion. Heat is absorbed into the fluid from the heat generating portion, and the fluid changes from a first phase to a second phase different from the first phase when the heat is absorbed. Heat is released from the fluid to the heat absorbing portion, and the fluid changes from the second phase to the first phase when the heat is released. | 06-30-2011 |
Jiunn-Yih Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150188697 | MULTIMEDIA INTERFACE RECEIVING CIRCUIT - A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal. | 07-02-2015 |
20150280761 | MULTI-LANE SERIAL LINK SIGNAL RECEIVING SYSTEM - A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal. | 10-01-2015 |
Kuang Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140043780 | HYBRID PORTABLE POWER SUPPLY - The present invention provides a hybrid portable power supply. In addition to providing emergency power to vehicles, the portable power supply of this invention integrates multiple functions, including lighting, warning, self-test and circuit protection. Moreover, the design of the power supply's housing is compact and aesthetically pleasing, making this power supply highly portable and easy for organizing cables. | 02-13-2014 |
Kun-Di Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110235444 | SRAM WRITING SYSTEM AND RELATED APPARATUS - SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal. | 09-29-2011 |
Lian Chun Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150149674 | EMBEDDED STORAGE DEVICE - An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus. | 05-28-2015 |
Li-Wei Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110012565 | CHARGING CIRCUIT WITH APPLICATION SYSTEM THEREOF - A charging circuit with an application system thereof provides an error amplifier to control a transistor switch for controlling the charging power source to charges the battery. When the voltage difference between the power source and load terminals of the transistor switch drops along with the transistor switch being turned on, the output voltage of the error amplifier changes as well to increase the turning-on resistance of the transistor switch such that the voltage difference between the power source and load terminals is capable of maintaining at a value above a certain reference level for avoiding the unstable state resulting from the charging circuit being turned on and off frequently. | 01-20-2011 |
Meng-Chang Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120086656 | Touch Sensing Circuit and Associated Method - A touch sensing circuit and method is provided. The touch sensing circuit discriminates a common voltage change of a display panel couple to the touch sensor in a touch panel display apparatus. The touch sensor comprises a plurality of sensor electrodes. The touch sensing circuit includes a plurality of channel circuits, each of which includes a reset switch and a sensing switch for alternately conducting an associated sensor electrode to a reset voltage and a charge collecting circuit. The channel circuits are divided to different groups that operate according to interleaving timings for encompassing possible common voltage changes. | 04-12-2012 |
Ming-Cheng Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130200445 | HVMOS TRANSISTOR STRUCTURE HAVING OFFSET DISTANCE AND METHOD FOR FABRICATING THE SAME - An HVMOS transistor structure includes: a first ion well of a first conductivity type and a second ion well of a second conductivity type different from the first conductivity type formed over a substrate, wherein the first ion well and the second ion well have a junction at their interface; a gate overlying the first ion well and the second ion well; a drain region of the first conductivity type, in the first ion well, spaced apart from a first sidewall of the gate by an offset distance; and a source region of the first conductivity type in the second ion well. In addition, a method for fabricating the HVMOS transistor structure described above is also provided. | 08-08-2013 |
Rong-Shen Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150097259 | CONDUCTIVE VIA STRUCTURE, PACKAGE STRUCTURE, AND PACKAGE OF PHOTOSENSITIVE DEVICE - Conductive plug structures suitable for stacked semiconductor device package is provided, wherein large contact region between the conductive plug structures and the corresponding pads of devices can be achieved, to reduce electrical impedance. Therefore, package structures such as photosensitive device packages using the conductive plug structures have superior electrical performance and reliability. | 04-09-2015 |
Song-Bor Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100130003 | Method of Forming Through-Silicon Vias - A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV. | 05-27-2010 |
20130154048 | Guard Ring for Through Vias - A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate. | 06-20-2013 |
20130207200 | INTEGRATED CIRCUIT HAVING THINNER GATE DIELECTRIC AND METHOD OF MAKING - An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different. | 08-15-2013 |
20140273508 | Wafer Back Side Processing Structure and Apparatus - Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms. | 09-18-2014 |
20140344770 | APPARATUS AND METHOD FOR DESIGNING AN INTEGRATED CIRCUIT LAYOUT HAVING A PLURALITY OF CELL TECHNOLOGIES - A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells. | 11-20-2014 |
20150020041 | METHOD AND SYSTEM FOR ENHANCED INTEGRATED CIRCUIT LAYOUT - An integrated circuit (IC) design method includes providing a design layout of the IC and placing a first cell and a second cell into the design layout. The second cell is a minor of the first cell. The method further includes dividing the first cell into a first plurality of segments and dividing the second cell into a second plurality of segments. A third cell is formed by connecting a first portion of the first plurality of segments with a first portion of the second plurality of segments. A fourth cell is formed by connecting a second portion of the first plurality of segments with a second portion of the second plurality of segments. The first, second, third and fourth cells each have substantially the same function. | 01-15-2015 |
20150357186 | Wafer Back Side Processing Structure and Apparatus - Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms. | 12-10-2015 |
20160005650 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate. | 01-07-2016 |
Te-Yu Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100252833 | THIN FILM TRANSISTOR DEVICES HAVING TRANSISTORS WITH DIFFERENT ELECTRICAL CHARACTERISTICS AND METHOD FOR FABRICATING THE SAME - A system for displaying images is provided. The system includes a thin film transistor (TFT) device comprising a substrate having a pixel region, a driving thin film transistor and a switching thin film transistor. The driving thin film transistor and the switching thin film transistor are disposed on the substrate and in the pixel region. The driving thin film transistor includes a polysilicon active layer and the switching thin film transistor includes an amorphous silicon active layer. A method for fabricating the system for displaying images including the TFT device is also disclosed. | 10-07-2010 |
20110284851 | SYSTEM FOR DISPLAYING IMAGES - A system for displaying images includes a multi-gate thin film transistor (TFT) device including an active layer, first and second gate structures, and first and second light-shielding layers. The active layer is disposed on a substrate in a pixel region. The first and second gate structures are disposed on the active layer. The first and second light-shielding layers are disposed between the substrate and the active layer. The active layer includes first and second source/drain regions and first and second channel regions. The first light-shielding layer corresponds to a first lightly doped region and laterally extends under at least a portion of the first channel region. The second light-shielding layer corresponds to the second lightly doped region and laterally extends under at least a portion of the second channel region. | 11-24-2011 |
Yea-Chen Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120104409 | FORMING LIGHT-EMITTING DIODES USING SEED PARTICLES - A seed layer for growing a group III-V semiconductor structure is embedded in a dielectric material on a carrier substrate. After the group III-V semiconductor structure is grown, the dielectric material is removed by wet etch to detach the carrier substrate. The group III-V semiconductor structure includes a thick gallium nitride layer of at least 100 microns or a light-emitting structure. | 05-03-2012 |
20130095581 | THICK WINDOW LAYER LED MANUFACTURE - A LED die and method for bonding, dicing, and forming the LED die are disclosed. In an example, the method includes forming a LED wafer, wherein the LED wafer includes a substrate and a plurality of epitaxial layers disposed over the substrate, wherein the plurality of epitaxial layers are configured to form a LED; bonding the LED wafer to a base-board to form a LED pair; and after bonding, dicing the LED pair, wherein the dicing includes simultaneously dicing the LED wafer and the base-board, thereby forming LED dies. | 04-18-2013 |
20130140592 | LIGHT EMITTING DIODE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY AND METHODS OF MANUFACTURING SAME - A light emitting diode structure and methods of manufacturing the same are disclosed. In an example, a light emitting diode structure includes a crystalline substrate having a thickness that is greater than or equal to about 250 μm, wherein the crystalline substrate has a first roughened surface and a second roughened surface, the second roughened surface being opposite the first roughened surface; a plurality of epitaxy layers disposed over the first roughened surface, the plurality of epitaxy layers being configured as a light emitting diode; and another substrate bonded to the crystalline substrate such that the plurality of epitaxy layers are disposed between the another substrate and the first roughened surface of the crystalline substrate. | 06-06-2013 |
20130187122 | PHOTONIC DEVICE HAVING EMBEDDED NANO-SCALE STRUCTURES - The present disclosure involves a method of fabricating a lighting apparatus. The method includes forming a first III-V group compound layer over a substrate. The first III-V group compound layer has a first type of conductivity. A multiple quantum well (MQW) layer is formed over the first III-V group compound layer. A second III-V group compound layer is then formed over the MQW layer. The second III-V group compound layer has a second type of conductivity different from the first type of conductivity. Thereafter, a plurality of conductive components is formed over the second III-V group compound layer. A light-reflective layer is then formed over the second III-V group compound layer and over the conductive components. The conductive components each have better adhesive and electrical conduction properties than the light-reflective layer. | 07-25-2013 |
20140021483 | Forming Light-Emitting Diodes Using Seed Particles - A seed layer for growing a group | 01-23-2014 |
20160035933 | THICK WINDOW LAYER LED MANUFACTURE - A LED die and method for bonding, dicing, and forming the LED die are disclosed. In an example, the method includes forming a LED wafer, wherein the LED wafer includes a substrate and a plurality of epitaxial layers disposed over the substrate, wherein the plurality of epitaxial layers are configured to form a LED; bonding the LED wafer to a base-board to form a LED pair; and after bonding, dicing the LED pair, wherein the dicing includes simultaneously dicing the LED wafer and the base-board, thereby forming LED dies. | 02-04-2016 |
Yen-Lin Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20160055031 | Dual-System Architecture With Fast Recover And Switching Of Operating System - Examples of a dual-system architecture capable of fast switching between the operating systems are provided. A first operating system may perform one or more operations associated with an apparatus as an active operating system of the apparatus. The active operating system may be switched from the first operating system to a second operating system for the second operating system to perform a task responsive to a determination that the second operating system is required to perform the task. | 02-25-2016 |
Yi-Ting Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20160063172 | Connectivity-Aware Layout Data Reduction For Design Verification - Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers. | 03-03-2016 |
Yi-Tsang Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110263187 | WIRE SAW AND METHOD FOR FABRICATING THE SAME - The present invention relates to a wire saw and a method for fabricating the same. The method for fabricating a wire saw according to the present invention includes: providing a core wire; coating an intermediate layer over the core wire, and embedding a plurality of abrasives in the intermediate layer; and plating a metal protective layer over the abrasives. Accordingly, the present invention can resolve the conventional problem of abrasives in the plating bath aggregating during electroplating deposition, so as to enhance cutting quality and precision. | 10-27-2011 |
Yu-Chun Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140361323 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A LED package structure includes a base portion, a light-emitting chip, a cup portion and an encapsulating glue. The base portion has an upper surface and a lower surface. The upper surface has a die-bonding area. The light-emitting chip emits a light with a first wavelength and is located on the die-bonding area. The cup portion is located on the base portion to surround the die-bonding area to form a recess having an opening. The encapsulating glue is filled into the recess. The encapsulating glue has a wavelength conversion material configured to convert part of the light with the first wavelength into a light with a second wavelength. The cup portion includes an electro chromic layer electrically connected to a first external power and a transmittance of the electro chromic layer is changed in accordance with an input voltage of the first external power to adjust the light-emitting profile of the light-emitting chip. | 12-11-2014 |
20150077996 | HEAT SINK FOR ELECTRICAL ELEMENTS AND LIGHT-EMITTING DEVICE CONTAINING THEREOF - The disclosure provides a heat sink for electrical elements and a light-emitting device containing thereof. The heat sink includes a radiating substrate and at least one hollow radiating channel. In which, the hollow radiating channel is horizontally embedded in the radiating substrate, and has two openings disposed on the same site or the opposite sites of the radiating substrate, so that gas may flow in the hollow radiating channel and remove heat of the radiating substrate. And a light-emitting device containing the heat sink is also provided. | 03-19-2015 |
Yueh-Ting Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140361846 | COMMUNICATION DEVICE AND CONTROL METHOD THEREOF - A communication device is provided in the present invention. The communication device comprises an oscillation signal source, a tunable capacitor array, a frame counter; and a control module. The control module is configured to jointly or separately control the tunable capacitor array and the frame counter to compensate a first frequency offset of the oscillation signal source when the communication device operates in a first mode, and to jointly or separately control the tunable capacitor array and the frame counter to compensate a second frequency offset of the oscillation signal source when the communication device operates in a second mode. | 12-11-2014 |
Yuhwen Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130105289 | INTERNAL STACK-UP STRUCTURE OF TOUCH PANEL AND METHOD FOR PRODUCING THE SAME | 05-02-2013 |
Yuh-Wen Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110279403 | CAPACITIVE TOUCH PANEL AND A METHOD OF REDUCING THE VISIBILITY OF METAL CONDUCTORS IN CAPACITIVE TOUCH PANEL - The present invention discloses a capacitive touch panel, comprises a substantially transparent substrate and a transparent sensing pattern. The transparent sensing pattern, which detects touch signals, is formed on the substantially transparent substrate. The transparent sensing pattern comprises a plurality of conductor cells and at least one metal conductor disposed on the substantially transparent substrate. The at least one metal conductor connects two adjacent conductor cells. At least one low-reflection layer is formed on the at least one metal conductor. The low-reflection layer can reduce the reflected light therefore reducing the visibility of the metal conductors. | 11-17-2011 |
20130069890 | TOUCH DISPLAY DEVICE AND A METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a touch display device and a method of manufacturing the same. The touch display device comprises a touch panel, a display module and a first adhesive layer formed by an ultraviolet-curing liquid adhesive, wherein the first adhesive layer laminates the touch panel and the display module. The touch display device further comprises of a lens and a second adhesive layer, wherein the second adhesive layer laminates the touch substrate layer and the lens. The present disclosure overcomes shading effect by curing the first adhesive layer and the second adhesive layer by adjusting the order of laminating the display module with the touch substrate and the lens so as to improve yield of lamination between the touch panel and the display module. | 03-21-2013 |
20130306451 | TOUCH PANEL AND MANUFACTURING METHOD THEREOF - A touch panel includes a strengthen cover lens and a touch electrode layer. The strengthen cover lens includes a first non-planar sulfate, and is planned with a display region and a peripheral region surrounding the display region. The touch electrode layer is formed, on the first non-planar surface and overlaid on the display region and at least part of the peripheral region for manufacturing a non-planar touch panel. | 11-21-2013 |
20140125597 | TOUCH PANEL AND A MANUFACTURING METHOD THEREOF - A touch panel is provided in the present disclosure, comprising: a sensing patterned layer, comprising a plurality of first sensing electrode units not in contact with each other along first axis; and a bridging line, electrically connected with the adjacent first sensing electrode units along the first axis; wherein the bridging line are made by at least a metallic layer and a conductive oxidized layer. By this way the touch panel lowers light reflection, thereby reducing flashes and bright-spots on the touch panel and improving appearance of the touch panel. | 05-08-2014 |
20140130548 | METHOD OF MANUFACTURING A TOUCH PANEL - The present disclosure relates to a method of manufacturing a touch panel, and more particularly, to a manufacturing method capable of strengthening the strength of the touch panel. The method comprises: sinking and then strengthening a glass substrate, and then conducting a manufacturing process of placing a sensing electrode array. Finally, the glass substrate is cut and produced into several touch panels, each having strengthening properties. | 05-15-2014 |
20140267945 | TOUCH PANEL AND METHOD FOR MANUFACTURING - The present disclosure relates to a touch panel, and more particularly, to a touch panel having no or a reduced number of frames. The touch panel includes a substrate, a plurality of first electrodes, and second electrodes, wherein the first electrodes and the second electrodes are disposed on two opposite sides of the substrate, respectively. The first electrodes extend along an initial direction from initial positions and divert from the initial direction to terminate in first termination positions. The second electrodes extend from second initial positions and terminate in second termination positions along a second direction. | 09-18-2014 |
Yu Lin Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150201474 | Lighting Device - A lighting device is provided. The lighting device includes a switch-mode power supply module, an electronic ballast power supply module, a first single-pole double-throw switch, a second single-pole double-throw switch, a third single-pole double-throw switch, a fourth single-pole double-throw switch, and a direct-current driven lighting module. The lighting device is connected with the ballast, one input of the ballast is connected to an AC power supply. The switch-mode power supply module and the electronic ballast power supply module are used to convert AC into DC. The common end of four single-pole double-throw switch is connected with the ballast. When the ballast is an inductive ballast, the common end of four single-pole double-throw switch is connected to the input of the switch-mode power supply module. When the ballast is the electronic ballast, the common end of four single-pole double-throw switch is connected to the output of the electronic ballast power modules. | 07-16-2015 |
Yung-Pin Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140296734 | PHYSIOLOGY SIGNAL SENSING DEVICE - A physiology signal sensing device includes an elastic pad and a strain sensor clement. The elastic pad is used for contact with a human body, and corresponds a blood vessel of the human body. The strain sensor element is disposed in the elastic pad and includes a conductive element. The conductive element deforms according to the vibration of the blood vessel, and the resistance value of the conductive element varies according to the strain of the conductive element. | 10-02-2014 |
Yung-Yao Lee, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120231395 | ITERATIVE RINSE FOR SEMICONDUCTOR FABRICATION - An iterative rinse for fabrication of semiconductor devices is described. The iterative rinse includes a plurality of rinse cycles, wherein each of the plurality of rinse cycles has a different resistivity. The plurality of rinse cycles may include a first rinse of a semiconductor substrate with de-ionized (DI) water and carbon dioxide (CO | 09-13-2012 |
20130108775 | DEFECT MONITORING FOR RESIST LAYER | 05-02-2013 |
20130201462 | METHOD OF DETERMINING OVERLAY ERROR AND CONTROL SYSTEM FOR DYNAMIC CONTROL OF RETICLE POSITION - A method of determining overlay error. The method includes transferring a pattern from a reticle to a wafer and selecting a first set of data points to measure the positional difference between features on the reticle and features on the wafer. The method also includes determining a second set of data points characteristic of the first set of data points but containing fewer data points. A control system for using the second set of data points to dynamically adjust the position of the reticle. | 08-08-2013 |
20130286395 | Tool Induced Shift Reduction Determination for Overlay Metrology - One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements. | 10-31-2013 |
20140017604 | LITHOGRAPHY PROCESS - A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer. | 01-16-2014 |
20140240703 | Overlay Sampling Methodology - One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface. | 08-28-2014 |
20140240706 | OVERLAY SAMPLING METHODOLOGY - A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies. | 08-28-2014 |
20150016943 | Lithographic Overlay Sampling - Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure. | 01-15-2015 |
20150116686 | EDGE-DOMINANT ALIGNMENT METHOD IN EXPOSURE SCANNER SYSTEM - An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone. | 04-30-2015 |
20160025650 | OVERLAY METROLOGY METHOD AND OVERLAY CONTROL METHOD AND SYSTEM - The present disclosure provides an overlay metrology method, an overlay control method and an overlay control system. The overlay metrology method includes capturing a current layer image of a current overlay mark on a current layer with a current focal length and capturing a previous layer image of a previous overlay mark on a previous layer with a previous focal length. Then, the overlay metrology method further includes combining the current layer image with the previous layer image to form an overlay mark image and determining an overlay error between the current overlay mark and the previous overlay mark based on the overlay mark image. | 01-28-2016 |
20160033878 | OVERLAY SAMPLING METHODOLOGY - One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface. | 02-04-2016 |