Patent application number | Description | Published |
20110094779 | CIRCUIT STRUCTURE - A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer. | 04-28-2011 |
20110100543 | MANUFACTURING METHOD OF CIRCUIT STRUCTURE - A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern. | 05-05-2011 |
20110155427 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer. | 06-30-2011 |
20120015304 | METHOD FOR FABRICATING AN INTERPOSER - Method for fabricating an interposer is provided. A substrate is provided having thereon at least a conductive via and at least a flange. The flange is bonded on the substrate and shades a portion of the via. A photoresist layer is formed on the interior surface of the via, on a contact surface of the flange and on an inner surface of the flange opposite to the contact surface. An opening is formed in the photoresist layer to expose a portion of the contact surface of the flange, while the photoresist layer still covers the interior surface of the via and the inner surface of the flange. A plating layer is formed on the exposed contact surface of the flange. The photoresist layer is then removed. | 01-19-2012 |
20120024584 | CONNECTOR AND MANUFACTURING METHOD THEREOF - A method of manufacturing a connector is provided. Firstly, a substrate having a first surface, a second surface opposite to the first surface and a through hole is provided. Next, a first conductive layer covering the inside wall of the through hole is formed on the substrate. Then, a filler is filled in the through hole to form a filler post. Next, a conductive elastic cantilever is formed over the first surface and electrically connected to the first conductive layer. Then, a gold layer is formed on the conductive elastic cantilever and over the first surface. A solder ball electrically connected to the first conductive layer is formed over the second surface. | 02-02-2012 |
20120031651 | CIRCUIT BOARD - A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material. | 02-09-2012 |
20120031652 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer. | 02-09-2012 |
20130327564 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed. | 12-12-2013 |
20140099432 | FABRICATION METHOD FOR FLEXIBLE CIRCUIT BOARD - A fabrication method for a flexible circuit board is provided. The fabrication method includes the following steps. Firstly, a release film having an upper surface and a lower surface opposite to each other is provided. Next, two flexible substrates are respectively disposed on the upper surface and the lower surface. Next, a plurality of nano-scale micro-pores are formed on each flexible substrate to form two non-smooth flexible substrates. The nano-scale micro-pores evenly distributed over an outer surface of each non-smooth flexible substrate. Each non-smooth flexible substrate being adapted to be performed a plating process directly on the outer surface thereof. | 04-10-2014 |
Patent application number | Description | Published |
20110011737 | HIGH-POWER PULSE MAGNETRON SPUTTERING APPARATUS AND SURFACE TREATMENT APPARATUS USING THE SAME - A magnetron sputtering apparatus suitable for coating on a workpiece is provided. The magnetron sputtering apparatus includes a vacuum chamber, a holder, a magnetron plasma source and a high-power pulse power supply set, wherein the magnetron plasma source includes a base, a magnetron controller and a target. A reactive gas is inputted into the vacuum chamber, and the holder supporting the workpiece is disposed inside the vacuum chamber. The magnetron plasma source is disposed opposite to the workpiece, wherein the magnetron controller is disposed in the base, and the target is disposed on the base. The high-power pulse power supply set is coupled to the vacuum chamber, the magnetron plasma source and the holder, and a high voltage pulse power is inputted to the magnetron plasma source to generate plasma to coat a film on the surface of the workpiece. | 01-20-2011 |
20110192348 | RF Hollow Cathode Plasma Generator - An RF hollow cathode plasma source consists of a vacuum chamber, a pipe, a hollow cathode, at least two compartments, a conduit and input electrodes. The pipe is inserted into the chamber for introducing working gas into the chamber. The hollow cathode is disposed in the chamber and formed with a large number of apertures. At least two compartments are located below the hollow cathode. Each of the compartments includes small apertures for uniformly spreading the working gas into the apertures of the hollow cathode. The conduit is disposed along two sides of the hollow cathode to circulate cooling water around the hollow cathode. The plural input power leads are arranged near the hollow cathode. The input power leads, the pipe and the conduits are connected to the hollow cathode though the electrically-insulated walls of the grounded vacuum chamber. | 08-11-2011 |
Patent application number | Description | Published |
20100099007 | Fuel cell assembly structure - A fuel cell assembly structure mainly comprises a housing in which there is an accommodating space; a plurality of unit cell stacks that are stacked in the same direction in the accommodating space of the housing and made by stacking in sequence a cathode layer, a power generation electrode, an anode layer and a connection disk; a connection disk connecting is series each unit cell stack, a sealing disk and a cover in sequence to cover the opening of the accommodating space of the housing. On the outer side of the cover there is a connection base, at least one surface of which has a plurality of conduits and the other end connects to a plurality of cell stack bypass manifolds that further connect to a plurality of side bypass manifolds. | 04-22-2010 |
20110097646 | Porous-Medium Burning Apparatus - A burning device is provided for fuel cell to be run under high temperature. The burning device uses a specific-designed fuel spraying device having porous medium. The burning device can be used under different statuses of flow in the fuel cell. With the burning device, the fuel cell has improved efficiency by enhancing recycling of system heat and pollution of discharged waste gas is reduced. | 04-28-2011 |
20120276467 | SOLID OXIDE FUEL CELL STACK MODULAR STRUCTURE - The present invention relates to a solid oxide fuel cell stack modular structure, in that, being an integration of a plurality of fuel cell modules, it can determine the amount of fuel cell modules to be stacked in the modular structure according to an actual power output demand while ensuring airtightness in the modular structure, and moreover, with the modularization design, each fuel cell module in the modular structure that is malfunctioning can be detached and removed easily from the stack individually so as to be replaced by another operative fuel cell module. | 11-01-2012 |
20140116048 | Multi-Functional Solar Combined Heat and Power System - A solar combined heat and power system is provided. The system is multi-functional. Saturated steam and organic vapor are provided to steam and organic Rankine cycle power generators by concentrating solar radiation to solar power thermal energy storage container. Thermoelectric generator chips and solar cells are run at an optimum temperature for generating extra power. A hot water storage tank is used to generate hot water by absorbing latent heat on condense process or by absorbing surplus heat from water or organic fluid when power generators stop. Thus, the present invention improves solar energy usage effectiveness, and provides heat and power with high efficiency. | 05-01-2014 |
Patent application number | Description | Published |
20100148977 | LOCALIZATION AND DETECTION SYSTEM APPLYING SENSORS AND METHOD THEREOF - In embodiments of the invention, multiple sensors, which are complementary, are used in localization and mapping. Besides, in detecting and tracking dynamic object, the sense results of sensing the dynamic object by the multiple sensors are cross-compared, to detect the location of the dynamic object and to track the dynamic object. | 06-17-2010 |
20100164807 | SYSTEM AND METHOD FOR ESTIMATING STATE OF CARRIER - A system and a method for estimating a state of a carrier are provided. The system includes the carrier, an electromagnetic wave sensing device, a motion sensing device, and a controller. The electromagnetic wave sensing device detects an electromagnetic wave emitted by at least one feature object in an environment around the carrier. The motion sensing device detects motion information of the carrier moving in the environment. The controller estimates state information of the carrier in the environment through a probabilistic algorithm according to the electromagnetic wave and motion information detected by aforementioned sensing devices. Thereby, in the present invention, the location and posture of the carrier in the environment can be precisely estimated according to the motion information of the carrier and existing information of the environment around the same. | 07-01-2010 |
20100250020 | SPACE SENSOR APPARATUS, MOBILE CARRIER, AND CONTROL METHOD THEREOF - A space sensor apparatus suitable for a mobile carrier is provided. The space sensor apparatus includes a posture angle calculation module, a position calculation module, and a processing system. The posture angle calculation module calculates the current posture angles of the mobile carrier corresponding to different direction axes in a space according to signals input by one or multiple sensors. The position calculation module calculates the current position of the mobile carrier in the space according to the posture angles and an acceleration parameter and outputs a positioning information to the processing system. The processing system further obtains an environment information through a mechanical wave transceiver. After that, the processing system generates a real-time calculation information for controlling the movement track of the mobile carrier in the space according to the positioning information and the environment information. | 09-30-2010 |
20130054130 | NAVIGATION SYSTEM, METHOD OF POSITION ESTIMATION AND METHOD OF PROVIDING NAVIGATION INFORMATION - A hybrid-computing navigation system worn by a user includes a modified motion sensor group which includes 9-axis or 10-axis motion sensors that are built-in, and a host device configured for providing navigation information, in which the modified motion sensor group is worn on the user so that a moving direction of the user is the same as a heading direction calculated from the modified motion sensor group. The modified motion sensor group provides step counting and absolute orientation in yaw, roll and pitch using a sensor fusion technique. The navigation system further includes at least one wireless sensor at wifi hot spot to perform sensor fusion for obtaining an absolute position of an estimated position of the user. Sensor fusion combining with location map are used to perform location map matching and fingerprinting. A method of position estimation of a user using the navigation system is also disclosed. | 02-28-2013 |
20130162525 | METHOD AND APPARATUS FOR PERFORMING MOTION RECOGNITION USING MOTION SENSOR FUSION, AND ASSOCIATED COMPUTER PROGRAM PRODUCT - A method and apparatus for performing motion recognition using motion sensor fusion and an associated computer program product are provided, where the method is applied to an electronic device. The method includes the steps of: utilizing a plurality of motion sensors of the electronic device to obtain sensor data respectively corresponding to the plurality of motion sensors, the sensor data measured at a device coordinate system of the electronic device, wherein the plurality of motion sensors includes inertial motion sensors; and performing sensor fusion according to the sensor data by converting at least one portion of the sensor data and derivatives of the sensor data into converted data based on a global coordinate system of a user of the electronic device, to perform motion recognition based on the global coordinate system, in order to recognize the user's motion. | 06-27-2013 |
20130176218 | Pointing Device, Operating Method Thereof and Relative Multimedia Interactive System - An operating method of a display device includes detecting resolution of a display module for determining a border of a user interface reference frame, setting a border of a 3D spatial reference frame utilized by a pointing device to correspond to the border detected of the user interface reference frame, moving a cursor of the user interface reference frame displayed on the display module according to a shift of the pointing device, stopping controlling a shift of the cursor according to the shift of the pointing device when the shift of the pointing device exceeds the border of the 3D spatial reference frame, and resuming controlling the shift of the cursor in the user interface reference frame of the display module when the pointing device is back within the border of the 3D spatial reference frame. An advantage of the present invention is when out of the operating range, stopping controlling the cursor to lower the affect of offset, for allowing the pointing device to be applied in different areas/directions without having the cursor displayed on the display device to incorrectly reflect shift of the pointing device. | 07-11-2013 |
20130178226 | Method of Positioning Using Wireless Signals and Inertial Measurement Units, Electronic Device, and Positioning System Using the Same Method - A method of positioning using wireless signals and an inertial measurement unit is provided. The method includes the following steps: providing a wireless signal strength data base, wherein the wireless signal strength database gathers a radio map and a plurality of wireless signal strength information corresponding to a plurality of orientations at all grid positions on the radio map; using the inertial measurement unit to detect a current orientation at a current position where the electronic device is located; detecting a current wireless signal strength information of the electronic device corresponding to the current orientation at the current position; and determining the current position according to the current orientation, the current wireless signal strength information, and the wireless signal strength data base. | 07-11-2013 |
20130184991 | Method of Generating Geometric Heading and Positioning System Using the Same Method - A method of generating a geometric heading during positioning is provided. The method includes the following steps: estimating a current declination information of a current position according to a declination database, wherein the declination database gathers a magnetic map and a plurality of declination information corresponding to a difference between a magnetic north and a geometric north at all grid positions on the magnetic map; generating a predicted heading according to an angular velocity reading of a gyroscope and a magnetic heading reading of a magnetometer; and generating the geometric heading according to the current declination information of the current position and the predicted heading. | 07-18-2013 |
20130234940 | Pointing Device, Operating Method Thereof and Relative Multimedia Interactive System - An operating method of a display device includes controlling a shift of a cursor of a user interface reference frame according to a shift of the pointing device with reference to an initial point in a 3D spatial reference frame; and updating a position of the initial point in the 3D spatial reference frame according to an updating signal. An advantage of the present invention is when the operating range is changed, reference coordinates utilized by the pointing device are appropriately adjusted, so as to lower the affect of offset, allowing the pointing device to be applied in different areas/directions without having the cursor displayed on the display device to incorrectly reflect shift of the pointing device. | 09-12-2013 |
20140337651 | Electronic Apparatus - An electronic apparatus including a plurality of sensors, an application processor, and a micro-processor is provided. The plurality of sensors is configured to generate at least one sensing signal. The application processor is configured to execute an application procedure according to a sensing-merged signal. The micro-processor is coupled between the plurality of sensors and the application processor, and is configured to generate the sensing-merged signal according to the at least one sensing signal. By utilizing the electronic apparatus, not only power can be saved, but also the elasticity for choosing sensor chip vendors can be improved. | 11-13-2014 |
Patent application number | Description | Published |
20080296725 | SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME - A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate. | 12-04-2008 |
20090146101 | ETCHANT FOR METAL ALLOY HAVING HAFNIUM AND MOLYBDENUM - An etchant for etching a metal alloy having hafnium and molybdenum includes 20 to 80 percent by weight of nitric acid, 1 to 49 percent by weight of hydrofluoric acid, 1 to 96 percent by weight of sulfuric acid, and 1 to 30 percent by weight of water, based on the total weight of the etchant. | 06-11-2009 |
20090166703 | MEMORY DEVICE WITH A LENGTH-CONTROLLABLE CHANNEL - A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain. | 07-02-2009 |
20110101448 | VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical transistor includes: a substrate, a bottom-oxide layer, an epitaxial silicon layer, an insulating oxide layer, two gate-oxide films and a gate-stacked layer. The bottom-oxide layer is disposed on the substrate, and the bottom-oxide layer has a gate recess concavely formed thereof. The substrate has a first doped area in an upper part corresponding to the gate recess. The epitaxial silicon layer is formed on the gate recess, and the epitaxial silicon layer has a second doped area in an upper part. The insulating oxide layer is disposed on the epitaxial silicon layer. The gate-oxide films are respectively formed on two opposite sides of the epitaxial silicon layer. The gate-stacked layer is formed on the two gate-oxide layers and the bottom-oxide layer. Whereby, the lateral area of transistor is reduced, and the integration and the performance of the device are improved. | 05-05-2011 |
20110133248 | VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure. | 06-09-2011 |
20110156285 | INTEGRATED ALIGNMENT AND OVERLAY MARK, AND METHOD FOR DETECTING ERRORS OF EXPOSED POSITIONS THEREOF - An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process. | 06-30-2011 |
20110226736 | METHOD OF PATTERNING METAL ALLOY MATERIAL LAYER HAVING HAFNIUM AND MOLYBDENUM - A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed. | 09-22-2011 |
20120313157 | DRAM CELL HAVING BURIED BIT LINE AND MANUFACTURING METHOD THEREOF - A dram cell having buried bit line includes a substrate having fin structures thereon, a plurality of deep trenches in the substrate, a buried stripe, a plurality of word lines formed on the substrate and a plurality of capacitors formed on the fin structures. Each of the deep trenches is arranged between two adjacent fin structures. Each of the deep trenches has a metal layer and a poly-silicon layer thereinside to define a buried bit line. The buried stripe is formed in the substrate and next to each of the deep trenches. The bit line is electrically connected to the corresponding fin structure via the buried stripe. The word lines are alternatively arranged with the bit lines, and each of the word lines are disposed cross on the fin structures to construct double gate structures. | 12-13-2012 |
20140117442 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source. | 05-01-2014 |
20140124844 | SEMICONDUCTOR LAYOUT STRUCTURE - A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction. | 05-08-2014 |
20140252550 | STACK CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a stack capacitor structure and a manufacturing method thereof, adapted for a random access memory. The stack capacitor structure is formed on a semiconductor substrate. The stack capacitor structure includes an oxide layer and a circular-shaped stopping layer. The oxide layer is disposed on the semiconductor substrate. The oxide layer has a capacitor trench therein. The circular-shaped stopping layer surrounds an edge of an opening of the capacitor trench. The disclosed stack capacitor structure and the manufacturing method thereof may thereby prevent the occurrence of the stack capacitor structure from having CD variation and belly region causing cell to cell leakage as result of manufacturing process limitation. | 09-11-2014 |
20140291729 | MEMORY UNIT, MEMORY UNIT ARRAY AND METHOD OF MANUFACTURING THE SAME - A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region. | 10-02-2014 |
20140291738 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines. | 10-02-2014 |
Patent application number | Description | Published |
20090119099 | System and method for automobile noise suppression - A system and a method for automobile noise suppression in an automobile are provided. The system comprises a processor and a noise suppression device. The noise suppression device is configured for receiving a voice signal, which includes a speech signal and a noise signal. The processor is configured for determining an adjusting parameter set according to an automobile speed signal corresponding to a speed of the automobile. The noise suppression device can suppress the noise signal according to the adjusting parameter set, whereby enhancing the voice quality. | 05-07-2009 |
20140219475 | APPARATUS AND METHOD OF MULTI-SENSOR SOUND RECORDING - An apparatus and a method for sound recording are provided. The apparatus stores an equalizer and includes a housing, a microphone, and a processor. The microphone includes a plurality of sensors and receives a sound signal through an acoustical resonator in the housing. The microphone generates a plurality of electronic signals in response to the sound signal. The equalizer generates a plurality of equalized signals according to the electronic signals. The processor generates an output signal according to the equalized signals. The equalizer compensates the gain margin and the phase margin caused by the sound signal passing through the acoustical resonator in order to prevent the output signal from being affected by resonance of the sound signal in the acoustical resonator. | 08-07-2014 |
20140233761 | ELECTRONIC DEVICE AND GAIN CONTROLLING METHOD - An electronic device and a corresponding gain controlling method are provided. The gain controlling method includes the steps of receiving a sound signal, calculating a sound level according to each value of the sound signal in a past period, determining a gain value according to the sound level, using the gain value to amplify the sound signal, and then storing the sound signal. | 08-21-2014 |
20140348336 | ELECTRONIC APPARATUS AND METHOD FOR ACTIVATING SPECIFIED FUNCTION THEREOF - An electronic apparatus and a method for activating a specified function are provided. The electronic apparatus includes a speaker, an audio signal processor and an application processor. The audio signal processor senses a variation of an acoustic condition of the speaker. The application processor is used for: generating a logic high or low signal in response to the sensed variation of the acoustic condition; interpreting the logic high or low signal as a control signal; and performing an instruction corresponding to the control signal. | 11-27-2014 |
Patent application number | Description | Published |
20080266278 | COLOR CHOLESTERIC LIQUID CRYSTAL DISPLAY DEVICES AND DRIVING METHODS THEREOF - Color cholesteric liquid crystal display devices and driving methods thereof are provided. A color cholesteric liquid crystal display device includes a color cholesteric liquid crystal display panel with a plurality of sub-pixels. A driving module exerts a first voltage on a portion of sub-pixels of the color cholesteric liquid crystal display panel to hold displaying states of the biased sub-pixels. An input element exerts pressure on the color cholesteric liquid crystal display panel to change displaying states of the unbiased sub-pixels. | 10-30-2008 |
20090244442 | COLOR CHOLESTERIC LIQUID CRYSTAL DISPLAY DEVICES AND FABRICATION METHODS THEREOF - Single-layered color cholesteric liquid crystal display devices and fabrication methods thereof are provided. The color cholesteric liquid crystal display device includes a first substrate structure having a base and periodic protrusion banks. A second substrate structure is disposed opposite the first substrate structure to enclose the periodic protrusion banks, and divide a plurality of color sub-pixel channels. A plurality of color cholesteric liquid crystals are respectfully filled in each of the color sub-pixel channel, wherein the base and the periodic protrusion banks are made of continuously integral material. | 10-01-2009 |
20100225611 | ELECTROWETTING DISPLAY DEVICES - Electrowetting display devices are provided. The electrowetting display includes a first substrate and an opposing second substrate with a polar fluid layer and a non-polar fluid layer interposed between the first and second substrates. A first electrode is disposed on the first substrate. A second electrode is disposed on the second substrate. A hydrophilic bank structure is disposed on the first substrate, and a reflective layer is disposed on the second substrate, wherein the first substrate of the electrowetting display serves as a display face. | 09-09-2010 |
20110013103 | DISPLAY SYSTEMS HAVING ELECTRICALLY INDEPENDENT REGIONS - A display system including a first set of conductive electrodes, a second set of conductive electrodes, and a display medium. The first set of conductive electrodes is configured to receive a selection signal. The second set of conductive electrodes is configured to interact with the first set of conductive electrodes for activating the reading or writing of display data. The second set of conductive electrodes is configured to receive a data signal and to activate the reading or writing of a target area of the display device, in response to the selection signal to the first set of conductive electrodes and the data signal to the second set of conductive electrodes. The display medium is movably coupled with the first and second sets of conductive electrodes. One or both of the first and the second sets of conductive electrodes have at least two electrically independent regions having an independent signal input for each region. | 01-20-2011 |
20110176077 | DRIVING METHODS FOR CHOLESTERIC LIQUID CRYSTAL DISPLAY DEVICES - Driving methods for cholesteric liquid crystal display devices are provided. The driving method includes providing a cholesteric liquid crystal display, wherein the capacitance detector corresponds to a driving module; outputting a capacitance sensing voltage waveform from the driving module to the cholesteric liquid crystal display panel such that a capacitance value of the cholesteric liquid crystal layer is acquired and stored in the memory; and when the capacitance value falls in a capacitance range of a second displaying state, the capacitance detector outputs a second sensing result, and when the capacitance value falls in a capacitance range of a first displaying state, the capacitance detector outputs a first sensing result. | 07-21-2011 |
20120218176 | DISPLAY SYSTEMS HAVING ELECTRICALLY INDEPENDENT REGIONS - A display system including a first set of conductive electrodes, a second set of conductive electrodes, and a display medium. The first set of conductive electrodes is configured to receive a selection signal. The second set of conductive electrodes is configured to interact with the first set of conductive electrodes for activating the reading or writing of display data. The second set of conductive electrodes is configured to receive a data signal and to activate the reading or writing of a target area of the display device, in response to the selection signal to the first set of conductive electrodes and the data signal to the second set of conductive electrodes. The display medium is movably coupled with the first and second sets of conductive electrodes. One or both of the first and the second sets of conductive electrodes have at least two electrically independent regions having an independent signal input for each region. | 08-30-2012 |
Patent application number | Description | Published |
20100302178 | TOUCH PANEL DISPLAY - A touch panel display including a first substrate, a second substrate, a display medium and a touch device is provided. The first substrate has a display area and a peripheral area. The first substrate has a pixel array in the display area and at least one integrated driving circuit in the peripheral area. The integrated driving circuit is electrically connected to the pixel array. The second substrate is disposed above the first substrate to cover the integrated driving circuit and the pixel array. The display medium is disposed on the pixel array and located between the first substrate and the second substrate. The touch device is disposed on the second substrate, and has a sensor element and a wiring element connected to the sensor element. The sensor element is located above the pixel array and the wiring element is located above at least a portion of the integrated driving circuit. | 12-02-2010 |
20110102310 | SHIFT REGISTER WITH IMAGE RETENTION RELEASE AND METHOD FOR IMAGE RETENTION RELEASE - A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high. | 05-05-2011 |
20130120328 | DISPLAY PANEL - A liquid crystal display panel including a first substrate, an active device array, a gate driver on array (GOA), at least one signal transmission connection pad, a second substrate, an opposite electrode layer, conduction devices, and a display medium is provided. The active device array includes scan lines, data lines, and active devices. The GOA is electrically connected to the scan lines. The signal transmission connection pads are located respectively at a first side of the active device array and a second side of the active device array. The first side and the second side are corresponding to two opposite ends of the scan lines, respectively. The conduction devices and the display medium are disposed between the first substrate and the second substrate. The signal transmission connection pads are electrically connected to the opposite electrode layer through the conduction devices. | 05-16-2013 |
20130215063 | TOUCH PANEL DISPLAY - A touch panel display including a first substrate, a second substrate, a display medium and a touch device is provided. The first substrate has a display area and a peripheral area. The first substrate has a pixel array in the display area and at least one integrated driving circuit in the peripheral area. The integrated driving circuit is electrically connected to the pixel array. The second substrate is disposed above the first substrate to cover the integrated driving circuit and the pixel array. The display medium is disposed on the pixel array and located between the first substrate and the second substrate. The touch device is disposed on the second substrate, and has a sensor element and a wiring element connected to the sensor element. The sensor element is located above the pixel array and the wiring element is located above at least a portion of the integrated driving circuit. | 08-22-2013 |
Patent application number | Description | Published |
20080232200 | Method of Generating a Digital Photo Slide Show from an Optical Disc - Before generating a digital photo slide show, both original digital photos and related media playing packages are burnt into a same optical disc. While the optical disc is loaded by a disc playing device, a media playing module installed on the optical disc playing device loads both the original digital photos and the related media packages on the optical disc, and generates a required digital photo slide show according to digital photos and media playing packages, both of which are chosen by a user, for preventing the problem of causing damage of resolution of the digital photos by repeatedly encoding said digital photos, and for management and reuse of said digital photos on the optical disc hereafter. | 09-25-2008 |
20080232212 | Method of Dynamically Updating Media Play Effects Utilized on a Digital Photo Slide Show - Before playing a digital photo slide show, both required digital photos and a guiding program are burnt on an optical disc in advance. While the disc is loaded into an optical disc play device, the guiding program triggers the optical disc play device to connect with an external network for updating media play effect packages, which are related to the digital photos, and for storing the updated media play effect packages in a preserved database of said optical disc play device. Then a corresponding digital photo slide show is dynamically generated and played according to both the updated media play effect packages, which are stored in the preserved database, and the digital photos burnt on the optical disc. | 09-25-2008 |
20130129303 | SYSTEMS AND METHODS FOR TRANSMISSION OF MEDIA CONTENT - A method provide a selection option to the at least one portable device, the selection option relating to selection of the first audio content and retrieving a selection from the at least one portable device based on the selection option. The method further retrieves a selection of the second audio content and synchronizing the first audio content, the second audio content, and the video content by embedding a synchronizing signal in the first audio content, the second audio content, and the video content. The method further outputs the second audio content and the video content to an output device according to the synchronizing signal. Responsive to the selection of the first audio content, the first audio content with the embedded synchronizing signal is transmitted to the least one portable device, wherein the at least one portable device outputs the first audio content according to the synchronizing signal. | 05-23-2013 |
Patent application number | Description | Published |
20100101338 | SAMPLING PIPE - A sampling pipe suitable for sampling materials in a channel is disclosed. The sampling pipe includes a hollow body and a plurality of openings. The hollow body has a plurality of sampling sections, and these sampling sections are suitable for being disposed in the channel. The openings penetrate through the outer wall of the hollow body and locate in the sampling sections. Wherein, there is at least one opening in each sampling section, and flux of materials flowing into each sampling section is the same. | 04-29-2010 |
20120060696 | AIR FILTERING SYSTEM CAPABLE OF ENHANCING INSPECTION CONVENIENCE - The present invention relates to an air filtering system capable of enhancing inspection convenience, which is disposed in the ceiling and comprises a housing, a filter, a first sampling tube, and a second sampling tube. On both ends of the housing, an intake and an outtake are disposed opposite to each other. The filter is disposed in the housing, and has an intake surface and an outtake surface opposite to each other. The filter divides the inner space of the housing into a first sampling zone and a second sampling zone. A first end of the first sampling tube is fixed on the housing, and communicates with the first sampling zone. Likewise, a first end of the second sampling tube is fixed on the housing, and communicates with the second sampling zone. Besides, a second end of the first sampling tube and a second end of the second sampling tube are both fixed on the wall. Thereby, the inspection convenience for the inspection staffs can be enhanced. | 03-15-2012 |
20130185850 | PROTECTIVE CLOTHING WITH VENTILATION EFFECT - A protective clothing with ventilation effect is revealed. The protective clothing includes an airproof protection portion and a plurality of ventilation portions. A periphery of each ventilation portion is connected to the airproof protection portion. Each ventilation portion includes a filter material. Heat and moisture inside the protective clothing can be removed by air flowing in and out through the ventilation portions while wearing the protective clothing. Thus uncomfortable feeling is reduced and working efficiency is improved. As to the filter material of the ventilation portion, it is used to filter while air flowing. Thus the protective clothing still provides users high-level protection beside the ventilation effect. | 07-25-2013 |
Patent application number | Description | Published |
20090068373 | Novel synergistic process and recipe for fabrication of a high integrity membrane electrode assembly of solid oxide fuel cell - A recipe and two sequential processes for fabrication of electrode substrates of solid oxide fuel cells (SOFCs) are described in this invention. The typical recipe consists of 50˜86 wt % electrolyte (8YSZ) or 50˜80 wt % anode electrode (NiO/8YSZ), 12˜22 wt % MEK (solvent 1), 5˜9 wt % EtOH (solvent 2), 1˜2 wt % TEA (dispersant), 0.5˜2 wt % DBP (plasticizer 1), 0.5˜2 wt % PEG (plasticizer 2), 3˜6 wt % PVB (binder), and 0.1˜10 wt % graphite (pore former). Two sequential processes include: 1. The process for preparation of the green tape slurry from materials of the recipe, 2. The synergistic process for fabrication of a high integrity membrane electrode assembly (MEA) of SOFC from the prepared electrode substrates. | 03-12-2009 |
20090151850 | Process for fabrication of a fully dense electrolyte layer embedded in membrane electrolyte assembly of solid oxide fuel cell - This invention describes the process for fabrication of a fully dense electrolyte layer (8YSZ/GDC/LSGM) embedded in a high performance membrane electrolyte assembly (MEA) (Unit Cell) of Solid Oxide Fuel Cell. An air-tight electrolyte layer (8YSZ/GDC/LSGM) is mainly prepared via tape casting technique and modified by thin film technologies, such as sputtering coating, spin coating, plasma spray/Coating etc., as well as combined with the sintering scheme and operation control. The gas permeability of electrolyte layer is less than 1×10 | 06-18-2009 |
20090166186 | Novel process for fabrication of a sputter deposited fully dense electrolyte layer embedded in a high performance membrane electrolyte assembly of solid oxide fuel cell - The innovation process describes the process and results for fabrication of a magnetron sputter deposited fully dense electrolyte layer (8YSZ/GDC/LSGM) embedded in a high performance membrane electrolyte assembly (MEA) (Unit Cell) of Solid Oxide Fuel Cell. A single cell with airtight electrolyte layer (8YSZ/GDC/LSGM) is prepared via thin film technique of magnetron sputter deposition, combined with SOFC-MEA processing methods (such as tape casting, lamination, vacuum hot pressing, screen printing, spin coating, and plasma spray coating) and sintering optimization conditions. The gas permeability of the electrolyte layer is below 1×10 | 07-02-2009 |
20090166907 | Innovation process for anode treatment of solid oxide fuel cell - membrane electrode assembly to upgrade power density in performance test - This invention describes the process for fabrication of a high conductivity and low resistance solid oxide fuel cell. An anode substrate is mainly prepared via tape casting technique and modified by abrasion and polish process. Electrolyte is fabricated onto the polished side by thin film technologies and can attach well in the cross section. Grinding surface of anode side about 10-30 μm after finish of MEA combination can get a high conductivity and low resistance unit cell and enhance cell performance effectively. | 07-02-2009 |
20090166908 | Innovation control process for specific porosity/gas permeability of electrode layers of SOFC-MEA through combination of sintering and pore former scheme and technology - An innovation scheme and technology used for controlling porosity/gas permeability of electrode layers of SOFC-MEA through combination of pore former and sintering manipulations. The porosity of electrode layer is 0-35 vol. %, and the gas permeability of electrode layer is 1×10 | 07-02-2009 |
20100018036 | Formulation of nano-scale electrolyte suspensions and its application process for fabrication of solid oxide fuel cell-membrane electrode assembly (SOFC-MEA) - This invention describes the recipe and preparation process of nano-scale electrolyte suspension and its application via a spin coating process for fabrication of airtight/fully dense electrolyte layers composed in solid oxide fuel cell-membrane electrode assembly with high performance characteristics. The recipe of nano-scale electrolyte suspension includes 10˜50 wt % nano-scale electrolyte powder, 0.01˜1 wt % poly acrylic acid (PAA as dispersant), 0.1˜5 wt % poly vinyl alcohol (PVA as binder), 0.005˜1 wt % octanol as defoamer, and deionized water as solvent. Solid oxide fuel cell fabricated via this recipe and process exhibits that the open-circuit voltage (OCV) is over 1 Volt, and maximum power density is 335 mW/cm | 01-28-2010 |
20110130267 | Process to Produce Fine Ceramic Powder through a Chemical Reactor with Powder Collection Device - The present invention is related to producing fine nano or submicron-scale precision ceramic powder by applying an innovative chemical reactor with powder collection to the glycine-nitrate combustion process (GNC-P). The unique feature lies in the utilization of a simple-operating process to massively produce nano or submicron-scale ceramic oxide powder with multiple metal components. The present invention not only provides very high powder collection efficiency and production yield as well as safety but also satisfies requirements of industrial safety and environmental safety, and lowers production cost. | 06-02-2011 |
20110221450 | MEASUREMENT PROCESS FOR DETERMINATION OF THE OPTIMUM CONTACT PRESSURE AMONG COMPONENTS OF A SOLID OXIDE FUEL CELL STACK IN THE PACKAGING PROCESS AND ITS MEASUREMENT APPARATUS - The present invention provides a measurement process for determination of the optimum contact pressure among components of a solid oxide fuel cell stack in the packaging process in order that the reduction in performance caused by the packaging process can be reduced. The present invention also provides a measurement apparatus which can carry the measurement process out. | 09-15-2011 |
20120115067 | PROCESS AND APPARATUS OF CO2 ENERGY SOURCE ADOPTED IN SOLID OXIDE FUEL CELL - CO2 ENERGY CONVERSION CYCLE - A process and apparatus of “Solid Oxide Fuel Cell (SOFC)-CO | 05-10-2012 |
20130230791 | Current collection apparatus and method of processing for a solid oxide fuel cell thereof - A current collection apparatus and its method of processing for a solid oxide fuel cell, which mainly includes using screen printing process to print conductive adhesive onto the surface of the electrode of solid oxide fuel cell (SOFC), forming a current collection layer with drying process, using an appropriate amount of conductive adhesive to paste a conductive wire onto the current collection layer, forming an adhesion layer through drying, fixing the conductive wire on the electrode surface with an appropriate amount of ceramic adhesive, and forming a fixing layer after baking. A good connection is hence made between metal conductive wire and electrode through current collection layer, not only the interface impedance between electrode and current collection layer can be reduced effectively, but also the output power density of the SOFC unit cell can be enhanced, and stable as well as long term power output can be provided. | 09-05-2013 |
Patent application number | Description | Published |
20090206487 | WIRE BONDING SUBSTRATE AND FABRICATION THEREOF - A method for forming a wire bonding substrate is disclosed. A substrate comprising a first surface and a second surface is provided. A through hole is formed in the substrate. A conductive layer is formed on the first surface and the second surface of the substrate and covers a sidewall of the through hole. The conductive layer on the first surface of the substrate is patterned to form at least a first conductive pad, and the conductive layer on the second surface of the substrate is patterned to form at least a second conductive pad. An insulating layer is formed on the first surface and the second surface of the substrate and covers the first conductive pad and the second conductive pad. The insulating layer is recessed until top surfaces of the first conductive pad and the second conductive pad are exposed. A first metal layer is electroplated on the first conductive pad by applying current from the second conductive pad to the first conductive pad through the conductive layer passing the through hole. | 08-20-2009 |
20090283315 | HIGH DENSITY PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - The invention provides a high density package substrate and a method for fabricating the same. A double-sided copper clad laminate containing an upper copper foil and a lower copper foil is provided. A bottom pad is disposed on the lower copper foil, aligned to a predetermined position of a through hole. The through hole is formed by laser drilling through the upper copper foil and the substrate, but not through the bottom pad. A seed layer is formed conformally lining the through hole, and a metal layer is formed on the seed layer by plating to form a plated through hole (PTH). | 11-19-2009 |
20110253440 | SUPPORTING SUBSTRATE AND METHOD FOR FABRICATING THE SAME - The invention provides a supporting substrate and method for fabricating the same. The supporting substrate includes: a substrate; a first surface metal layer formed on the substrate, wherein the first surface metal layer has a first opening; a second surface metal layer formed on the substrate and disposed oppositely to the first surface metal layer, wherein the substrate has a through hole, and the through hole is formed along the first opening to expose the second surface metal layer; a protective layer formed on the first surface metal layer and the second surface metal layer, wherein the protective layer has a second opening which exposes the through hole; and a conductive bump formed in the through hole, the first opening and the second opening, wherein the conductive bump is electrically connected to the second surface metal layer. | 10-20-2011 |
Patent application number | Description | Published |
20090072973 | PHYSICAL AUDIT SYSTEM WITH RADIO FREQUENCY IDENTIFICATION AND METHOD THEREOF - The present invention relates to a physical audit system with radio frequency identification (RFID) and a method thereof, which perform physical audit by means of RFID. First, a plurality of electronic tags is set in a physical system and all the physical units included in the physical system, respectively. The plurality of electronic tags records physical configuration data related to the physical system and the physical units, respectively. A radio-frequency writer unit writes the physical configuration data of a newer version according to the physical system and the physical units. Then, a radio-frequency reader unit reads the physical configuration data of the plurality of electronic tags, and transmits the physical configuration data to an integrated data processing device for analyzing and comparing the physical configuration data. It is judged if the physical configuration is identical to comparison data in the integrated data processing device. | 03-19-2009 |
20090140040 | ANTI-FAKE IDENTIFICATION SYSTEM AND METHOD CAPABLE OF AUTOMATICALLY CONNECTING TO WEB ADDRESS - This invention relates to an anti-fake identification system and method capable of automatically connecting to web address, in which an electronic tag of commodity is scanned by a reader device so as to read the identification code into the computer device; the identification code includes a web address of a remote maker to which the computer can automatically connect so as to transmit the identification code to the web address; a verifying device receives and verifies the identification code at the web address, and produce an authentication code according to the identification code after the identification code passes through verification so as to confirm the accuracy of the identification code. The method comprises the following steps of: reading an identification code of commodity; transmitting the identification code to the web address; verifying the identification code and generating an authentication code when the identification code is accurate. When the identification code is verified to be accurate according to the authentication code, the computer can keep consumer informed that the commodity passing through anti-fake verification is genuine, and that the user's manual and service information of the commodity can be understood. | 06-04-2009 |
20120075115 | System and Method for Measuring Polar Substances - A system for measuring polar substances includes a measurement module, a transfer module, a display module and a store module. The measurement module includes a measurement unit and a transmitter. The measurement unit measures the polar substances and produces a data-related signal. The transmitter transmits the data-related signal. The transfer module includes a receiver and a transmitter. The receiver receives the data-related signal. The transmitter of the transfer module receives the data-related signal from the receiver and transmits the data-related signal. The display module receives the data-related signal from the transmitter of the transfer module and shows the data-related signal. The store module receives the data-related signal from the transmitter of the transfer module and stores the data-related signal. | 03-29-2012 |
20130049964 | Electronic Seal Equipped with a Breakage-Detecting Circuit and Method for Sealing a Door Based on the Same - Disclosed is an electronic seal for sealing a door. The door is equipped with a latch. The electronic seal includes a plug and a socket. The plug can be inserted in the socket through the latch. Thus, the door is sealed by the electronic seal. The door cannot be opened without breaking the electric seal. The electronic seal records any event of breakage. | 02-28-2013 |
20130051283 | Full-Duplex Wireless Voice Broadcasting Apparatus with Channel-Changing and Interference-Resistance - The present disclosure is a full-duplex wireless voice broadcasting apparatus. The apparatus is capable of channel-changing. Full-duplex (two-way) voice communication is achieved by using at least one receiving device and an emitting device. The receiving device has good mobility to be used as an emergent caller to the emitting device. The present disclosure has advantages in interference resistance, energy saving, short-distance emergent calling, and calling for help. | 02-28-2013 |
Patent application number | Description | Published |
20110026742 | METHOD OF FABRICATING INTEGRATED SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF - A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process. | 02-03-2011 |
20120037989 | LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME - LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region. | 02-16-2012 |
20120270350 | SEMICONDUCTOR BIO-SENSORS AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening. | 10-25-2012 |
20130037914 | NOVEL STRUCTURE OF NPN-BJT FOR IMPROVING PUNCH THROUGH BETWEEN COLLECTOR AND EMITTER - A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode. | 02-14-2013 |
20130056825 | MOS DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 03-07-2013 |
20130285136 | Schottky diode with enhanced breakdown voltage - An apparatus of and method for making enhanced Schottky diodes having p-body regions operable to pinch a current flow path in a high-voltage n-well region and field plate structures operable to distribute an electric potential of the Schottky diode allow for a device with enhanced breakdown voltage properties. N-well regions implanted into the substrate over a p-type epitaxial layer may act as an anode of the Schottky diode and n-type well regions implanted in the high-voltage n-well regions may act as cathodes of the Schottky diode. The Schottky diode may also be used as a low-side mosfet structure device. | 10-31-2013 |
20140264599 | SEMICONDUCTOR DEVICE HAVING REDUCED LEAKAGE CURRENT AT BREAKDOWN AND METHOD OF FABRICATING THEREOF - A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n− (HVN−) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n− well and a source n− well disposed in the HVN− doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN− ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle. | 09-18-2014 |
20140264855 | SEMICONDUCTOR COMPOSITE LAYER STRUCTURE AND SEMICONDUCTOR PACKAGING STRUCTURE HAVING THE SAME THEREOF - A semiconductor composite layer structure disposed on a substrate having an electronic circuit structure and a first conductive layer is disclosed. The semiconductor composite layer structure comprises a plurality of dielectric layers, a first wetting layer, a stiff layer and a second wetting layer. The dielectric layers are disposed on the substrate separately. The first wetting layer is disposed on the dielectric layer and the substrate between the dielectric layers. The stiff layer is disposed on the first wetting layer. The second wetting layer is disposed on stiff layer, for contacting with a second conductive layer. | 09-18-2014 |
20140302654 | MOS device and method of manufacturing the same - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 10-09-2014 |
20150044808 | METHOD OF FABRICATING INTEGRATED SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF - A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process. | 02-12-2015 |
Patent application number | Description | Published |
20080277141 | CIRCUIT BOARD AND METHOD OF FABRICATING THE SAME - A circuit board including a dielectric layer, a circuit layer, at least one conductive joint column, and a solder mask layer is provided. The circuit layer having at least one pad is in contact with the dielectric layer. The conductive joint column is disposed on the pad. The solder mask layer is disposed on the dielectric layer and covers the circuit layer. The solder mask layer is in contact with the conductive joint column, and the conductive joint column penetrates the solder mask layer. A height of the conductive joint column is larger than a thickness of the solder mask layer. The enhanced reliability of bonding between another component and the conductive joint column will be provided. Further, a method of fabricating a circuit board is also provided. | 11-13-2008 |
20090025210 | CIRCUIT BOARD STRUCTURE WITH CONCAVE CONDUCTIVE CYLINDERS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a circuit board structure with concave conductive cylinders is provided. Firstly, a conductive layer is provided; a plurality of conductive cylinders are formed on a surface of the conductive layer; a dielectric layer is formed on the surface of the conductive layer with the conductive cylinders; the tips of the conductive cylinders are exposed on a surface of the dielectric layer far away from the conductive layer; removing the exposed tips of the conductive cylinders such that the height of the conductive cylinders is lower than the height of the dielectric layer, and the conductive cylinders sunk into the dielectric layer. | 01-29-2009 |
20090117262 | METHOD OF FABRICATING CIRCUIT BOARD - A method of fabricating a circuit board includes the following steps. First, a patterned metal board is provided. The patterned metal board includes a patterned circuit having at least a pad. Next, a dielectric layer is formed on the patterned metal board to cover the patterned circuit. Thereafter, a processing treatment is preformed on a surface of the patterned metal board in which the surface is opposite to the patterned circuit, such that at least a conductive joint column disposed on the pad and a circuit layer having the patterned circuit are formed. Afterwards, a solder mask layer is formed on the dielectric layer to cover the circuit layer, such that the solder mask layer is in contact with the conductive joint column, the conductive joint column passes through the solder mask layer, and a height of the conductive joint column exceeds a thickness of the solder mask layer. | 05-07-2009 |
20100101083 | METHOD FOR FABRICATING CIRCUIT BOARD STRUCTURE WITH CONCAVE CONDUCTIVE CYLINDERS - A method of fabricating a circuit board structure with concave conductive cylinders is provided. Firstly, a conductive layer is provided and a dielectric layer is formed on a surface of the conductive layer. Next, a plurality of vias is formed in the dielectric layer, where the vias are exposed on the surface of the conductive layer. A conductive material is then filled in the vias to form a plurality of conductive cylinders on the surface of the conductive layer, so that the tips of the conductive cylinders are exposed on a surface of the dielectric layer relatively far away from the conductive layer. The exposed tips of the conductive cylinders are removed, so that the height of the conductive cylinders is lower than the dielectric layer and the conductive cylinders sunk into the dielectric layer. | 04-29-2010 |
20120124830 | PROCESS FOR FABRICATING CIRCUIT BOARD - A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad. | 05-24-2012 |
Patent application number | Description | Published |
20090155169 | Glyco-molecular imaging method for grade classification of liver fibrosis and its glyco-molecular imaging agent thereof - The invention discloses one glyco-molecular imaging method for grade classification of liver fibrosis and its glyco-molecular imaging agent. The agent combining with glyco-molecular imaging method for liver targeting could be used to differentiate the grade of liver fibrosis and follow-up evaluation of the therapeutic effect. | 06-18-2009 |
20120115178 | Method of Diagnosing Gastric Cancer by Using Human Neutrophil Peptide 1-3 - Human neutrophil peptide (HNP) 1-3, used as diagnostic and therapeutic molecular probes, are found in clinical tissues of gastric cancer patients. In the analytical process according to the present disclosure, pairs of gastric cancer tissues are used to seek the putative biomarkers by proteomic strategy based on matrix assisted laser desorption ionization-imaging mass spectrometry (MALDI-IMS). Then, three differential biomarkers, including HNP-1, -2 and -3, are identified (P<0.001) and overexpressed in gastric cancer. At last, western blotting and immunohistochemistry are used to validate the protein expression in gastric cancer tissues. In conclusion, the use of the up-regulated proteins, HNP1-3, helps diagnosis and therapy in clinical for gastric cancer after validating the sensitivity and specificity. | 05-10-2012 |
20120207675 | Method of Colorectal Cancer Detection by Using Radiolabeled Anti-GRP78 Peptide - The present disclosure describes techniques used for colorectal cancer detection. Position and distribution of colorectal cancer tumor are detected through nuclear imaging. Alternatively, stage of colorectal cancer is identified by shading value in tumor. Thus, the present disclosure provides a safe and noninvasive clinical method for diagnosing and tracing level and distribution of colorectal cancer before and after treatment. | 08-16-2012 |
20120288442 | Nuclear Imaging Method Using Molecular Target Detection Agent for Liver Fibrosis - A method for diagnosing liver fibrosis is provided. A monoclonal antibody and an antagonist of cannabinoid receptor in liver fibrosis cell are labeled. The monoclonal antibody or the antagonist is injected for nuclear imaging. Thus, through the image obtained through the nuclear imaging, liver fibrosis is diagnosed and traced in clinic use for preventive medicine. | 11-15-2012 |
20130109580 | High-Affinity Peptide Probes for Tumor Biomarker, GRP-78, and Screening Method Thereof | 05-02-2013 |
Patent application number | Description | Published |
20100216232 | MAMMAL DEDICATED CELL LINE - A mammal dedicated cell line is provided, which is a HepG2 hepatocellular carcinoma cell line (HepG2/NF-kB/Luc/sr39tk)1_18 obtained by co-transformation with NF-kB/Luc and NF-kB/sr39tk. Firstly, a successfully transformed pNF-kB/Luc HepG2 cell is obtained. Then, a dedicated cell line sensitive to TPA and MTX is generated by experimental screening Next, a plasmid construct carrying pNF-kB/sr39tk genome is introduced into the dedicated cell line by means of Superfect protocol. Finally, a HepG2 cell line co-expressing NF-kB/Luc and NF-kB/sr39tk is screened with G418 and ZEOCIN, and transformation result is confirmed by luminescence and radio activity. The (HepG2/NF-kB/Luc/sr39tk)1_18 obtained is suitable to screen drug for treating liver cancer and examine these cells by bioluminescence imaging and nuclear medicine imaging. | 08-26-2010 |
20110097263 | KIT FORMULATION FOR THE PREPARATION OF IMMUNOLIPOSOME DRUG IN COMBINED BIMODALITY RADIOCHEMOTHERAPY - A kit formulation for the preparation of immunoliposome drug in combined chemotherapy and radionuclide therapy is disclosed, which consists: (1) a vial A containing proteins; (2) a vial B containing Traut's reagent; (3) a vial C containing DSPC, Cholesterol, mPEG-DSPE, Mal-DSPE-PEG and chemotherapy drug; (4) a vial D containing BMEDA, gluconate acetate, SnCl | 04-28-2011 |
20120295349 | MAMMAL DEDICATED CELL LINE FROM HUMAN HEPATOCELLULAR CARCINOMA CELL - A mammal dedicated cell line is provided, which is a HepG2 hepatocellular carcinoma cell line (HepG2/NF-kB/Luc/sr39tk)1_18 obtained by co-transformation with NF-kB/Luc and NF-kB/sr39tk. Firstly, a successfully transformed pNF-kB/Luc HepG2 cell is obtained. Then, a dedicated cell line sensitive to TPA and MTX is generated by experimental screening Next, a plasmid construct carrying pNF-kB/sr39tk genome is introduced into the dedicated cell line by means of Superfect protocol. Finally, a HepG2 cell line co-expressing NF-kB/Luc and NF-kB/sr39tk is screened with G418 and ZEOCIN, and transformation result is confirmed by luminescence and radio activity. The (HepG2/NF-kB/Luc/sr39tk)1_18 obtained is suitable to screen drug for treating liver cancer and examine these cells by bioluminescence imaging and nuclear medicine imaging. | 11-22-2012 |
20130172532 | METHOD FOR MAKING RHENIUM-186/188 LABELED HUMAN SERUM ALBUMIN MICROSPHERES AND KIT FOR MAKING THE SAME AND METHOD FOR USING THE KIT - The present invention relates to a method for preparing | 07-04-2013 |
20140377169 | Automated synthesis device to produce Re-188-Liposome and method thereof - An automated synthesis device to produce Re-188-BMEDA solution including: a plurality of reagent vials, three-way solenoid valves, gel filtration columns and micro pumps, and a reaction vial, a product vial, a temporary storage vial, a filter membrane, and a waste vial, wherein the plurality of reagent vials include first reagent vial and second reagent vials being connected to the reaction vial through first micro pump, the third reagent vial and fourth reagent vial being connected to the reaction vial through second micro pump, fifth reagent vial being connected to the reaction vial through third micro pump, and sixth reagent vial being connected to the temporary storage vial through fourth micro pump, wherein the reaction vial is connected to the plurality of gel filtration columns through the micro-pump, respectively. The automated synthesis device is operable with program to upgrade yield and avoid contamination. | 12-25-2014 |
20150033828 | Automated test apparatus for testing risk and integrity of pharmaceutical filtration membranes and method thereof - An automated test apparatus for risk and integrity testing for pharmaceutical filtration membranes, including at least the following components: a liquid injection inlet, a pump, a fluid pressure gauge, a gas pressure gauge, a plurality of solenoid valves, a plurality of membranes, a gas pressure regulator valve, a pharmaceutical product bottle, and a bubble generation bottle. The automated test apparatus of the present invention is controlled by computer software in connection with an automatic pharmaceutical synthesis apparatus for automated testing. In use of the automated test apparatus of the present invention, it needs only to start the operating system of the automated test apparatus for membrane risk and integrity test after the completion of the automatic pharmaceutical synthesis. The membrane risk and integrity test can be accomplished in a short time by measuring pressures of gas and liquid with pressure gauges deposed online concurrently. | 02-05-2015 |
Patent application number | Description | Published |
20110017414 | Method for making mineral fiber paper - Disclosed is a method for making fiber paper. In this method, mineral fibers and PVA resin are blended in water, thus forming first solution. Polymer fibers and PVA resin are blended in water, thus forming second solution. The first solution is mixed with the second solution. A wet paper-making machine is used to make mineral fiber paper from the mixture. | 01-27-2011 |
20120289396 | Method for Producing a Refractory Material from Aluminum residues - Disclosed is a method for making a refractory material from aluminum residues of aluminum recycling. At first, the aluminum residues is mixed with adhesive solution so that the percentage by weight of the adhesive solution is 5 wt % to 10 wt %. The mixture is granulated into grains. The grains are filled in a mold, pressed and then removed from the mold so that the grains are turned into a green body. The green body is heated in a furnace at a range of temperature from 1100° C. to 1400° C. so that the grains are sintered and become a refractory material. | 11-15-2012 |
20130049248 | Method of Producing Artificial Stones with Aluminum residues - The present disclosure uses aluminum residues to fabricate artificial stones. The aluminum residues are obtained from a recycle process of aluminum scrap. The aluminum residues is made into dross and baghouse dust as raw materials for the artificial stones. The artificial stones thus made are improved in characteristics of mechanical strength, hardness, abrasion resistance, flame resistance and anti-oxidation. Hence, the present disclosure reduces impacts to the nature; obtains derived products from recycled aluminum residues; increases commercial income; decreases cost for handling aluminum residues; and saves the use of aluminum oxide, aluminium hydroxide or silicon oxide on making artificial stones. The artificial stones thus made are fit to be used in fields of green material, green construction and green industry. | 02-28-2013 |
20140322078 | METHOD FOR DECONTAMINATING BRICK OR CONCRETE - A method for decontaminating a brick or concrete according to the present invention comprises the steps of: pulverizing the brick or the concrete by using a pulverizing device (pulverizing step); arranging the brick or concrete in a container room and washing the brick or concrete by using a decontamination agent in the container room (washing), wherein the container room has a pressure of above 74 Pa, and a temperature of above 32° C., and the decontamination agent includes a supercritical carbon dioxide flow, a cosolvent and a metal chelating agent; introducing a replacing fluid to the container room to replace the decontamination agent in the container room and then separating the replacing fluid and the brick or concrete (replacing and separating step); and acid cleaning the cosolvent and the metal chelating agent by using an acidic solution (acid cleaning step). A radionuclide may be decontaminated from the brick or concrete. | 10-30-2014 |
Patent application number | Description | Published |
20090197354 | SYSTEM AND METHOD FOR MONITORING MANUFACTURING PROCESS - A system and method for monitoring a manufacturing process are provided. A wafer is provided. Process parameters of a manufacturing machine are in-situ measured and recorded if the wafer is processed in the manufacturing machine. A wafer measured value of the wafer is measured after the wafer has been processed. The process parameters are transformed into a process summary value. A two dimensional orthogonal chart with a first axis representing the wafer measured value and a second axis representing the process summary value is provided. The two dimensional orthogonal chart includes a close-loop control limit. A visualized point representing the wafer measured value and the process summary value is displayed on the two dimensional orthogonal chart. | 08-06-2009 |
20090259332 | FUZZY CONTROL METHOD FOR ADJUSTING A SEMICONDUCTOR MACHINE - A method of fuzzy control for adjusting a semiconductor machine comprising: providing measurement values from first the “parameter of a pre-semiconductor manufacturing process”, second the “parameter of the semiconductor manufacturing process”, and third the “operation parameter of the semiconductor manufacturing process”; performing a fuzzy control to define two inputs and one output corresponding to the measurement values, wherein the difference between the first and third values, and the difference between the second and third values, forms the two inputs, then from the two inputs one target output is calculated by fuzzy inference; finally, determining if the target output is in or out of an acceptable range. Whereby the target output is the “machine control parameter of the semiconductor manufacturing process” and when within an acceptable range is used for adjusting the semiconductor machine. | 10-15-2009 |
20090327173 | METHOD FOR PREDICTING CYCLE TIME - A method for predicting cycle time comprises the steps of: collecting a plurality of known sets of data; using a clustering method to classify the known sets of data into a plurality of clusters; using a decision tree method to build a classification rule of the clusters; building a prediction model of each cluster; preparing data predicted set of data; using the classification rule to determine that to which clusters the predicted set of data belongs; and using the prediction model of the cluster to estimate the objective cycle time of the predicted set of data. Therefore, engineers can beforehand know the cycle time that one lot of wafers spend in the forward fabrication process, which helps engineers to properly arrange the following fabrication process of the lot of wafer. | 12-31-2009 |
20100233830 | METHOD FOR MONITORING FABRICATION PARAMETER - A method for monitoring fabrication parameters comprises steps of: obtaining a normal parameter variance curve and a comparing parameter variance curve; defining a plurality of normal parameter points on the normal parameter variance curve; defining a plurality of comparing parameter points on the comparing parameter variance curve; finding out the corresponding comparing parameter points nearest to the normal parameter points; calculating the distances between the normal parameter points and the corresponding comparing parameter points thereof; summing up the distances so as to receive a total distance; and determining whether or not the total distance exceeds a limit. Via this arrangement, when fabrication parameter of tool is abnormal, it can be efficiently and immediately determined. | 09-16-2010 |
Patent application number | Description | Published |
20100073206 | ANALOG-TO-DIGITAL CONVERSION CIRCUITS AND METHOD FOR CALIBRATING THEREOF - An analog-to-digital conversion circuit is provided and includes an input unit, at least one analog-to-digital converter, and a processing unit. The input unit receives an analog input signal and outputs an analog output signal. A first reference signal is injected into the input unit, and the analog output signal is related to the first reference signal. The at least one analog-to-digital converter receives the analog output signal and converts the analog output signal to a digital output signal. The processing unit receives the digital output signal and performs correlation computation on the digital output signal with a second reference signal to generate a calibration parameter. | 03-25-2010 |
20100073209 | TRACK AND HOLD AMPLIFIERS AND ANALOG TO DIGITAL CONVERTERS - A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal. | 03-25-2010 |
20100225515 | TRACK AND HOLD AMPLIFIERS AND ANALOG TO DIGITAL CONVERTERS - A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal. | 09-09-2010 |