Patent application number | Description | Published |
20110175789 | RF MODULE AND ANTENNA SYSTEMS - Architectures and implementations of a transceiver system for wireless communications are presented, the system including one or more antennas supporting a single frequency band or multiple frequency bands, a transmit circuit, a receive circuit, and an isolation circuit that is coupled to the one or more antennas and the transmit and receive circuits and provides adequate isolation between the transmit circuit and the receive circuit. | 07-21-2011 |
20110210787 | SWITCHLESS BAND SEPARATION FOR TRANSCEIVERS - A system includes a plurality of band pass filters to pass signals in separated frequency bands to or from an antenna. A matching network provides characteristic impedances. The system is designed such that the configuration of the matching network and BPFs provides high impedance to the band pass filters for those routing paths other than the band pass path as these routing paths do not transmit or receive the signals at this particular pass band. The system is further designed such that the configuration of the matching network and BPFs provides minimal insertion loss for the band pass path of for transmission and receipt of signals at this particular pass band, where each routing path has a corresponding pass band. The matching network is for coupling to an amplifier, when frequency separation is needed at the output of the amplifier to the BPFs. In one embodiment an impedance network tunes the impedance by using varying length transmission lines. | 09-01-2011 |
20110267244 | MULTI-FUNCTIONAL CRLH ANTENNA DEVICE - This application relates to a multi-functional Composite Right and Left Handed CRLH antenna device. A conductive element of a wireless device is incorporated into the antenna structure for reuse. In one embodiment a peripheral feature, such as a key dome, is incorporated into the antenna device. In this way, the antenna structure includes portions which are multi-functional. | 11-03-2011 |
20120313830 | MULTI-BAND ANTENNA - Methods and systems for extending a bandwidth of a multi-band antenna of a user device are described. A multi-band antenna includes a single radio frequency (RF) input coupled to a first antenna, the first antenna configured to provide a first resonant mode. The multi-band antenna also includes a second antenna parasitically coupled to the first antenna to provide additional resonant modes of the multi-band antenna. | 12-13-2012 |
20130114470 | DUPLEXER WITH ENHANCED ISOLATION - A system includes a transmit filter ( | 05-09-2013 |
20130147673 | METAMATERIAL LOADED ANTENNA STRUCTURES - Techniques and devices based on antenna structures with a MTM loading element. | 06-13-2013 |
20130156080 | ANTENNA DEPLOYMENT SWITCHING FOR DATA COMMUNICATION OF A USER DEVICE - Methods and systems for selecting one of a plurality of antennas to be used as a transmit antenna based on an orientation of a user device are described. A user device determines an orientation of the user device, and selects one of multiple antennas to use as a first transmit antenna based on the orientation of the user device. The user device transmits information using the first transmit antenna. | 06-20-2013 |
20140022133 | SINGLE-LAYER METALIZATION AND VIA-LESS METAMATERIAL STRUCTURES - Techniques and apparatus based on metamaterial structures provided for antenna and transmission line devices, including single-layer metallization and via-less metamaterial structures. | 01-23-2014 |
20150102968 | ANTENNA DEVICES HAVING FREQUENCY-DEPENDENT CONNECTION TO ELECTRICAL GROUND - Antenna devices and techniques that provide specific control of the spatial distributions of DC and RF signals at various positions in a wireless apparatus are disclosed. The wireless apparatus includes various device components each having specifications for achieving desired operations in antenna devices. | 04-16-2015 |
Patent application number | Description | Published |
20110239149 | TIMELINE CONTROL - Timeline control techniques are described. In one or more implementations, a timeline is displayed that is divided into a plurality of intervals, each of which corresponds to a respective period of time. Responsive to selection of one of the plurality of intervals, a control is displayed within the selected interval that is scrollable within an area defined by the selected interval to move between content that is associated at corresponding points in time at a scrolling speed that is based at least in part on an amount of the content that is associated with the interval. | 09-29-2011 |
20130122875 | LOCATION-BASED AND GROUP-BASED OPERATIONS ON A DATA PROCESSING DEVICE - A system and method are described for location-based and group-based operations on a data processing device. For example, a computer-implemented method according to one embodiment of the invention comprises: establishing a group containing identities of a plurality of users within the group and notification data indicating when other users are to be notified about current locations of the users in the group; determining whether wireless data processing devices of two or more users of the group are at the same location or within a particular distance of the location; identifying the users and the location; and notifying other users in the group of the identity of the users and the location. | 05-16-2013 |
20140095964 | MESSAGE LINKS - A system is described that includes a web link evaluation process for identifying a web link included in a message and selecting content from a website associated with the web link. The selected content may be presented to a user in a format that permits the user to consider whether the link may be safely clicked on. | 04-03-2014 |
20140096032 | CENTRALIZED MEDIA HANDLING - A system is described that includes a media management application for automatically scanning messages in a message inbox and new messages that are sent from or received by the message inbox to identify content, such as pictures, songs, etc., for tagging each message based on content attributes, and for storing the messages and content in a “shoebox” relative to the content attributes. | 04-03-2014 |
20140181934 | SUPPORTING MULTIPLE MESSAGING SERVICES ON MOBILE DEVICES IN A SINGLE USER EXPERIENCE - A system is described that contains a device including a memory with a management application installed thereon. The management application contains a manager that generates a plurality of user accounts and associates at least one communication service as a messaging account with each user account, and an interface module that generates a user interface that presents the plurality of user accounts and that modifies the user interface based on the identification of the selected user account to present a selected account display. | 06-26-2014 |
20140280582 | RELATIONSHIP TRACKING AND MAINTENANCE - Disclosed are for aggregating communication data. Data pertaining to a plurality of users is received. A probability that a particular user of the plurality of users will likely have a future encounter with a first other user of the plurality of users based on the received data is determined. An identity of the first other user is provided. Communication content exchanged between the first other user and the particular user is also provided. | 09-18-2014 |
20140298347 | COMPUTING SYSTEM WITH RESOURCE MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an activity-schedule module configured to identify a future activity estimation for representing an activity occurring after a current time; a usage module, coupled to the activity-schedule module, configured to generate a consumption model associated with the future activity estimation for describing a resource; a model generator module, coupled to the usage module, configured to determine a cost model for evaluating an access location; and a selection module, coupled to the model generator module, configured to determine an optimal access selection based on the cost model and the consumption model for displaying on a device. | 10-02-2014 |
20150094093 | COMPUTING SYSTEM WITH CONFIGURATION UPDATE MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: a context module configured to determine a contextual information for representing the contextual information relative to a device; a zone module, coupled to the context module, configured to determine a proximity zone for identifying further devices within the proximity zone relative to the device; a proximate-device module, coupled to the zone module, configured to determine proximate-device identities for identifying the further devices relative to the device; and a configuration transfer module, coupled to the proximate-device module, configured to communicate a transferable configuration setting with a communication unit using the proximate-device identities for updating the device based on the transferable configuration setting and the contextual information for displaying on the device. | 04-02-2015 |
20150095725 | COMPUTING SYSTEM WITH INFORMATION MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: a control unit configured to: determine a precision level of an entry made to an application, determine an incomplete item based on the precision level failing to meet a precision threshold, and a user interface, coupled to the control unit, configured to display the incomplete item. | 04-02-2015 |
Patent application number | Description | Published |
20140091381 | SUPPORT LINES TO PREVENT LINE COLLAPSE IN ARRAYS - Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings. | 04-03-2014 |
20140151778 | Select Gate Formation for Nanodot Flat Cell - Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches. | 06-05-2014 |
20140175530 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 06-26-2014 |
20140239365 | METHOD FOR USING NANOPARTICLES TO MAKE UNIFORM DISCRETE FLOATING GATE LAYER - A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape. | 08-28-2014 |
20140252447 | Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices - A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer. | 09-11-2014 |
20140346583 | INVERTED-T WORD LINE AND FORMATION FOR NON-VOLATILE STORAGE - A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines. | 11-27-2014 |
20140346584 | MEMORY DEVICE WITH CONTROL GATE OXYGEN DIFFUSION CONTROL AND METHOD OF MAKING THEREOF - An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate. | 11-27-2014 |
20150072488 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 03-12-2015 |
20150137208 | NAND STRING CONTAINING SELF-ALIGNED CONTROL GATE SIDEWALL CLADDING - A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates. | 05-21-2015 |
20150214235 | NON-VOLATILE STORAGE ELEMENT WITH SUSPENDED CHARGE STORAGE REGION - Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid. | 07-30-2015 |
20150287733 | IN-SITU SUPPORT STRUCTURE FOR LINE COLLAPSE ROBUSTNESS IN MEMORY ARRAYS - Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch. | 10-08-2015 |
20150318295 | VERTICAL FLOATING GATE NAND WITH OFFSET DUAL CONTROL GATES - A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack. | 11-05-2015 |
20150318298 | TRENCH VERTICAL NAND AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench. | 11-05-2015 |
Patent application number | Description | Published |
20120029411 | CARPAL TUNNEL DRAINAGE - A procedure for treating carpal tunnel syndrome can involve aspirating one or more of the flexor tendons running through the carpal tunnel to reduce swelling, and hence reduce the cross-sectional area of those flexor tendons. As a result, the median nerve also running through the carpal tunnel is less constricted, and the CTS symptoms associated with such constriction can be relieved. Such relief can be enhanced by delivery of one or more therapeutic substances to the area to provide additional or supplemental symptom treatment. | 02-02-2012 |
20120029543 | TISSUE STRUCTURE PERFORATION SYSTEM AND METHOD - A surgical treatment can involve creating a pattern of perforations in a tissue structure to allow lengthening of that tissue structure. For example, a pattern of perforations can be created in the transverse carpal ligament of a patient suffering from carpal tunnel syndrome (CTS) that allows the carpal ligament to lengthen slightly. This lengthening can relieve pressure on the median nerve, thereby reducing the symptoms of CTS while maintaining the structural integrity of the wrist. A surgical instrument for use in perforating a tissue structure (such as the transverse ligament) can be an elongate structure with one or more retractable blades. Such a tool can be used in either an open or minimally invasive procedure to create a desired pattern of perforations in the tissue structure. | 02-02-2012 |
20120100125 | LOCAL DEHYDRATION FOR CARPAL TUNNEL SYNDROME - A procedure for treating carpal tunnel syndrome can involve delivering a dehydrating agent into and/or near the carpal tunnel. The dehydrating agent can reduce swelling of the flexor tendons and/or the carpal ligament in the region, thereby reducing pressure on the median nerve that also runs through the carpal tunnel. Through the use of a dehydrating agent that affects proteoglycans without affecting collagen, localized dehydration can be induced without weakening the flexor tendons, carpal ligament, and any other structures in the carpal tunnel region. | 04-26-2012 |
20120101325 | LOCALLY TARGETED ANTI-FIBROTIC AGENTS AND METHODS OF USE - Effective devices and methods using an antifibrotic agent are provided for treating fibrosis or treating normal fibrous tissue. The devices and methods comprise an antifibrotic agent to degrade shrink, relax or stretch at least a portion of the fibrotic tissue. In some embodiments, the methods and devices are configured to immediately release an effective amount of the antifibrotic agent within 24 hours. In some embodiments, when the device comes in contact directly or indirectly with an activator, the antifibrotic agent will be immediately released from the depot. In some embodiments, the depot provides sustained release of the antifibrotic agent over a period of up to one year to treat fibrous tissue. | 04-26-2012 |
20120101577 | ACTIVATABLE DEVICES CONTAINING A CHEMONUCLEOLYSIS AGENT - Effective devices and methods using a chemonucleolysis agent are provided for treating an intervertebral disc or treating spinal arachnoiditis. The devices and methods comprise a chemonucleolysis agent to degrade or to shrink at least a portion of the intervertebral disc. In some embodiments, the methods and devices are configured to immediately release an effective amount of the chemonucleolysis agent within 24 hours when the device comes in contact directly or indirectly with an activator and provide sustained release of the chemonucleolysis agent over a period of up to one year to treat the intervertebral disc. In some embodiments, the chemonucleolysis agent in the device is administered in or near the intrathecal space and/or thecal sac to treat spinal arachnoiditis. | 04-26-2012 |
20120101578 | DEVICES CONTAINING A CHEMONUCLEOLYSIS AGENT AND METHODS FOR TREATING AN INTERVERTEBRAL DISC OR SPINAL ARACHNOIDITIS - Effective devices and methods using a chemonucleolysis agent are provided for treating an intervertebral disc or treating spinal arachnoiditis. The devices and methods comprise a chemonucleolysis agent to degrade or to shrink at least a portion of the intervertebral disc. In some embodiments, the methods and devices are configured to immediately release an effective amount of the chemonucleolysis agent within 24 hours and provide sustained release of the chemonucleolysis agent over a period of up to one year to treat the intervertebral disc. In some embodiments, the chemonucleolysis agent in the device is administered in or near the intrathecal space and/or thecal sac to treat spinal arachnoiditis. | 04-26-2012 |
20120158099 | LOW LEVEL LASER THERAPY FOR LOW BACK PAIN - The invention provides an energy source emitting, such as a low level laser light, catheter having a throughbore, an energy emitting surface disposed near the distal end of the catheter that is connected, directly or indirectly, to the energy source, which allows for the application of therapeutic energy to treat internal areas of a patient that have been accessed by way of a catheter. | 06-21-2012 |
20120253466 | METHODS AND DEVICES FOR THE TREATMENT OF INTERVERTEBRAL DISCS DISORDERS - Devices for the treatment of intervertebral discs are described. The devices, when implanted into the nucleus pulposus of an intervertebral disc, are specifically configured with an inert outer layer and an inner layer containing at least one chemonucleolysis agent so as to provide a delayed and controlled release of the chemonucleolysis agent from the inner layer into the disc. The implant can be an elongated solid body having a tapered or rounded insertion end having at least one therapeutic agent in the inner layer of the implant surrounded by an outer layer of inert material. | 10-04-2012 |
Patent application number | Description | Published |
20080202588 | METHOD AND APPARATUS FOR CONTROLLING GAS FLOW TO A PROCESSING CHAMBER - A method and apparatus for delivering gases to a semiconductor processing system are provided. In one embodiment, an apparatus for delivering gases to a semiconductor processing system includes a plurality of gas input and output lines having inlet and outlet ports. Connecting lines couple respective pairs of the gas input and gas output lines. Connecting valves are arranged to control flow through the respective connecting lines. Mass gas flow controllers are arranged to control flow into respective inlet ports. In another embodiment, a method includes providing a manifold having at least a plurality of inlet that may be selectively coupled to at least one of a plurality of outlets, flowing one or more gases through the manifold to a vacuum environment by-passing the processing chamber prior to processing or to a calibration circuit, and flowing the one or more gases into the processing chamber during substrate processing. | 08-28-2008 |
20080202609 | METHOD AND APPARATUS FOR CONTROLLING GAS FLOW TO A PROCESSING CHAMBER - A method and apparatus for delivering gases to a semiconductor processing system are provided. In one embodiment, an apparatus for delivering gases to a semiconductor processing system includes a plurality of gas input and output lines having inlet and outlet ports. Connecting lines couple respective pairs of the gas input and gas output lines. Connecting valves are arranged to control flow through the respective connecting lines. Mass gas flow controllers are arranged to control flow into respective inlet ports. In another embodiment, a method includes providing a manifold having at least a plurality of inlet that may be selectively coupled to at least one of a plurality of outlets, flowing one or more gases through the manifold to a vacuum environment by-passing the processing chamber prior to processing or to a calibration circuit, and flowing the one or more gases into the processing chamber during substrate processing. | 08-28-2008 |
20080202610 | METHOD AND APPARATUS FOR CONTROLLING GAS FLOW TO A PROCESSING CHAMBER - A method and apparatus for delivering gases to a semiconductor processing system are provided. In one embodiment, an apparatus for delivering gases to a semiconductor processing system includes a plurality of gas input and output lines having inlet and outlet ports. Connecting lines couple respective pairs of the gas input and gas output lines. Connecting valves are arranged to control flow through the respective connecting lines. Mass gas flow controllers are arranged to control flow into respective inlet ports. In another embodiment, a method includes providing a manifold having at least a plurality of inlet that may be selectively coupled to at least one of a plurality of outlets, flowing one or more gases through the manifold to a vacuum environment by-passing the processing chamber prior to processing or to a calibration circuit, and flowing the one or more gases into the processing chamber during substrate processing. | 08-28-2008 |
20090272717 | METHOD AND APPARATUS OF A SUBSTRATE ETCHING SYSTEM AND PROCESS - Embodiments of the invention relate to a substrate etching system and process. In one embodiment, a method may include depositing material on the substrate during a deposition process, etching a first layer of the substrate during a first etch process, and etching a second layer of the substrate during a second etch process, wherein a first bias power is applied to the substrate during the first process, and wherein a second bias power is applied to the substrate during the second etch process. In another embodiment, a system may include a gas delivery system containing a first gas panel for supplying a first gas to a chamber, a second gas panel for supplying a second gas to the chamber, and a plurality of flow controllers for directing the gases to the chamber to facilitate rapid gas transitioning between the gases to and from the chamber and the panels. | 11-05-2009 |
20100251828 | METHOD AND APPARATUS FOR GAS FLOW MEASUREMENT - A method and apparatus for measuring gas flow are provided. In one embodiment, a calibration circuit for gas control may be utilized to verify and/or calibrate gas flows utilized for backside cooling, process gas delivery, purge gas delivery, cleaning agent delivery, carrier gases delivery and remediation gas delivery, among others. | 10-07-2010 |
20110265831 | METHODS AND APPARATUS FOR PROVIDING A GAS MIXTURE TO A PAIR OF PROCESS CHAMBERS - A method and apparatus for supplying a gas mixture to a load lock chamber is described. In one embodiment, the apparatus supplies a gas mixture to a pair of process chambers, comprising a first ozone generator to provide a first gas mixture to a first process chamber, a second ozone generator to provide a second gas mixture to a second process chamber, a first gas source coupled to the first ozone generator via a first mass flow controller and a first gas line, and coupled to the second ozone generator via a second mass flow controller and a second gas line, and a second gas source coupled to the first ozone generator via a third mass flow controller and a third gas line and coupled to the second ozone generator via fourth mass flow controller and a fourth gas line. | 11-03-2011 |
20110265883 | METHODS AND APPARATUS FOR REDUCING FLOW SPLITTING ERRORS USING ORIFICE RATIO CONDUCTANCE CONTROL - Methods and apparatus for gas delivery to a process chamber are provided herein. In some embodiments, an apparatus for processing substrates may include a mass flow controller to provide a desired total fluid flow; a first flow control manifold comprising a first inlet, a first outlet, and a first plurality of orifices selectably coupled therebetween, wherein the first inlet is coupled to the mass flow controller; and a second flow control manifold comprising a second inlet, a second outlet, and a second plurality of orifices selectably coupled therebetween, wherein the second inlet is coupled to the mass flow controller; wherein a desired flow ratio between the first outlet and the second outlet is selectably obtainable when causing the fluid to flow through one or more of the first plurality of orifices of the first manifold and one or more of the second plurality of orifices of the second manifold. | 11-03-2011 |
20110265887 | APPARATUS FOR RADIAL DELIVERY OF GAS TO A CHAMBER AND METHODS OF USE THEREOF - Apparatus for the delivery of a gas to a chamber and methods of use thereof are provided herein. In some embodiments, a gas distribution system for a process chamber may include a body having a first surface configured to couple the body to an interior surface of a process chamber, the body having a opening disposed through the body; a flange disposed proximate a first end of the opening opposite the first surface of the body, the flange extending inwardly into the opening and configured to support a window thereon; and a plurality of gas distribution channels disposed within the body and fluidly coupling a channel disposed within the body and around the opening to a plurality of holes disposed in the flange, wherein the plurality of holes are disposed radially about the flange. | 11-03-2011 |
20110265899 | SYSTEM AND METHOD FOR CALIBRATING PRESSURE GAUGES IN A SUBSTRATE PROCESSING SYSTEM - Systems and methods for calibrating pressure gauges in one or more process chambers coupled to a transfer chamber having a transfer volume is disclosed herein. The method includes providing a first pressure in the transfer volume and in a first inner volume of a first process chamber coupled to the transfer chamber, wherein the transfer volume and the first inner volume are fluidly coupled, injecting a calibration gas into the transfer volume to raise a pressure in the transfer volume and in the first inner volume to a second pressure, measuring the second pressure using each of a reference pressure gauge coupled to the transfer chamber and a first pressure gauge coupled to the first process chamber while the transfer volume and the first inner volume are fluidly coupled, and calibrating the first pressure gauge based on a difference in the measured second pressure between the reference pressure gauge and the first pressure gauge. | 11-03-2011 |
20110265951 | TWIN CHAMBER PROCESSING SYSTEM - Methods and apparatus for twin chamber processing systems are disclosed, and, in some embodiments, may include a first process chamber and a second process chamber having independent processing volumes and a plurality of shared resources between the first and second process chambers. In some embodiments, the shared resources include at least one of a shared vacuum pump, a shared gas panel, or a shared heat transfer source. | 11-03-2011 |
20110269314 | PROCESS CHAMBERS HAVING SHARED RESOURCES AND METHODS OF USE THEREOF - Process chambers having shared resources and methods of use are provided. In some embodiments, substrate processing systems may include a first process chamber having a first substrate support disposed within the first process chamber, wherein the first substrate support has a first heater and a first cooling plate to control a temperature of the first substrate support; a second process chamber having a second substrate support disposed within the second process chamber, wherein the second substrate support has a second heater and a second cooling plate to control a temperature of the second substrate support; and a shared heat transfer fluid source having an outlet to provide a heat transfer fluid to the first cooling plate and the second cooling plate and an inlet to receive the heat transfer fluid from the first cooling plate and the second cooling plate. | 11-03-2011 |
20110304078 | METHODS FOR REMOVING BYPRODUCTS FROM LOAD LOCK CHAMBERS - Methods for removing process byproducts from a load lock chamber are provided herein. In some embodiments, a method for removing process byproducts from a load lock chamber may include: performing a process on a substrate disposed within a process chamber; transferring the substrate from the process chamber to a load lock chamber; and providing an inert gas to the load lock chamber via at least one gas line while transferring the substrate from the process chamber to the load lock chamber to remove process byproducts from the load lock chamber. | 12-15-2011 |
20120222699 | METHOD FOR REMOVING HALOGEN-CONTAINING RESIDUES FROM SUBSTRATE - Methods for removing halogen-containing residues from a substrate are provided. By combining the heat-up and plasma abatement steps, the manufacturing throughput can be improved. Further, by appropriately controlling the pressure in the abatement chamber, the removal efficiency can be improved as well. | 09-06-2012 |
20120222752 | METHOD EXTENDING THE SERVICE INTERVAL OF A GAS DISTRIBUTION PLATE - Methods for reducing the contamination of a gas distribution plate are provided. In one embodiment, a method for processing a substrate includes transferring the substrate into a chamber, performing a treating process on the substrate, and providing a purge gas into the chamber before or after the treating process to pump out a residue gas relative to the treating process from the chamber. The treating process includes distributing a reactant gas into the chamber through a gas distribution plate. | 09-06-2012 |
20120222813 | VACUUM CHAMBERS WITH SHARED PUMP - Embodiments of the present disclosure generally relate to vacuum processing chambers having different pumping requirements and connected to a shared pumping system through a single foreline. In one embodiment, the vacuum processing chambers include a high conductance pumping conduit and a low conductance pumping conduit coupled to a single high conductance foreline. In another embodiment, a plurality of unbalanced chamber groups may be connected to a common pumping system by a final foreline. | 09-06-2012 |
20130059403 | METHOD AND APPARATUS FOR WAFER TEMPERATURE MEASUREMENT USING AN INDEPENDENT LIGHT SOURCE - An apparatus is provided for measuring a substrate temperature during an etching process, comprising: one or more windows formed in a substrate supporting surface; a first signal generator configured to pulse a first signal; and a first sensor positioned to receive energy transmitted from the first signal generator through the one or more windows. A method is provided for measuring a substrate temperature during an etching process comprising: heating a substrate using radiant energy; pulsing a first light; determining a metric indicative of total transmittance through the substrate when the first light is pulsed on; determining a metric indicative of background transmittance through the substrate when the first light is pulsed off; and determining a process temperature. | 03-07-2013 |
20130224953 | ABATEMENT AND STRIP PROCESS CHAMBER IN A LOAD LOCK CONFIGURATION - Embodiments of the present invention a load lock chamber including two or more isolated chamber volumes, wherein one chamber volume is configured for processing a substrate and another chamber volume is configured to provide cooling to a substrate. One embodiment of the present invention provides a load lock chamber having at least two isolated chamber volumes formed in a chamber body assembly. The at least two isolated chamber volumes may be vertically stacked. A first chamber volume may be used to process a substrate disposed therein using reactive species. A second chamber volume may include a cooled substrate support. | 08-29-2013 |
20130284287 | APPARATUS FOR UNIFORM PUMPING WITHIN A SUBSTRATE PROCESS CHAMBER - Substrate supports for use in process chambers having limited physical space for configuring chamber components are disclosed. In some embodiments, a substrate support may include a body having a support surface; a utilities feed coupled to the body and comprising a second portion coupled to and extending laterally away from the body beyond a diameter of the body, and first portion coupled to the second portion and extending perpendicularly away from the body; and a cover plate movably disposable beneath and with respect to the body between a first position disposed completely beneath the body, and a second position wherein the cover plate is disposed over the first portion of the utilities feed and includes a first portion disposed beneath the body, and wherein the first portion has a curved edge having a radius equal to the distance from a central axis of the support surface to the curved edge. | 10-31-2013 |
20130334199 | THIN HEATED SUBSTRATE SUPPORT - Embodiments of the present invention provide an apparatus heating and supporting a substrate in a processing chamber. One embodiment of the present invention provides a substrate support assembly. The substrate support assembly includes a heated plate having a substrate supporting surface on a front side and a cantilever arm extending from a backside of the heated plate. The heated plate is configured to support and heat a substrate on the substrate supporting surface. The cantilever arm has a first end attached to the heated plate near a central axis of the heated plate, and a second end extending radially outwards from the central axis. | 12-19-2013 |
20130337655 | ABATEMENT AND STRIP PROCESS CHAMBER IN A DUAL LOADLOCK CONFIGURATION - Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume. | 12-19-2013 |
20140076850 | METHODS AND APPARATUS FOR PROVIDING A GAS MIXTURE TO A PAIR OF PROCESS CHAMBERS - A method and apparatus for supplying a gas mixture to a load lock chamber is described. In one embodiment, the apparatus supplies a gas mixture to a pair of process chambers, comprising a first ozone generator to provide a first gas mixture to a first process chamber, a second ozone generator to provide a second gas mixture to a second process chamber, a first gas source coupled to the first ozone generator via a first mass flow controller and a first gas line, and coupled to the second ozone generator via a second mass flow controller and a second gas line, and a second gas source coupled to the first ozone generator via a third mass flow controller and a third gas line and coupled to the second ozone generator via fourth mass flow controller and a fourth gas line. | 03-20-2014 |
20140087561 | METHOD AND APPARATUS FOR SUBSTRATE TRANSFER AND RADICAL CONFINEMENT - Embodiments of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One embodiment of the present invention provides a hoop assembly for using a processing chamber. The hoop assembly includes a confinement ring defining a confinement region therein, and three or more lifting fingers attached to the hoop. The three or more lifting fingers are configured to support a substrate outside the inner volume of the confinement ring. | 03-27-2014 |
20140110057 | SEGMENTED FOCUS RING ASSEMBLY - Embodiments of the present invention include a focus ring segment and a focus ring assembly. In one embodiment, the focus ring segment includes an arc-shaped body having a lower ring segment, a middle ring segment, a top ring segment and a lip. The lower ring segment has a bottom surface, and the middle ring segment has a bottom surface, wherein the middle ring segment is connected to the lower ring segment at the middle ring segment bottom surface. The top ring segment has a bottom surface, wherein the top ring segment is connected to the middle ring segment at the top ring segment bottom surface. The lip extends horizontally above the middle ring segment, wherein the lip is sloped radially inwards towards a centerline of the focus ring segment. In another embodiment, the focus ring assembly includes at least a first ring segment and a second ring segment. | 04-24-2014 |
20140366953 | PARTICLE REDUCTION VIA THROTTLE GATE VALVE PURGE - Methods and apparatus for particle reduction in throttle gate valves used in substrate process chambers are provided herein. In some embodiments, a gate valve for use in a process chamber includes a body having an opening disposed therethrough from a first surface to an opposing second surface of the body; a pocket extending into the body from a sidewall of the opening; a gate movably disposed within the pocket between a closed position that seals the opening and an open position that reveals the opening and disposes the gate completely within the pocket; and a plurality of gas ports disposed in the gate valve configured to direct a gas flow into a portion of the gate valve fluidly coupled to the opening. | 12-18-2014 |
20150063405 | SUBSTRATE PLACEMENT DETECTION IN SEMICONDUCTOR EQUIPMENT USING THERMAL RESPONSE CHARACTERISTICS - Methods and apparatus for determining proper placement of a substrate upon a substrate support in a process chamber are disclosed. In some embodiments, a method for detecting substrate placement in a process chamber includes placing a substrate on a support surface of a substrate support with the process chamber; modifying a pressure within the chamber to create a detection pressure within the chamber; sensing a first temperature of the substrate support; monitoring a thermal response characteristic of the substrate support after placing the substrate on the substrate support; comparing the thermal response characteristic to a predetermined response characteristic; and determining whether the substrate is placed correctly based upon the comparison of the thermal response characteristic to the predetermined response characteristic. | 03-05-2015 |
20150307982 | PLASMA EROSION RESISTANT THIN FILM COATING FOR HIGH TEMPERATURE APPLICATION - An article such as a susceptor includes a body of a thermally conductive material coated by a first protective layer and a second protective layer over a surface of the body. The first protective layer is a thermally conductive ceramic. The second protective layer covers the first protective layer and is a plasma resistant ceramic thin film that is resistant to cracking at temperatures of 650 degrees Celsius. | 10-29-2015 |
Patent application number | Description | Published |
20110258475 | Dynamically Calibrated DDR Memory Controller - A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided. | 10-20-2011 |
20140013149 | Dynamically Calibrated DDR Memory Controller - A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values. | 01-09-2014 |
20140075146 | METHODS FOR OPERATING A MEMORY INTERFACE CIRCUIT INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES - A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes. | 03-13-2014 |
20140075236 | MEMORY INTERFACE CIRCUITS INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES - A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes. | 03-13-2014 |
20140129791 | Method of Application Memory Preservation for Dynamic Calibration of Memory Interfaces - A method for calibrating a memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface. | 05-08-2014 |
20140129870 | Application Memory Preservation for Dynamic Calibration of Memory Interfaces - A calibrating memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface. | 05-08-2014 |
20150302905 | METHODS FOR CALIBRATING A READ DATA PATH FOR A MEMORY INTERFACE - A method for calibrating a read data path for a DDR memory interface circuit from time to time in conjunction with functional operation of a memory circuit is described. The method uses the steps of issuing a sequence of read commands so that a delayed dqs signal toggles continuously. Next, delaying a core clock signal originating within the DDR memory interface circuit to produce a capture clock signal. The capture clock signal is delayed from the core clock by a capture clock delay value. Next, determining an optimum capture clock delay value. The output of the read data path is clocked by the core clock. The timing for the read data path with respect to data propagation is responsive to at least the capture clock. | 10-22-2015 |
Patent application number | Description | Published |
20100102999 | CODING SYSTEM FOR MEMORY SYSTEMS EMPLOYING HIGH-SPEED SERIAL LINKS - A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained. | 04-29-2010 |
20100103929 | METHOD, APPARATUS, AND SYSTEM FOR AUTOMATIC DATA ALIGNER FOR MULTIPLE SERIAL RECEIVERS - A method, apparatus and system for employing an automatic data aligner for multiple serial receivers in serial link technologies is provided. In one embodiment, converting a transmission data path of a single bit into a parallel bit via a data aligner, wherein the data is being transmitted via one or more ports. Further, binding data transmission channels to reduce latency in transmission of the data, wherein the binding of the data transmission channels further includes inserting delay to match latency via the one or more ports. | 04-29-2010 |
20100295711 | 17B/20B CODING SYSTEM - A method, apparatus and system employing a 17 B/20 B coder is disclosed. The 17 B/20 B coder to receive an incoming stream including a 17 B block and a 20 B block, and partition the 17 B block into first blocks, and partitioning the 20 B into second blocks. The coder is further to code 17 B to 20 B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17 B block and the second blocks of the 20 B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained. | 11-25-2010 |
20140016037 | INTEGRATED MOBILE DESKTOP - Embodiments of the invention are generally directed to an integrated mobile desktop. An embodiment of an apparatus includes a display chip to receive graphical data and produce video display signals; and a logic chip to receive data from a mobile device and the video display signals from the display chip to generate a display including at least a portion for a representation of a display of the mobile device. The logic chip provides for integration of operations for the apparatus and the mobile device using the generated display. | 01-16-2014 |
20150032975 | Method and System for Improving Serial Port Memory Communication Latency and Reliability - A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval. | 01-29-2015 |
Patent application number | Description | Published |
20110025700 | Using a Texture Unit for General Purpose Computing - An interpolation unit, such as may be found in a texture unit or texture sampler, may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to an interpolation unit. The interpolation unit may use linear interpolators in order to perform the dot product calculations. | 02-03-2011 |
20110066806 | System and method for memory bandwidth friendly sorting on multi-core architectures - In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed. | 03-17-2011 |
20110134137 | Texture Unit for General Purpose Computing - A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations. | 06-09-2011 |
20110148896 | Grouping Pixels to be Textured - A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing grouped pixels improves efficiency. | 06-23-2011 |
20110320913 | RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE SUPPORT - Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device. | 12-29-2011 |
20120137074 | METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS - A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy. | 05-31-2012 |
20120254589 | SYSTEM, APPARATUS, AND METHOD FOR ALIGNING REGISTERS - Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination. | 10-04-2012 |
20120254592 | SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION - Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored. | 10-04-2012 |
20130311530 | APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION - An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N-1 reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals. | 11-21-2013 |
20140089634 | APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER - An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register. | 03-27-2014 |
20140149718 | INSTRUCTION AND LOGIC TO PROVIDE PUSHING BUFFER COPY AND STORE FUNCTIONALITY - Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core. | 05-29-2014 |
20140176590 | Texture Unit for General Purpose Computing - A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations. | 06-26-2014 |
20140181580 | SPECULATIVE NON-FAULTING LOADS AND GATHERS - According to one embodiment, a processor includes an instruction decoder to decode an instruction to read a plurality of data elements from memory, the instruction having a first operand specifying a storage location, a second operand specifying a bitmask having one or more bits, each bit corresponding to one of the data elements, and a third operand specifying a memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the instruction, to read one or more data elements speculatively, based on the bitmask specified by the second operand, from a memory location based on the memory address indicated by the third operand, and to store the one or more data elements in the storage location indicated by the first operand. | 06-26-2014 |
20140189288 | INSTRUCTION TO REDUCE ELEMENTS IN A VECTOR REGISTER WITH STRIDED ACCESS PATTERN - A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a current element position being processed, the execution circuitry sequentially set one or more data elements of the first vector register to a result, which is generated by the associative reduction operation applied to both a previous data element of the first vector register and a data clement of a third vector register. The previous data element is located more than one element position away from the current element position. | 07-03-2014 |
20140189323 | APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION - An apparatus and method for propagating conditionally evaluated values. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register. | 07-03-2014 |
20140223139 | SYSTEMS, APPARATUSES, AND METHODS FOR SETTING AN OUTPUT MASK IN A DESTINATION WRITEMASK REGISTER FROM A SOURCE WRITE MASK REGISTER USING AN INPUT WRITEMASK AND IMMEDIATE - Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described. | 08-07-2014 |
20140237303 | APPARATUS AND METHOD FOR VECTORIZATION WITH SPECULATION SUPPORT - An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition. | 08-21-2014 |
20140337580 | GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY - Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed. | 11-13-2014 |
20150186077 | PROCESSOR WITH ARCHITECTURALLY-VISIBLE PROGRAMMABLE ON-DIE STORAGE TO STORE DATA THAT IS ACCESSIBLE BY INSTRUCTION - A processor of an aspect includes an on-die programmable architecturally-visible storage. The processor also includes a decode unit to receive a data access instruction of an instruction set of the processor. The data access instruction to indicate a data address that is to be associated with data to be stored in the on-die programmable architecturally-visible storage, to indicate a data size associated with the data to be stored in the on-die programmable architecturally-visible storage, and to indicate a destination storage location of the processor. An execution unit is coupled with the decode unit and the on-die programmable architecturally-visible storage. The execution unit is on-die with the on-die programmable storage. The execution unit is operable, in response to the data access instruction, to store the data, which is associated with the data address and the data size, in the destination storage location that is to be indicated by the instruction. | 07-02-2015 |
20150228091 | Texture Unit for General Purpose Computing - A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations. | 08-13-2015 |
20150277910 | METHOD AND APPARATUS FOR EXECUTING INSTRUCTIONS USING A PREDICATE REGISTER - An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence. | 10-01-2015 |
Patent application number | Description | Published |
20130303089 | Uplink and/or Downlink Testing of Wireless Devices in a Reverberation Chamber - A system and method for wireless device testing. The system includes a reverberation chamber (RC) and a downlink channel emulator. A wireless device is placed within the RC. Probe antennas are positioned within the RC. The downlink (DL) channel emulator couples to the probe antennas. The DL channel emulator is configured to: (a) receive downlink stimulus signals; and (b) generate downlink intermediate signals based on the downlink stimulus signals in order to emulate desired downlink channel characteristics. The probe antennas are configured to respectively transmit the downlink intermediate signals into the RC for reception by the wireless device. The system may also include an uplink channel emulator, which receives uplink transmit signals from the RC, and generates uplink terminal signals based on the uplink transmit signals in order to emulate desired uplink channel characteristics. The uplink transmit signals may be used to evaluated the performance of the wireless device. | 11-14-2013 |
20140118194 | MULTI-BAND ANTENNA AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is a multi-band antenna. The multi-band antenna, as provided in one embodiment, includes a first resonant portion having a first length defined by an outer perimeter of a conductive segment and operable to effect an antenna for communication in a first band of frequencies. The multi-band antenna, in this aspect, further includes a second resonant portion having a second length defined by an inner perimeter of the conductive segment and operable to resonate capacitively for communication in a second different band of frequencies. | 05-01-2014 |
20140118204 | ANTENNA INTEGRATED WITH METAL CHASSIS - One aspect provides an antenna. The antenna, in this aspect, includes a grounded segment extending from a metal chassis of an electronic device, and a feed portion coplanar with the grounded segment, the grounded segment and feed portion jointly tuned to cause the antenna to communicate in selected bands of frequencies. | 05-01-2014 |
20150022401 | ANTENNA SYSTEM AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna system. The antenna system, in this aspect, includes a first antenna operable to communicate at a given frequency below about 1000 MHz. The antenna system, in this aspect, further includes a second antenna of a different type associated with the first antenna and operable to communicate at the given frequency, wherein a correlation coefficient of the first and second antennas is less than about 0.5 for the given frequency. In this antenna system, the first and second antennas are capable of fitting within a conductive chassis having a largest physical dimension of about ¼ or less a wavelength of the given frequency. | 01-22-2015 |
20150022402 | CAPACITIVELY COUPLED LOOP ANTENNA AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna. The antenna, in one embodiment, includes a feed element electrically connectable to a positive terminal of a transmission line, and a ground element electrically connectable to a negative terminal of the transmission line. In this embodiment of the antenna, the feed element and ground element capacitively couple to one another without touching to form a capacitively coupled loop antenna. | 01-22-2015 |
20150207219 | WIDEBAND ANTENNA AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna. The antenna, in one embodiment, includes a feed element having a first feed element end and a second feed element end, the first feed element end configured to electrically connect to a positive terminal of a transmission line. The antenna, in this embodiment, further includes a ground element having a first ground element end and a second ground element end, the first ground element end configured to electrically connect to a negative terminal of the transmission line. In this particular embodiment, the first ground element end is located proximate and inside the first feed element end, and the second ground element end is located proximate and outside the second feed element end. | 07-23-2015 |
20150207228 | SINGLE ELEMENT DUAL-FEED ANTENNAS AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna. The antenna, in this aspect, includes an inverted-F GPS antenna structure, the inverted-F GPS antenna structure embodying a GPS feed element, a GPS extending arm, and a ground element. The antenna, in this aspect, further includes a loop WiFi antenna structure, the loop WiFi antenna structure embodying a WiFi feed element, the ground element, and a WiFi connecting arm coupling the WiFi feed element to the ground element. In this particular aspect, the ground element is located between the GPS feed element and the WiFi feed element. | 07-23-2015 |
20150207230 | WIDEBAND LOOP ANTENNA AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna. In one aspect, the antenna includes a feed element having a first feed element end and a second feed element end, the first feed element end configured to electrically connect to a positive terminal of a transmission line. The antenna, in this aspect, further includes a loop antenna element having a first loop antenna element end and a second loop antenna element end, wherein the first loop antenna element end is coupled to the second feed element end and the second loop antenna element end is configured to electrically connect to a negative terminal of the transmission line. The antenna, of this aspect, further includes a monopole antenna element having a first monopole antenna element end and a second monopole antenna element end, wherein the first monopole antenna element end is coupled to the second feed element end. | 07-23-2015 |
20150207231 | CO-LOCATED ANTENNAS AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna system. The antenna system, in this aspect, includes a loop antenna element, the loop antenna element having a positive loop antenna terminal end and a negative loop antenna terminal end. The antenna system, in this embodiment, further includes an inverted-F antenna element co-located with the loop antenna element, the inverted-F antenna element having a positive inverted-F antenna terminal end and a negative inverted-F antenna terminal end located proximate the positive loop antenna terminal end and the negative loop antenna terminal end. In this antenna system embodiment, the positive loop antenna terminal end, negative loop antenna terminal end, positive inverted-F antenna terminal end and negative inverted-F antenna terminal end alternate between positive and negative terminals. | 07-23-2015 |
Patent application number | Description | Published |
20150088943 | Media-Aware File System and Method - An embodiment Media-Aware File System (MAFS) includes a network node having a processor executing programming stored on a non-transitory computer readable medium of the network node. The programming includes instructions to: receive a first media stream made up of a plurality of primary frames; receive a primary namespace for the first media stream; determine a first file name for the first media stream and a second file name for a second media stream in accordance with the primary namespace; and determine a partition index for partitioning the first media stream into a plurality of groups of primary frames, including a first group having a first length in frames and a second group having a different length. The programming also includes instructions to determine the second media stream that includes a derived group of frames, including at least one frame that is derived in accordance with the first group. | 03-26-2015 |
20150089328 | Flex Erasure Coding of Controllers of Primary Hard Disk Drives Controller - System and method embodiments are provided for managing storage systems. In an embodiment, a storage system includes an over-provisioned redundant array of independent disks (RAID); and a flexible erasure coding controller coupled to the RAID, the controller comprising a flexible exclusive-or engine configured to provide erasure coding for the over-provisioned RAID using M-parity convolution codes. | 03-26-2015 |
20150100860 | Systems and Methods of Vector-DMA cache-XOR for MPCC Erasure Coding - System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage interface configured to couple to a plurality of storage devices; and a vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and the erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by the MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two. | 04-09-2015 |
20150254003 | RDMA-SSD DUAL-PORT UNIFIED MEMORY AND NETWORK CONTROLLER - System and method for a unified memory and network controller for an all-flash array (AFA) storage blade in a distributed flash storage clusters over a fabric network. The unified memory and network controller has 3-way control functions including unified memory buses to cache memories and DDR4-AFA controllers, a dual-port PCIE interconnection to two host processors of gateway clusters, and four switch fabric ports for interconnections with peer controllers (e.g., AFA blades and/or chassis) in the distributed flash storage network. The AFA storage blade includes dynamic random-access memory (DRAM) and magnetoresistive random-access memory (MRAM) configured as data read/write cache buffers, and flash memory DIMM devices as primary storage. Remote data memory access (RDMA) for clients via the data caching buffers is enabled and controlled by the host processor interconnection(s), the switch fabric ports, and a unified memory bus from the unified controller to the data buffer and the flash SSDs. | 09-10-2015 |
20150255130 | DDR4-SSD DUAL-PORT DIMM DEVICE - As a solution to the type of problems noted above, this disclosure provides novel methods and systems that include dual-port solid-state drive (SSD) DIMM devices to provide primary storage capabilities with very low latency and better availability of DDR4 devices. The dual-port DDR4-SSD flash memory devices guarantee primary storage devices still accessible with one CPU or network failure. The novel DDR4 memory bus devices may be used not only for memory media and storage device buffers, but also to allow two CPUs to share data stored in flash SSD chips and to greatly improve DDR4 bus efficiency and bus utilizations by block accesses and eliminate PCIE-DMA data transfers. Through the features of the claimed subject matter described herein, dual-port DDR4-DIMM memory devices can be achieved that provide an All-Flash-Array storage system with substantially higher reliability, availability, and performance over conventional SATA/SAS-SSD, PCIE-SSD, and NVME-SSD solutions. | 09-10-2015 |
20150261446 | DDR4-ONFI SSD 1-TO-N BUS ADAPTATION AND EXPANSION CONTROLLER - An apparatus for communicating data requests received by host devices using one DDR protocol to memory devices using a different DDR protocol is presented. The apparatus includes an ONFI communication interface is for communicating with a plurality of flash memory devices and a SSD processor coupled to the communication interface. The SSD processor receives a first signal from a host device corresponding to a first DDR protocol to access DRAM, stores the first signal upon receipt in a data buffer of a plurality of data buffers resident on the apparatus, converts the first signal into a second signal using an ONFI standard, transmits the configured second signal to one of the plurality of flash memory devices corresponding to a second DDR protocol, and receives data from the flash memory device, where the data is converted into signals corresponding to the first DDR4 protocol for communication back to the host device. | 09-17-2015 |
20150262633 | DUAL-PORT DDR4-DIMMS OF SDRAM AND NVRAM FOR SSD-BLADES AND MULTI-CPU SERVERS - A memory system is disclosed that includes a first FPGA controller coupled to a first SSD cluster, a first DDR4 DIMM and a second DDR4 DIMM. A second FPGA controller is coupled to a second SSD cluster, the first DDR4 DIMM and the second DDR4 DIMM, where the first and second FPGAs are operable to share access to the first and second DDR4 DIMMs and provide connectivity to a plurality of network resources. The dual-port design enables the use of existing SDRAM, MRAM and RRAM chips at low speed rates to reach DDR4 2.0 speed DIMM devices. The dual-port DDR4 DIMM comprises 1-to-2 data buffer splitters and a DDR3 or DDR2 to DDR4 bus adaptation/termination/relaying circuits to increase (e.g., double or quadruple) the chip speed of SDRAM, MRAM, and RRAM chips. | 09-17-2015 |