Lee, Jhubei City
Cheng-Ming Lee, Jhubei City TW
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20130127338 | Drive Circuit Structure for LED Lamp Tube - A drive circuit structure for LED lamp tube is disclosed, wherein the LED lamp tube comprises a lampshade, at least an LED lamp strap and at least a drive circuit structure. The LED lamp strap is disposed inside the lampshade, and drive circuit structure connected with the LED lamp strap is disposed on any side within the lampshade. Moreover, the drive circuit structure includes multiple general-sized electronic components, at least a large-sized electronic component and a drive circuit board, wherein such general-sized electronic components are inserted on a plane of the drive circuit board, and the large-sized electronic component is disposed upright on any side of the drive circuit board. Accordingly, though the large-sized electronic component becomes voluminous, by disposing it upright on one side of the drive circuit board, it is possible to prevent the drive circuit structure from occupying larger accommodation space due to the large-sized electronic component. | 05-23-2013 |
20130128567 | Light Emitting Diode (LED) Lamp Tube Structure - An improved light emitting diode (LED) lamp tube structure, comprising a lampshade, at least an LED lamp strap installed inside the lampshade and at least a drive circuit installed on any side of the interior of the lampshade, wherein the drive circuit includes multiple electronic components and a drive circuit board, in which the electronic components are insertion installed on one side of the drive circuit board, and at least an LED is insertion installed on the other side of the drive circuit board. Therefore, when the drive circuit drives the LED lamp strap to illuminate, it also drives the LEDs insertion installed on the other side of the drive circuit board to light up at the same time so the entire lampshade can illuminate completely. | 05-23-2013 |
Chien Chen Lee, Jhubei City TW
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20130249073 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a single-layer support structure having a structure non-horizontal surface; forming a single-layer contact coplanar with the single-layer support structure, the single-layer contact having a contact non-horizontal surface; forming a single-layer insulation coplanar with the single-layer contact and horizontally between the structure non-horizontal surface and the contact non-horizontal surface; forming an upper support pad over the single-layer insulation and directly on the single-layer support structure; and mounting an integrated circuit over the upper support pad. | 09-26-2013 |
20140319695 | Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures - A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer. | 10-30-2014 |
20150041985 | Semiconductor Device and Method of Making Wafer Level Chip Scale Package - A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die. | 02-12-2015 |
Chun-Kun Lee, Jhubei City TW
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20110173381 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 07-14-2011 |
20120198142 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 08-02-2012 |
20130311713 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 11-21-2013 |
20140317341 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 10-23-2014 |
Da-Yaun Lee, Jhubei City TW
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20130149821 | Methods for a Gate Replacement Process - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process. | 06-13-2013 |
Da-Yuan Lee, Jhubei City TW
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20100052076 | METHOD OF FABRICATING HIGH-K POLY GATE DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer. | 03-04-2010 |
20100124818 | FABRICATING HIGH-K/METAL GATE DEVICES IN A GATE LAST PROCESS - The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches. | 05-20-2010 |
20110081774 | METHODS FOR A GATE REPLACEMENT PROCESS - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process. | 04-07-2011 |
20110117734 | Method of Fabricating High-K Poly Gate Device - The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer. | 05-19-2011 |
20110143529 | METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE - The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench. | 06-16-2011 |
20110147858 | METAL GATE STRUCTURE OF A FIELD EFFECT TRANSISTOR - The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance. | 06-23-2011 |
20110159678 | METHOD TO FORM A SEMICONDUCTOR DEVICE HAVING GATE DIELECTRIC LAYERS OF VARYING THICKNESSES - A method for fabricating an integrated circuit device is disclosed. An exemplary method can include providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region. | 06-30-2011 |
20110193180 | METHOD AND APPARATUS OF FORMING A GATE - The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize. | 08-11-2011 |
20110256682 | Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device - A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O | 10-20-2011 |
20110256731 | METHOD FOR FABRICATING A GATE DIELECTRIC LAYER - A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer. | 10-20-2011 |
20110266637 | Precise Resistor on a Semiconductor Device - A method includes forming a polysilicon layer on a substrate; and patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate. A first ion implantation is performed on the polysilicon resistor to adjust electric resistance of the polysilicon resistor. A second ion implantation is performed on a top portion of the polysilicon resistor such that the top portion of the polysilicon resistor has an enhanced etch resistance. An etch process is then used to remove the polysilicon gate while the polysilicon resistor is protected by the top portion. | 11-03-2011 |
20110306196 | METHOD TO FORM A SEMICONDUCTOR DEVICE HAVING GATE DIELECTRIC LAYERS OF VARYING THICKNESS - A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region. | 12-15-2011 |
20120261758 | METHOD OF FABRICATING A GATE DIELECTRIC LAYER - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate having a first active region; a first gate structure over the first active region, wherein the first gate structure comprises a first interfacial layer having a convex top surface; a first high-k dielectric over the first interfacial layer; and a first gate electrode over the first high-k dielectric. | 10-18-2012 |
20130020630 | GATE DIELECTRIC OF SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described. | 01-24-2013 |
20130026637 | METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR - An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10. | 01-31-2013 |
20130040455 | HIGH TEMPERATURE ANNEAL FOR STRESS MODULATION - A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials. | 02-14-2013 |
20130056836 | Techniques Providing Metal Gate Devices with Multiple Barrier Layers - A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers. | 03-07-2013 |
20130075827 | REPLACEMENT GATE SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device including providing a semiconductor substrate having a first opening and second opening. A dielectric layer is formed on the substrate. An etch stop layer on the dielectric layer in the first opening. Thereafter, a work function layer is formed on the etch stop layer and fill metal is provided on the work function layer to fill the first opening. | 03-28-2013 |
20130099320 | SEMICONDUCTOR DEVING HAVING METAL GATE ELECTRODE AND METHOD OF FABRICATION THEREOF - The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is formed in the first opening. A second metal gate electrode is formed the second opening while the blocking layer is in the first opening. The blocking layer is then removed from the first opening, and a first metal gate electrode formed. In embodiments, this provides for a device having a second gate electrode that includes a second work function layer and not a first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer. | 04-25-2013 |
20130102142 | STRESS MODULATION FOR METAL GATE SEMICONDUCTOR DEVICE - The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon. | 04-25-2013 |
20140004694 | METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR | 01-02-2014 |
20140091400 | Gate Dielectric Of Semiconductor Device - A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described. | 04-03-2014 |
20140295659 | METHOD OF MAKING A GATE STRUCTURE - A method of making a gate structure includes forming a trench in a dielectric layer. The method further includes forming a gate dielectric layer in the trench. The gate dielectric layer defines an opening in the dielectric layer. The method includes forming a gate electrode in the opening. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material. The first metal material has a recess. Forming the gate electrode includes filling an entire width of a top portion of the opening with a homogeneous second metal material. The homogeneous second metal material has a protrusion extending into the recess, and a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material. A top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material. | 10-02-2014 |
20150017796 | TECHNIQUES PROVIDING METAL GATE DEVICESWITH MULTIPLE BARRIER LAYERS - A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers. | 01-15-2015 |
Feng-Pin Lee, Jhubei City TW
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20130127338 | Drive Circuit Structure for LED Lamp Tube - A drive circuit structure for LED lamp tube is disclosed, wherein the LED lamp tube comprises a lampshade, at least an LED lamp strap and at least a drive circuit structure. The LED lamp strap is disposed inside the lampshade, and drive circuit structure connected with the LED lamp strap is disposed on any side within the lampshade. Moreover, the drive circuit structure includes multiple general-sized electronic components, at least a large-sized electronic component and a drive circuit board, wherein such general-sized electronic components are inserted on a plane of the drive circuit board, and the large-sized electronic component is disposed upright on any side of the drive circuit board. Accordingly, though the large-sized electronic component becomes voluminous, by disposing it upright on one side of the drive circuit board, it is possible to prevent the drive circuit structure from occupying larger accommodation space due to the large-sized electronic component. | 05-23-2013 |
20130155669 | Separate Drive Circuit Structure for LED Lamp Tube - A separate drive circuit structure for light emitting diode (LED) lamp tube, wherein the LED lamp tube comprises a lampshade and at least an LED lamp strap installed inside the lampshade, and the left and right sides of the LED lamp strap in the interior of the lampshade are respectively installed with a separate drive circuit structure. The separate drive circuit structures disposed at the two ends are connected with a transmission line such that the separate drive circuit structures disposed at the two ends together constitute a drive circuit capable of driving the LED lamp strap to illuminate. Moreover, the separate drive circuit structure can effectively reduce the tube diameter of the lampshade. | 06-20-2013 |
Hsin Chou Lee, Jhubei City TW
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20100259424 | POWER SAVING METHOD IN SLEEP MODE AND KEYBOARD CONTROLLER USING THE SAME - The invention relates to a power saving method in a sleep mode and a keyboard controller using the same. The method is adapted for a triangular-type scan keyboard controller including a plurality of input/output (I/O) pins. The method includes the steps of: providing a first clock source and a second clock source, wherein the frequency of the second clock source is much lower than the frequency of the first clock source. In a normal mode, a scan pulse is sequentially outputted from the I/O pins according to the frequency of the first clock source. In a sleep mode, the scan pulse is sequentially outputted from the I/O pins according to the frequency of the second clock source. When a specific one of the I/O pins outputs the scan pulse, the other I/O pins are used for detecting. | 10-14-2010 |
Li-Wei Lee, Jhubei City TW
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20100066312 | Overvoltage protection circuit for use in charger circuit system and charge circuit with overvoltage protection function - The present invention discloses an overvoltage protection (OVP) circuit for use in a charger circuit system, comprising: a power transistor electrically connected between a voltage supply and a battery; an OVP circuit which turns off the transistor when a voltage supply exceeds a threshold value; and a multiplexing circuit electrically connected between an output of the OVP circuit and the gate of the transistor. The present invention also discloses a charger circuit with an OVP function, comprising: a single power transistor electrically connected between a voltage supply and a battery; an OVP control circuit which turns off the power transistor when a voltage supply exceeds a threshold value; and a charger control circuit which controls the gate of the power transistor to determine a charge current to the battery when the voltage supply does not reach the threshold value. | 03-18-2010 |
Ryan Lee, Jhubei City TW
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20090206344 | System for displaying images - A system for displaying images is disclosed. The system includes a self-emitting display device including an array substrate having a pixel region. A light-emitting diode is disposed on the array substrate of the pixel region. First and second driving thin film transistors are electrically connected to a light-emitting diode. The first driving thin film transistor includes a first gate and an active layer stacked on the array substrate of the pixel region and the second driving thin film transistor includes the active layer and a second gate thereon. The first gate is coupled to a first voltage and the second gate is coupled to a second voltage different from the first voltage during the same frame. | 08-20-2009 |
Te-Wei Lee, Jhubei City TW
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20120044383 | HIGH RESOLUTION DIGITAL IMAGE CAPTURING APPARATUS AND REFERENCE PIXEL MEMORY STORAGE SPACE CONFIGURATION METHOD - A reference pixel memory storage space configuration method for configuring a main storage sub-space and an extra storage sub-space of a reference pixel memory storage space of a high resolution digital image capturing apparatus is disclosed. The method includes steps of: calculating a first frame to obtain a plurality of first reconstruction reference pixels; storing the first reconstruction reference pixels in the main storage sub-space; moving a search range window to search the first reconstruction reference pixels and calculating a second frame by referencing the first reconstruction reference pixels covered by the search range window to obtain a plurality of second reconstruction reference pixels, and when the search range window is moved from a first region to a second region in the main storage sub-space, the first region becomes an available space. The second reconstruction reference pixels are orderly stored in the extra storage sub-space and the available space. | 02-23-2012 |
Te-Yu Lee, Jhubei City TW
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20100181574 | THIN FILM TRANSISTOR DEVICES WITH DIFFERENT ELECTRICAL CHARACTERISTICS AND METHOD FOR FABRICATING THE SAME - A system for displaying images. The system includes a thin film transistor (TFT) device including a first insulating layer covering a first region and a second region of a substrate. A first polysilicon active layer is disposed in the first region and between the substrate and the first insulating layer. A second polysilicon active layer is disposed on the first insulating layer in the second region. A polysilicon gate layer is disposed above the first polysilicon active layer. A second insulating layer covers the polysilicon gate layer and the second polysilicon active layer. A metal gate layer is disposed above the second polysilicon active layer. A method for fabricating the system for displaying images including the TFT device is also disclosed. | 07-22-2010 |
20100270541 | SYSTEM FOR DISPLAY IMAGES AND FABRICATION METHOD THEREOF - A system for displaying images including a display panel and a fabrication method thereof are provided. The display panel includes a substrate having a first, second and third areas, a first patterned semiconductor layer disposed over the first area of the substrate, a first insulating layer covering the first patterned semiconductor layer and the first, the second and the third areas of the substrate, a second patterned semiconductor layer disposed on the first insulating layer of the first and the third areas respectively, a second insulating layer covering the second patterned semiconductor layer and the first insulating layer, and a patterned conductive layer disposed on the second insulating layer to form a first thin-film transistor at the first area and a second thin-film transistor at the third area. | 10-28-2010 |
20100271349 | THIN FILM TRANSISTOR DEVICES FOR OLED DISPLAYS AND METHOD FOR FABRICATING THE SAME - A system for displaying images. The system includes a thin film transistor (TFT) device including a first gate layer disposed on a first region of a substrate and covered by a first insulating layer. A first polysilicon active layer is disposed on the first insulating layer and a second polysilicon layer is disposed on a second region of the substrate. A second insulating layer covers both of the first and second polysilicon gate layers. Second and third gate layers are respectively disposed on the second insulating layer above the first and second polysilicon active layers. A method for fabricating a system for displaying images including the TFT device is also disclosed. | 10-28-2010 |
Tung-Li Lee, Jhubei City TW
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20100247773 | ALLOY SUSCEPTOR WITH IMPROVED PROPERTIES FOR FILM DEPOSITION - Provided is a method for processing a wafer that includes providing an alloy susceptor including an exterior surface and a wafer contact surface. The exterior surface of the alloy susceptor is treated to produce a roughness of the exterior surface. The roughened exterior surface of is coated with a ceramic material. The alloy susceptor including the ceramic-coated roughened exterior surface is positioned in a wafer process chamber. A plurality of layers of a film are deposited on the ceramic-coated roughened exterior surface of the alloy susceptor, wherein a first adhesion exists between the plurality of layers of the film and the ceramic material coated on the roughened exterior surface of the alloy susceptor that is greater than a second adhesion that would exist between the plurality of layers of the film and a non-roughened exterior surface of the alloy susceptor without the ceramic material. | 09-30-2010 |
Yu Lin Lee, Jhubei City TW
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20150009651 | LED Lamp - A LED lamp is provided. The LED lamp includes a tube and a plurality of LED light bar. The tube has a placement surface, and these LED light bar are disposed on the placement surface. Each LED light bar includes a circuit board and a plurality of LED lights, and these LED light is disposed on the circuit board. The LED light bar is mounted on the placement surface in a detachable manner. | 01-08-2015 |