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| 20090321948 | METHOD FOR STACKING DEVICES - A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process. | 12-31-2009 |
| 20100279463 | METHOD OF FORMING STACKED-DIE PACKAGES - A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer. | 11-04-2010 |
| 20130127049 | Method for Stacking Devices and Structure Thereof - A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material continuously extending over the first device and covering the first TSV structure, a second device disposed over the first device and within the first coating material, the second device includes a second TSV structure and a plurality of conductive bumps, the plurality of conductive bumps are positioned within the first coating material, a second coating material disposed over the second device, the second coating material continuously extends over the second device and covers the second TSV structure, and a third device disposed over the second coating material, the third device includes a third TSV structure. | 05-23-2013 |
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| 20100330321 | COVER LAYER FOR PRINTED CIRCUIT BOARD - The present invention provides a cover layer for a printed circuit board. The cover layer includes a first polymer layer, a second polymer layer and a light-reflecting layer disposed between the first and second polymer layers and having a thickness being 0.5 to 10 micro meters. Due to the light-reflecting layer, the cover layer of the present invention has high reflection rate and great flexibility suitable for a flexible printed circuit board. | 12-30-2010 |
| 20110086192 | COVER LAYER FOR PRINTED CIRCUIT BOARD - The present invention provides a cover film for a printed circuit board. The cover film includes an adhesive layer; a core layer made of a polymer; and a composite material layer formed on the core layer, comprising epoxy resin, a black material selected from the group consisting of a black pigment, carbon powder, nano carbon tube and a combination thereof, and an additive selected from the group consisting of titanium dioxide, boron nitride, barium sulfate and a combination thereof, wherein the core layer is disposed between the adhesive layer and the composite material layer, and the adhesive layer and the composite material layer have the same thickness or have a thickness difference being no more than 15 micro meters. The cover film of the preset invention is capable of shielding circuit patterns and has great folding endurance, and is thus applicable to flexible printed circuit boards. | 04-14-2011 |
| 20110114371 | COMPOSITE DOUBLE-SIDED COPPER FOIL SUBSTRATES AND FLEXIBLE PRINTED CIRCUIT BOARD STRUCTURES USING THE SAME - A double-sided copper foil substrate, which comprises: a polymer layer; a first copper foil; an adhesive layer formed on the polymer layer such that the polymer layer is sandwiched between the adhesive layer and the first copper layer; and a second copper foil causing the adhesive layer to be sandwiched between the second copper foil and the polymer layer, wherein the polymer layer and the adhesive layer have a total thickness of from 12 to 25 μm. The present invention further provides a flexible printed circuit board structure utilizing the composite double-sided copper foil substrate of the present invention, wherein the second double-sided copper foil substrate has a trench for exposing a portion of the adhesive layer. The double-sided copper foil substrate of the present invention are lower in rebound and satisfying the demand for the greater number of bending and sliding cycles under a lower R angle, and particularly is suitable for thin and flexible electronic products. | 05-19-2011 |
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| 20110029992 | Casing assembling structure of optical disc drive - A casing assembling structure of an optical disc drive is provided to comprise a bottom cover; a top cover combined with the bottom cover to form a space, wherein the top cover has a first side wall and a fixing portion, which is extended from the first side wall and is positioned under the bottom cover; and a first screw screwed on the fixing portion, wherein the top cover, the first side wall and the fixing portion are formed as a integral. | 02-03-2011 |
| 20110219388 | Slim Optical Disc Drive - The present invention discloses a slim optical disc drive comprising a case with an upper cover and a lower cover, a disc tray for loading and unloading an optical disc, a first circuit board disposed on the lower cover, a second circuit board disposed on the disc tray, and a flexible flat cable for connecting the first circuit board and the second circuit board. The flexible flat cable comprises a fixed portion and a movable portion, and a patch is adhered to the movable portion of the flexible flat cable. The patch has a first end and a second end, and the width of the first end is larger than that of the second end. | 09-08-2011 |
| 20120110605 | Optical Disc Drive - An optical disc drive is provided to comprise a main circuit board; an optical pickup head, electrically connected to the main circuit board for reading data from an optical disc and for writing a label side of the optical disc; an spindle motor module, electrically connected to the main circuit board through a first flexible flat cable for supporting and rotating the optical; and a spoke detecting module, electrically connected to the main circuit board through a second flexible flat cable for detecting a spoke pattern formed on inner radius of the label side of the optical disc. | 05-03-2012 |
| 20130125151 | OPTICAL DISK DRIVE - An optical disk drive including a case, a traverse, a guide rod, an optical pick-up head and at least a locking member is provided. The traverse is disposed in the case and includes at least a cantilever part and at least a locking hole. The cantilever part protrudes from a carrying surface of the traverse and is integrated with the traverse. The guide rod leans against a bearing end of the cantilever part. The optical pick-up head is slidably disposed on the guide rod. The locking member includes a leaning part and a locking part. The locking part is locked into the locking hole and the leaning part presses an upper side of an end of the guide rod for making the bearing end generate a bending displacement toward the carrying surface through the guide rod. | 05-16-2013 |
| 20130185741 | SLIM-TYPE OPTICAL DISC DRIVE - A slim-type optical disc drive includes a casing and a tray. A first circuit board is disposed within the casing. A second circuit board is disposed on the tray. A spring switch is disposed on the second circuit board. A first end of the spring switch is fixed on the second circuit board. A resistor is connected between the first end of the spring switch and a first power source. A second end of the spring switch is extended outside the second circuit board. In a tray-out status, the second end of the spring switch is not contacted with any object, so that a first status signal is generated. In a tray-in status, the second end of the spring switch is contacted with a conducting zone of a second power source, so that a second status signal is generated. | 07-18-2013 |
| 20130283300 | TRAY LOCKING DEVICE OF OPTICAL DISC DRIVE - A tray locking device of an optical disc drive adapted to lock and release a tray is provided. The optical disc drive has an optical head engaged with a lead screw and driven to move by the lead screw. The tray locking device includes a pushing member disposed on the optical head, a latching hook for latching and releasing a pin, and a transmission assembly disposed between the pushing member and the latching hook. The transmission assembly includes first and second lever elements. The first lever element pivoted in the tray has a slide slot having a first protrusion portion therein. The second lever element has a second protrusion portion adapted to move within the slide slot. When the tray is to be ejected, the lead screw drives the pushing member to push the second lever element, such that the second protrusion portion is aligned with the first protrusion portion. | 10-24-2013 |
| 20130298144 | TRAY LOCKING DEVICE FOR OPTICAL DISC DRIVE - A tray locking device adapted to an optical disc drive for locking and releasing a tray is provided. The optical disc drive has an optical head connected to a lead screw and driven to move by the lead screw. The tray locking device includes a pushing member driven to move by the lead screw, a latching hook for locking and releasing a protruding pin, and a transmission assembly configured between the pushing member and the latching hook. The transmission assembly includes a first rod and a second rod movably configured in the tray. The first rod has a first driving portion, and the second rod has a second driving portion. When the transmission assembly is located at an initial position, the first driving portion is located on a moving path of the pushing member, while the second driving portion is not located on the moving path of the pushing member. | 11-07-2013 |
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| 20080270771 | METHOD OF OPTIMIZING MULTI-SET CONTEXT SWITCH FOR EMBEDDED PROCESSORS - A method of optimizing multi-set context switch for embedded processors includes the steps of partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the registers, storing contents of first target registers according to live set information of a current task, wherein the first target registers are selected from the register sets, determining a next task by an operating system and updating the live set information according to the next task, and restoring contents of second target registers according to the updated live set information, wherein the second target registers are selected from the register sets. | 10-30-2008 |
| 20100037037 | METHOD FOR INSTRUCTION PIPELINING ON IRREGULAR REGISTER FILES - A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned to the same local register file. The virtual registers of the instructions that have data dependency across the first functional unit and the second functional unit are assigned to a global register file. The instructions are then modulo scheduled based on a current value of initial interval. The virtual registers of the scheduled instructions are allocated to the corresponding register files. If the allocation fails, a set of virtual registers is transferred from the first or second register file to the global register file. | 02-11-2010 |
| 20110087922 | TEST METHOD AND TOOL FOR MASTER-SLAVE SYSTEMS ON MULTICORE PROCESSORS - A test method for a master-slave concurrent system running on a multicore processor includes the steps of establishing a PFA, otherwise called probabilistic finite automata, or probabilistic finite state machine, for a given regular expression; generating test patterns by running the PFA; splitting and merging the test patterns to generate an interleaved test pattern; and performing test on the master-slave system according to the interleaved test pattern. In an embodiment, the method further includes a step of debugging failures of the multicore processor during testing. | 04-14-2011 |
| 20120159110 | METHOD FOR ALLOCATING REGISTERS FOR A PROCESSOR BASED ON CYCLE INFORMATION - A method of allocating registers for a processor based on cycle information is disclosed. The processor comprises a first cluster and a second cluster. Each cluster comprises a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment are performed to take full advantage of the properties of a processor as well as cycle information. | 06-21-2012 |
| 20130024666 | METHOD OF SCHEDULING A PLURALITY OF INSTRUCTIONS FOR A PROCESSOR - A method of scheduling a plurality of instructions for a processor comprises the steps of: establishing a functional unit resource table comprising a plurality of columns, each of which corresponds to one of a plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a functional unit of the processor; establishing a ping-pong resource table comprising a plurality of columns, each of which corresponds to one of the plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a read port or a write port of a register bank of the processor; and allotting the plurality of instructions to the plurality of operation cycles of the processor and registering the functional units and the ports of the register banks corresponding to the allotted instructions on the functional unit resource table and the ping-pong resource table. | 01-24-2013 |
| 20130061022 | COMPILER FOR PROVIDING INTRINSIC SUPPORTS FOR VLIW PAC PROCESSORS WITH DISTRIBUTED REGISTER FILES AND METHOD THEREOF - A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations. | 03-07-2013 |
| 20130191818 | PROBABILISTIC POINTER ANALYSIS METHOD USING SSA FORM - A computer-implemented probabilistic pointer analysis method using SSA form comprises the steps of: evaluating a program in an SSA form comprising a target pointer to determine pointer relations between the target pointer, a plurality of aliased pointers related to the target pointer and at least a probable location of the target pointer; and generating a direct probabilistic relation between the target pointer and the at least a probable location of the target pointer according to the pointer relation. | 07-25-2013 |
| 20140344791 | METHOD AND APPARATUS FOR CODE SIZE REDUCTION - A method for code size reduction, which comprises determining basic blocks in an IR module; grouping the basic blocks having duplicate code into groups; providing weighting values corresponding to different instructions of the module, wherein the weighting values are determined based on a plurality of intermediate representation program codes; determining a weighted size of the module, wherein the weighted size of the module is determined by summing weighted sizes of the basic blocks of the module, and the weighted size of each basic block is determined by summing products of numbers of different instructions of the basic blocks and the corresponding weighting values; removing duplicates in one group to obtain a module having one processed group; determining a weighted size of the module having one processed group; and comparing the weighted size of the module to the weighted size of the module having one processed group. | 11-20-2014 |
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| 20100289057 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD, SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). | 11-18-2010 |
| 20120069479 | POWER TRANSISTOR DEVICE WITH ELECTROSTATIC DISCHARGE PROTECTION AND LOW DROPOUT REGULATOR USING SAME - The present invention discloses a power transistor device and a low dropout regulator (LDO) with electrostatic discharge protection. The power transistor device includes: a P-type metal oxide semiconductor (PMOS) field effect transistor (FET), having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal respectively; and an electrostatic discharge protection device, electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path to protect the PMOSFET. | 03-22-2012 |
| 20130084680 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD, SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). | 04-04-2013 |
| 20140299913 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type. | 10-09-2014 |
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| 20080296761 | Cylindrical Bonding Structure and method of manufacture - A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder. | 12-04-2008 |
| 20080315424 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 12-25-2008 |
| 20090008778 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 01-08-2009 |
| 20090011542 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 01-08-2009 |
| 20090104769 | Semiconductor chip with coil element over passivation layer - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer. | 04-23-2009 |
| 20090289346 | Structure and manufacturing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 11-26-2009 |
| 20110233776 | SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer. | 09-29-2011 |
| 20120098128 | CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME - A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers. | 04-26-2012 |
| 20130221512 | STRUCTURE AND MANUFACTURING METHOD OF CHIP SCALE PACKAGE - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 08-29-2013 |
| 20130309812 | INTEGRATED CHIP PACKAGE STRUCTURE USING CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry. | 11-21-2013 |
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| 20090167975 | Liquid Crystal Display Unit Structure and Manufacturing Method Thereof - A liquid crystal display unit structure and the manufacturing method thereof are provided. The method comprises the following steps: forming a patterned first metal layer with a first data line segment and a lower gate pad on a substrate; forming a patterned dielectric layer covering the first data line and the lower gate pad having a plurality of first openings and a second opening therein, forming a patterned second metal layer including a common line, a second data line segment and a upper gate pad, wherein the upper gate pad is electrically connected to the lower gate pad through the first openings, and the second data line segment is electrically connected to the first data line segment through the first openings; finally forming a patterned passivation layer and a patterned transparent conductive layer. | 07-02-2009 |
| 20110165725 | Pixel Structure and Method for Fabricating the Same - A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on the first insulation layer and overlapped with the first data line, a second data line formed on the first insulation layer and electrically connected to the exposed end of the first data line, a second insulation layer overlying the shielding electrode and the second data line, and a pixel electrode formed on the second insulation layer and overlapped with the shielding electrode. The invention also provides a method for fabricating the pixel structure. | 07-07-2011 |
| 20120218489 | Liquid Crystal Display Unit Structure Including a Patterned Etch Stop Layer Above a First Data Line Segment - A liquid crystal display unit structure and the manufacturing method thereof are provided. The liquid crystal display unit structure comprises a patterned first metal layer with a first data line segment and a gate line on a substrate; a patterned dielectric layer covering the first data line and the gate line having a plurality of first openings and a second opening therein, a patterned etch stop layer having a first portion located above the first data line segment and a second portion; a patterned second metal layer including a common electrode line, a second data line segment, a source electrode and a drain electrode, wherein the first portion of the patterned etch stop layer is between the first data line segment and the common line; a patterned passivation layer and a patterned transparent conductive layer. | 08-30-2012 |
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| 20110063434 | Monitor system for monitoring riverbed elevation change at bridge pier - A monitor system for monitoring riverbed elevation changes at bridge piers is revealed. The monitor system includes a container, a rail, a holder, a photographic unit, a processor and a transmission unit. The container is disposed at a pier under the water and the rail is mounted in the container. The holder is arranged at the rail and is moved on the rail. The photographic unit is disposed on the holder to capture a monitor image of a riverbed under the water. As to the processor, it processes the monitor image so as to learn elevation change of the riverbed under the water. By the transmission unit, the riverbed elevation change is sent to a remote monitor unit so as to get the riverbed elevation according to the riverbed elevation change. Thus the riverbed elevation change at the bridge pier is monitored in real time. | 03-17-2011 |
| 20110242309 | MULTI-LENS MONITORING SYSTEM FOR BED ELEVATION AROUND A PIER - The present invention relates to a multi-lens monitoring system for bed elevation around a pier according to the present invention comprises a container, a holder, a plurality of photographing units, and a processing module. The container is disposed on the pier; the holder is disposed inside the container; and the plurality of photographing units are disposed on the holder for photographing the bed under water and producing a monitoring image. The processing module is used for activating one of the plurality of photographing units for photographing the bed under water. The processing module also analyzes the monitoring image, gives the elevation variation of the bed, and transmits the elevation variation of the bed to a remote monitoring unit for real-timely monitoring and recording. During the monitoring process, the processing module will change activating one of the plurality of photographing units according to the monitoring image, and hence the electrical power can be saved. | 10-06-2011 |
| 20110255735 | PROBE MONITORING SYSTEM FOR RIVERBED ELEVATION MONITORING AT BRIDGE PIERS - A probe monitoring system for riverbed elevation monitoring at bridge piers is revealed. The system includes a housing, a measuring rod, a moving member, a control module, a photographic unit and a sensing unit. The housing is fixed on the pier. Both the moving member for driving the measuring rod and the control module for control of the moving member are mounted in the housing. When the control module drives the measuring rod to move downward and the sensing unit on the bottom of the measuring rod approaches the riverbed, a sensing signal is sent to the control module. Thus the moving member stops moving the measuring rod and the photographic unit takes pictures of the measuring rod to generate an image. Then the riverbed elevation is obtained according to the image or the movement of the moving member and is sent to a remote monitor unit for real-time monitoring. | 10-20-2011 |
| 20110293156 | METHOD AND COMPUTER FOR AIDING DETERMINATION OF OBSTRUCTIVE SLEEP APNEA - A computer for aiding determination of Obstructive Sleep Apnea (OSA) includes a storage device storing with a medical image and a central processing unit (CPU). The CPU executes a method for aiding determination of OSA. The method for aiding determination of OSA includes the following steps. The medical image is obtained. An upper airway model is established. A narrowest cross-section and a nasopharyngeal boundary cross-section are defined in the airway model. A cross-sectional area of the narrowest cross-section and a cross-sectional area of the nasopharyngeal boundary cross-section are calculated. A stenosis rate is calculated according to the cross-sectional area of the narrowest cross-section and the cross-sectional area of the nasopharyngeal boundary cross-section. The stenosis rate is provided. In addition, in the method for aiding determination of OSA, a respiratory flow field simulation may be further performed to obtain and provide a flow field pressure distribution of the upper airway model. | 12-01-2011 |
| 20130103375 | METHOD FOR ASSISTING IN DETERMINING STRENGTH OF FIXING CRANIOFACIAL SURGERY PATCH AND COMPUTER USING THE SAME - A computer for assisting in determining the strength of fixing a craniofacial surgery patch comprises a storage device for storing a medical image and a central processing unit, the central processing unit carry out a method for assisting in determining the strength of fixing a craniofacial surgery patch. The method includes obtaining a medical image; establishing a skull model according to the medical image; receiving a patch setting command, and disposing a patch model on the skull model according to the patch setting command; generating an internal grid mesh data of the skull model disposed with the patch model; executing a biomechanical simulation of a patch structural strength according to the skull model disposed with the patch model, the internal grid mesh data and a boundary condition; and providing a stress distribution, a strain distribution or a displacement distribution of the patch model to assist in determining. | 04-25-2013 |
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| 20090240862 | System Design for a Digital Electronic Sign Board - A system design for a digital electronic sign board comprises a main circuit module, an adapter module and a computer module; wherein the adapter module is fixed between the main circuit module and the computer module. The main circuit module and the adapter module are fixed in the digital electronic sign board. The computer module is externally inserted into the digital electronic sign board. Therefore the computer module and the main circuit module are electrically connected through the adapter module. The system design of the present invention removable and attached the computer module with the main circuit module. As a result, when a maintenance worker needs to perform maintenance on the computer module, he or she can conveniently pull out the computer module from the digital electronic sign board and insert the computer module back to the digital electronic sign board after maintenance is done so as to improve the efficiency and quality of maintenance. | 09-24-2009 |
| 20120081853 | MEDICAL ANTIBACTERIAL FULL-FLAT TOUCH SCREEN - A medical antibacterial full-flat touch screen comprises an antibacterial housing, an antibacterial rubber strip and an antibacterial full-flat panel, wherein a recessed edge is configured around the periphery at the bottom of the antibacterial rubber strip which recessed edge encompassing the periphery of the antibacterial full-flat panel, and a plurality of upright buckle holes are configured on the inner side of the periphery of the antibacterial full-flat panel. In addition, a groove is configured around the periphery at the top of the antibacterial rubber strip such that the antibacterial housing can be directly inserted into the groove, and a plurality of bumps configured on the inner side of the antibacterial housing can be positioned into the upright buckle holes thereby allowing the antibacterial housing and the antibacterial full-flat panel to combine together. Furthermore, the antibacterial rubber strip closely joined between the antibacterial housing and the antibacterial full-flat panel can effectively prevent the breeding of bacteria inside the gap of the assembled body and the infiltration of any liquid into the body as well. | 04-05-2012 |
| 20120084728 | BUTTON CONTROL SYSTEM FOR MEDICAL TOUCH SCREEN AND METHOD THEREOF - A button control system for medical touch screen and method thereof comprises a central control module, a touch signal input module, a lock time control module, a button lock module, a button unlock module and a cleanse display module, wherein the central control module determines the signal inputted by the touch signal input module, and selects to control the button lock module or the button unlock module thereby locking or unlocking a touch button; furthermore, the lock time control module is configured to set up the lock time for the touch button so as to preset the lock time of the touch button as cleansing the touch screen by the user, and after pressing down the cleanse touch button on the touch screen, it allows to control to lock or unlock other touch buttons and also to effectively prevent the occurrence of the situation where the screen button is erroneously touched as performing the cleanse process. | 04-05-2012 |
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| 20100109028 | Vertical ACLED structure - This application related to an opto-electrical device, comprising a first ACLED having a first n-type semiconductor layer, a first light emitting layer, a first p-type semiconductor layer, a first p-type electrode and a first n-type electrode; a second ACLED having a second n-type semiconductor layer, a second light emitting layer, a second p-type semiconductor layer, a second p-type electrode and a second n-type electrode, wherein each of the first ACLED and the second ACLED are vertical stack structure and is connected in anti-parallel manner. | 05-06-2010 |
| 20100283062 | OPTOELECTRONIC SYSTEM - An embodiment of the invention discloses an optoelectronics system and a method of making the same. The method includes steps of providing a temporary substrate; providing un-packaged optoelectronic elements on the temporary substrate; forming a trench between two of the un-packaged optoelectronic elements; providing an adhesive material to fill the trench and cover the optoelectronic elements; providing a permanent substrate on the adhesive material; and removing the temporary substrate. | 11-11-2010 |
| 20120018745 | INTEGRATED LIGHTING APPARATUS AND METHOD OF MANUFACTURING THE SAME - An integrated lighting apparatus includes at least a lighting device, a control device comprising an integrated circuit, and a connector that is used to electrically connect the lighting device and the control device. With the combination, the integrated circuit drives the lighting device in accordance with its various designed functionality, thus expands applications of the integrated lighting apparatus. | 01-26-2012 |
| 20120132944 | LIGHT-EMITTING DEVICE, LIGHT MIXING DEVICE AND MANUFACTURING METHODS THEREOF - Disclosed is a light-emitting device comprising: a carrier; a light-emitting element disposed on the carrier; a first light guide layer covering the light-emitting element, and disposed on the carrier; a wavelength conversion and light guide layer covering the first light guide layer and the light-emitting element, and disposed on the carrier; and a low refractive index layer disposed between the first light guide layer and the wavelength conversion and light guide layer; wherein the first light guide layer comprises a gradient refractive index, the wavelength conversion and light guide layer comprises a dome shape structure and is used to convert a wavelength of light emitted from the light-emitting element and transmit light, and the low refractive index layer is used to reflect light from the wavelength conversion and light guide layer. | 05-31-2012 |
| 20130120999 | ILLUMINATION APPARATUS - This disclosure discloses an illumination apparatus. The illumination apparatus comprises an inner cover comprising a top surface having a first length; a pedestal on which the inner cover is disposed comprising a top surface having a second length; and a holder supporting the pedestal; wherein the first length is greater than the second length. | 05-16-2013 |
| 20130121002 | ILLUMINATION APPARATUS - This disclosure discloses an illumination apparatus. The illumination apparatus comprises a cover comprising a second portion and a first portion, and a light source disposed within the cover. An average thickness of the first portion is greater than that of the second portion. | 05-16-2013 |
| 20130256729 | LIGHT-EMITTING DEVICE - Disclosed is a light-emitting device comprising: a light-emitting stack with a length and a width comprising: a first conductivity type semiconductor layer; an active layer on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer on the active layer; a conductive layer with a width greater than the width of the first conductivity type semiconductor layer and under the first conductivity type semiconductor layer, the conductive layer comprising a first overlapping portion which overlaps the first conductivity type semiconductor layer and a first extending portion which does not overlap the first conductivity type semiconductor layer; a transparent conductive layer with a width greater than the width of the second conductivity type semiconductor layer over the second conductivity type semiconductor layer, the transparent conductive layer comprising a second overlapping portion which overlaps the second conductivity type semiconductor layer and a second extending portion which does not overlap the second conductivity type semiconductor layer; a first electrode substantially joined with only the first extending portion or a part of the first extending part; and a second electrode substantially joined with only the second extending portion or a part of the second extending portion. | 10-03-2013 |
| 20130313594 | OPTOELECTRONIC ELEMENT AND MANUFACTURING METHOD THEREOF - An optoelectronic element includes an optoelectronic unit having a first top surface; a first metal layer on the first top surface; a first transparent structure surrounding the optoelectronic unit and exposing the first top surface; and a first contact layer on the first transparent structure, including a connective part electrically connected with the first metal layer. | 11-28-2013 |
| 20140034988 | MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE AND LIGHT MIXING DEVICE - Disclosed is a light-emitting device comprising: a carrier; a light-emitting element disposed on the carrier; a first light guide layer covering the light-emitting element; a second light guide layer covering the first light guide layer; a low refractive index layer between the first light guide layer and the second light guide layer to reflect the light from the second light guide layer; and a wavelength conversion layer covering the second light guide layer; wherein the low refractive index layer has a refractive index smaller than one of the refractive indices of first light guide layer and the second light guide layer. | 02-06-2014 |
| 20140070250 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment of the present application comprises a substrate; a first semiconductor light-emitting structure formed on the substrate, wherein the first semiconductor light-emitting structure comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and a first active layer formed between the first semiconductor layer and the second semiconductor layer, wherein the first active layer is capable of emitting a first light having a first dominant wavelength; and a first thermal-sensitive layer formed on a path of the first light, wherein the first thermal-sensitive layer comprises a material characteristic which varies with a temperature change. | 03-13-2014 |
| 20140361319 | INTERGRATED LIGHTING APPARATUS AND METHOD OF MANUFACTURING THE SAME - An integrated lighting apparatus comprises a first control device including a semiconductor substrate, an integrated circuit block formed above a first portion of the semiconductor substrate, and a plurality of power pads formed above the integrated circuit block; a first light emitting device formed above a second portion of the semiconductor substrate; and a through plug passing through the semiconductor substrate for electrically connecting the first control device and the first light emitting device. | 12-11-2014 |
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| 20100015814 | MOSFET Device With Localized Stressor - MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer. | 01-21-2010 |
| 20100075480 | STI STRESS MODULATION WITH ADDITIONAL IMPLANTATION AND NATURAL PAD SIN MASK - A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation. | 03-25-2010 |
| 20100291751 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void. | 11-18-2010 |
| 20100323494 | NARROW CHANNEL WIDTH EFFECT MODIFICATION IN A SHALLOW TRENCH ISOLATION DEVICE - A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation. | 12-23-2010 |
| 20110049567 | BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess. | 03-03-2011 |
| 20110263092 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The present disclosure discloses an exemplary method for fabricating a semiconductor device comprises selectively growing a material on a top surface of a substrate; selectively growing a protection layer on the material; and removing a portion of the protection layer in an etching gas. | 10-27-2011 |
| 20120012047 | METHOD OF TEMPERATURE DETERMINATION FOR DEPOSITION REACTORS - A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer. | 01-19-2012 |
| 20120168821 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate. | 07-05-2012 |
| 20130082309 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity. | 04-04-2013 |
| 20130084682 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity. | 04-04-2013 |
| 20130122675 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle. | 05-16-2013 |
| 20130171803 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide. | 07-04-2013 |
| 20130244389 | STRAINED SEMICONDUCTOR DEVICE WITH FACETS - A method for fabricating a semiconductor device, the method includes forming a gate stack over a major surface of a substrate. The method further includes recessing the substrate to form source and drain recess cavities adjacent to the gate stack in the substrate. The method further includes selectively growing a strained material in the source and drain recess cavities in the substrate using an LPCVD process, wherein the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiH | 09-19-2013 |
| 20130252189 | Wafer Holder With Varying Surface Property - An apparatus, a system and a method are disclosed. An exemplary apparatus includes a first portion configured to hold an overlying wafer. The first portion includes a central region and an edge region circumscribing the central region. The first portion further including an upper surface and a lower surface. The apparatus further includes a second portion extending beyond an outer radius of the wafer. The second portion including an upper surface and a lower surface. The lower surface of the first portion in the central region has a first reflective characteristic. The lower surface of the first portion in the edge region and the second portion have a second reflective characteristic. | 09-26-2013 |
| 20130252424 | WAFER HOLDER WITH TAPERED REGION - An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness. | 09-26-2013 |
| 20140170319 | INJECTOR FOR FORMING FILMS RESPECTIVELY ON A STACK OF WAFERS - An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided. | 06-19-2014 |
| 20140367768 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution. | 12-18-2014 |
| 20150079750 | TILT IMPLANTATION FOR FORMING FINFETS - Methods for fabrication of fin devices for an integrated circuit are provided. Fin structures are formed in a semiconductor material, where the fin structures include sidewalls and tops. Dopant implantation is performed at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, where the semiconductor material is maintained at an elevated temperature during the dopant implantation. The elevated temperature prevents amorphization of the fin structures during the dopant implantation. A field effect transistor is formed from the fin structures. The field effect transistor has a threshold voltage that is based on the dopant implantation. | 03-19-2015 |
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| 20090111205 | Method of seperating two material systems - An embodiment of this invention discloses a method of separating two material systems, which comprises steps of providing a bulk sapphire; forming a nitride system on the bulk sapphire; forming at least two channels between the bulk sapphire and the nitride system; etching at least one inner surface of the channel; and separating the bulk sapphire and the nitride system. | 04-30-2009 |
| 20100084679 | LIGHT-EMITTING DEVICE - A light-emitting device having a substrate, a light-emitting stack, and a transparent connective layer is provided. The light-emitting stack is disposed above the substrate and comprises a first diffusing surface. The transparent connective layer is disposed between the substrate and the first diffusing surface of the light-emitting stack; an index of refraction of the light-emitting stack is different from that of the transparent connective layer. | 04-08-2010 |
| 20100314991 | LIGHT-EMITTING DEVICE HAVING A PATTERNED SUBSTRATE AND THE METHOD THEREOF - This disclosure provides a light-emitting device including a patterned substrate and the manufacturing method thereof. The patterned substrate has a plurality of depressions and/or extrusions for scattering light emitted from a light-emitting layer. Each of the plurality of depressions and/or extrusions comprises a top portion, a bottom portion, and a sidewall portion enclosing the top portion and the bottom portion, and at least part of the sidewall portion comprises a curve. In a preferred embodiment, the light-emitting device further comprises a rough surface formed on at least one of the top portion, the bottom portion, and the sidewall portion. | 12-16-2010 |
| 20130009188 | LIGHT-EMITTING DEVICE HAVING A PATTERNED SUBSTRATE AND THE METHOD THEREOF - This disclosure provides a light-emitting device including a patterned substrate and the manufacturing method thereof. The patterned substrate has a plurality of depressions and/or extrusions for scattering light emitted from a light-emitting layer. Each of the plurality of depressions and/or extrusions comprises a top portion, a bottom portion, and a sidewall portion enclosing the top portion and the bottom portion, and at least part of the sidewall portion comprises a curve. Ina preferred embodiment, the light-emitting device further comprises a rough surface formed on at least one of the top portion, the bottom portion, and the sidewall portion. | 01-10-2013 |
| 20140306253 | Light Emitting Device - This disclosure relates to a light-emitting apparatus comprising a submount, a chip carrier formed on the submount, a light-emitting chip formed on the chip carrier, a reflecting cup formed on the submount and enclosing the light-emitting chip and the chip carrier, and a transparent encapsulating material for encapsulating the light-emitting chip. | 10-16-2014 |
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| 20110122729 | Controlling Method for Ultra-sound Sensor - A controlling method for ultra-sound sensor is provided. The method includes the steps of measuring a distance of an obstacle, determining whether the distance is smaller than a distance threshold, and adjusting a driving voltage if the distance is smaller than the distance threshold. | 05-26-2011 |
| 20110133653 | ULTRASONIC LAMP AND CONTROL METHOD THEREOF - An ultrasonic lamp control method is provided. The control method includes the following steps. The ultrasonic lamp emits a first burst, and detects whether a first echo is received within a fixed period of time after the emission of the first burst. If the first echo is received within the fixed period of time, then the ultrasonic lamp neglects the first echo and emits a second burst. The ultrasonic lamp detects whether a second echo is received within the fixed period of time after the emission of the second burst. If the second echo is received within the fixed period of time, then the ultrasonic lamp enters a control mode. | 06-09-2011 |
| 20110134725 | ULTRASONIC SYSTEM AND COMMUNICATION METHOD THEREOF - An ultrasonic system including an ultrasonic transmitter and an ultrasonic receiver is provided. The ultrasonic transmitter emits a transmission signal, which includes a synchronous burst and multiple data bursts. The ultrasonic receiver receives a synchronous echo, and determines whether the amplitude of the synchronous echo is larger than a first threshold. If the amplitude of the synchronous echo is larger than the first threshold, then the ultrasonic receiver interprets the multiple data echoes corresponding to the data bursts to obtain a digital signal. | 06-09-2011 |
| 20140133240 | SOLID STATE STORAGE DEVICE WITH SLEEP CONTROL CIRCUIT - A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode. | 05-15-2014 |
