Patent application number | Description | Published |
20100012596 | APPARATUS AND METHOD FOR FILTERING A MATERIAL FROM A LIQUID MEDIUM - An apparatus for filtering a material from a medium includes a first housing having a wall with a plurality of openings formed therein, a conveyor disposed in the housing for moving the material therealong, and a conduit line communicating with the interior of the housing for supplying the medium to the apparatus. At least one of the first housing and the conveyor rotate relative to a central axis to direct the medium toward the wall so as to separate the material from the medium. A method for filtering a material from a medium includes supplying the medium to a first housing, spinning the medium within the housing, passing the medium through a wall of the housing to separate the material from the medium, moving the material along the housing, introducing a fluid into the material within the housing, and washing the material using the fluid. | 01-21-2010 |
20100307484 | Process for Steeping Corn and Steeping System Therefore - The present invention is directed to improvements in the steeping process of corn wet milling and a steeping system therefore. The process for steeping corn includes subjecting corn situated in a battery of no less than four steeping tanks to a countercurrent flow of steep water. The first steeping tank defines a new corn receiving tank and the last steeping tank defines a discharge tank. The countercurrent flow of steep water includes sulfur dioxide and flows in a direction from the discharge tank to the new corn receiving tank. The sulfur dioxide concentration in the steep water of the first steeping tank is greater than the sulfur dioxide concentrations in a plurality of the remainder of the steeping tanks, which maintain sulfur dioxide levels that are substantially equivalent. | 12-09-2010 |
20120064213 | METHODS FOR PRODUCING A HIGH PROTEIN CORN MEAL FROM A WHOLE STILLAGE BYPRODUCT AND SYSTEM THEREFORE - The present invention relates generally to corn dry-milling, and more specifically, to methods for producing a high protein corn meal from a whole stillage byproduct produced in a corn dry-milling process for making ethanol and a system therefore. In one embodiment, a method for producing a high protein corn meal from a whole stillage byproduct includes, in a corn dry-milling process for making ethanol, separating the whole stillage byproduct into an insoluble solids portion and a thin stillage portion. The thin stillage portion is separated into a protein portion and a water soluble solids portion. Next, the protein portion is dewatered then dried to define a high protein corn meal that includes at least 40 wt % protein on a dry basis. | 03-15-2012 |
20120244590 | DRY GRIND ETHANOL PRODUCTION PROCESS AND SYSTEM WITH FRONT END MILLING METHOD - A dry grind ethanol production process and system with front end milling method is provided for improving alcohol and/or by-product yields, such as oil and/or protein yields. In one example, the process includes grinding corn kernels into particles then mixing the corn particles with a liquid to produce a slurry including oil, protein, starch, fiber, germ, and grit. Thereafter, the slurry is subjected to a front end milling method, which includes separating the slurry into a solids portion, including fiber, grit, and germ, and a liquid portion, including oil, protein, and starch, then milling the separated solids portion to reduce the size of the germ and grit and release bound starch, oil, and protein from the solids portion. The starch is converted to sugar, and alcohol is produced therefrom then recovered. Also, the fiber can be separated and recovered. Oil and protein may be separated and recovered as well. | 09-27-2012 |
20130236936 | A SYSTEM AND METHOD FOR SEPARATING HIGH VALUE BY-PRODUCTS FROM GRAINS USED FOR ALCOHOL PRODUCTION - Systems and methods are provided for separating high value by-products, such as oil and/or germ, from grains used for alcohol production. In one embodiment, a method for separating by-products from grains used for alcohol production includes, subjecting milled grains to liquefaction to provide a liquefied starch solution including fiber, protein, and germ. The germ is separated from the liquefied starch solution. The separated germ is ground, e.g., to a particle size less than 50 microns, to release oil to provide a germ/oil mixture. Then, prior to fermentation, the oil is separated from the germ/oil mixture to yield an oil by-product. The pH of the germ/oil mixture can be adjusted to about 8 to about 10.5 and/or cell wall breaking enzymes or chemicals may be added to help release oil from the germ. In one example, the oil yield is greater than 1.0 lb/Bu. | 09-12-2013 |
20130288376 | SYSTEM FOR AND METHOD OF SEPARATING GERM FROM GRAINS USED FOR ALCOHOL PRODUCTION - Methods of and device for separating germs from grains used for alcohol production are provided. The principle of density difference is able to be used to separate germs from a slurry. By adjusting the density and/or viscosity of the slurry, higher germ recovering rate is attended. The method of adjusting the density and/or viscosity includes recycling a cook-water to reduce the viscosity of the slurry before fermentation and pre-concentrating a whole stillage at an evaporator and adding a syrup to the whole stillage after fermentation. An air flotation unit is able to be used to increase oil and germ recovery rate. | 10-31-2013 |
20140053829 | METHOD OF AND SYSTEM FOR PRODUCING OIL AND VALUABLE BYPRODUCTS FROM GRAINS IN DRY MILLING SYSTEMS WITH A BACK-END DEWATER MILLING UNIT - A method of and system for producing oil and valuable byproducts from grains, such as corn, in dry mills are disclosed. The method and system include dewater milling process after fermenting. Further, the method and system are able to produce oil without evaporating. Moreover, the method and system include one or more of the germ processing units, emulsion processing units, fiber processing units, high value protein producing units, and glycerol and inorganic salt producing units, such that high value byproducts are able to be generated. | 02-27-2014 |
20140110512 | GRIND MILL FOR DRY MILL INDUSTRY - A disc mill includes an inlet configured to provide solid material for grinding to the grind plates in a smooth and constant manner. A solid ring is added around an outer circumference of the grind plates to control the grinded solid discharge rate. In some embodiments, the grind plates are configured with constant solid path way open area from row to row. The grind surface and solid pass way open area are maximized by increasing the relative tooth height compared to the tooth width. The teeth can be positioned according to a block channel configurations so as to force the solid material to pass along the grind surface of each row. A grind plate design program is used to enable conjunction of the design parameters with application variation, thereby enabling the optimum grind plate design to meeting various applications needed. | 04-24-2014 |
20140147897 | TWO STAGE HIGH SPEED CENTRIFUGES IN SERIES USED TO RECOVER OIL AND PROTEIN FROM A WHOLE STILLAGE IN A DRY MILL PROCESS - Methods of and devices for recovering oil and protein and increasing production yields using two centrifuges in series or a centrifuge with dual oil and protein separating functions in a dry mill are provided. | 05-29-2014 |
Patent application number | Description | Published |
20080203054 | PLANARIZATION OF A LAYER OVER A CAVITY - A method for fabricating a micro structure includes disposing a sacrificial material in a recess formed in a lower layer and forming a layer of compensatory material on the sacrificial material in the recess. The compensatory material is higher than the upper surface of the lower layer. A first portion of the compensatory material is removed to form a substantially flat surface on the sacrificial material. The substantially flat surface is substantially co-planar with the upper surface of the lower layer. An upper layer is formed on the lower layer and the substantially flat surface. | 08-28-2008 |
20120295074 | ARRAYS OF LONG NANOSTRUCTURES IN SEMICONDUCTOR MATERIALS AND METHODS THEREOF - An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 μm. All nanowires of the plurality of nanowires are substantially parallel to each other. | 11-22-2012 |
20120319082 | LOW THERMAL CONDUCTIVITY MATRICES WITH EMBEDDED NANOSTRUCTURES AND METHODS THEREOF - A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C. | 12-20-2012 |
20130175654 | BULK NANOHOLE STRUCTURES FOR THERMOELECTRIC DEVICES AND METHODS FOR MAKING THE SAME - Array of nanoholes and method for making the same. The array of nanoholes includes a plurality of nanoholes. Each of the plurality of nanoholes corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 μm. Each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, and the distance across ranges from 5 nm to 500 nm. Each of the plurality of nanoholes is separated from at least another nanohole selected from the plurality of nanoholes by a semiconductor material associated with a sidewall thickness, and the sidewall thickness ranges from 5 nm to 500 nm. | 07-11-2013 |
20140193982 | LOW THERMAL CONDUCTIVITY MATRICES WITH EMBEDDED NANOSTRUCTURES AND METHODS THEREOF - A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C. | 07-10-2014 |
Patent application number | Description | Published |
20090077305 | Flexible Sequencer Design Architecture for Solid State Memory Controller - A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks. | 03-19-2009 |
20090089492 | FLASH MEMORY CONTROLLER - Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device. | 04-02-2009 |
20100058003 | MULTI-PLANE DATA ORDER - Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device. | 03-04-2010 |
20120011298 | INTERFACE MANAGEMENT CONTROL SYSTEMS AND METHODS FOR NON-VOLATILE SEMICONDUCTOR MEMORY - A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event. | 01-12-2012 |
20120023284 | Nonvolatile Memory System - A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format. | 01-26-2012 |
20120159052 | Descriptor Scheduler - Methods, systems and computer program products for providing a sequencer that schedules job descriptors are described. The sequencer can manage the scheduling of the job descriptors for execution based on the availability of their respective segments and channels. For example, the sequencer can check the status of the segments, and identify one or more segments that are in busy or full state, or one or more segments that are in non-busy or empty state. Based on the status check, the sequencer can execute job descriptors out of order, and in particular, give priorities to job descriptors whose associated segments are available over job descriptors whose associated segments are in busy or full state. In doing so, pending job descriptors can be processed quicker and unnecessary latency can be avoided. | 06-21-2012 |
20120278545 | NON-VOLATILE MEMORY DEVICE WITH NON-EVENLY DISTRIBUTABLE DATA ACCESS - A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes memory cells arranged among physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format. | 11-01-2012 |
20130121089 | SYSTEMS AND METHODS FOR REDUCING PEAK POWER CONSUMPTION IN A SOLID STATE DRIVE CONTROLLER - In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal. | 05-16-2013 |
20130246890 | ARCHITECTURE TO ALLOW EFFICIENT STORAGE OF DATA ON NAND FLASH MEMORY - Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a pre-determined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page. | 09-19-2013 |
20130246892 | ARCHITECTURE FOR STORAGE OF DATA ON NAND FLASH MEMORY - Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs. | 09-19-2013 |
20130290614 | FLASH MEMORY CONTROLLER - A method includes, in at least one aspect, asserting a control signal to one or more devices, determining an initial wait time after asserting the control signal, issuing a first command based on the initial wait time, determining a first interval time associated with the first command and a second command, and issuing the second command based on the first interval time. | 10-31-2013 |
20140108714 | APPARATUS AND METHOD FOR GENERATING DESCRIPTORS TO TRANSFER DATA TO AND FROM NON-VOLATILE SEMICONDUCTOR MEMORY OF A STORAGE DRIVE - A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory. | 04-17-2014 |
20140122786 | FLASH MEMORY CONTROLLER - In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands. | 05-01-2014 |
20140173197 | METHOD AND STORAGE DRIVE FOR WRITING PORTIONS OF BLOCKS OF DATA IN RESPECTIVE ARRAYS OF MEMORY CELLS OF CORRESPONDING INTEGRATED CIRCUITS - A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells. | 06-19-2014 |
20150039817 | METHOD AND APPARATUS FOR PARALLEL TRANSFER OF BLOCKS OF DATA BETWEEN AN INTERFACE MODULE AND A NON-VOLATILE SEMICONDUCTOR MEMORY - A system including a non-volatile semiconductor memory (NVSM), an interface module and a control module. The NVSM stores first and second blocks of data. The first or second block of data is non-page based such that a size of the first block of data or a size of the second block of data is not an integer multiple of a page of data. The interface module transfers the first and second blocks of data during respectively a first data transfer event and a second data transfer event. The control module, based on descriptors, controls the first and second data transfer events such that the interface module transfers the first block of data between the interface module and the NVSM while transferring the second block of data between the interface module and the NVSM. The descriptors include respective sets of instructions for transferring the first and second blocks of data. | 02-05-2015 |
Patent application number | Description | Published |
20130088848 | SOLID-STATE LAMPS WITH IMPROVED RADIAL EMISSION AND THERMAL PERFORMANCE - A solid-state lamp comprises: one or more solid-state light emitting devices (typically LEDs); a thermally conductive body; at least one duct; and a photoluminescence wavelength conversion component remote to the one or more LEDs. The lamp is configured such that the duct extends through the photoluminescence wavelength conversion component and defines a pathway for thermal airflow through the thermally conductive body to thereby provide cooling of the body and the one or more LEDs. | 04-11-2013 |
20130088849 | SOLID-STATE LAMPS WITH IMPROVED RADIAL EMISSION AND THERMAL PERFORMANCE - A solid-state lamp comprises: one or more solid-state light emitting devices (typically LEDs); a thermally conductive body; at least one duct; and a photoluminescence wavelength conversion component remote to the one or more LEDs. The lamp is configured such that the duct extends through the photoluminescence wavelength conversion component and defines a pathway for thermal airflow through the thermally conductive body to thereby provide cooling of the body and the one or more LEDs. | 04-11-2013 |
20130176723 | SOLID-STATE LAMPS WITH IMPROVED RADIAL EMISSION AND THERMAL PERFORMANCE - A solid-state lamp is described that includes a first light emission zone and a second light emission zone, where the first light emission zone is longitudinally spaced apart from the second light emission zone. The light emission zones comprise a photoluminescence wavelength conversion component and a solid state light emitting device. The lamp comprises a lower body, a central body, and an upper duct, where the central body, and the upper duct together define at least one passageway/duct for thermal airflow. | 07-11-2013 |
20130176724 | SOLID-STATE LAMPS WITH IMPROVED RADIAL EMISSION AND THERMAL PERFORMANCE - A solid-state lamp is described that includes a wavelength conversion component located at one end of the lamp. The solid-state lamp comprises: one or more solid-state light emitting devices (typically LEDs); a thermally conductive body; at least one duct; and a photoluminescence wavelength conversion component remote to the one or more LEDs, located at one end of the lamp. The lamp is configured such that the duct extends through the photoluminescence wavelength conversion component and defines a pathway for thermal airflow through the thermally conductive body to thereby provide cooling of the body and the one or more LEDs. | 07-11-2013 |
20130293098 | SOLID-STATE LINEAR LIGHTING ARRANGEMENTS INCLUDING LIGHT EMITTING PHOSPHOR - A solid-state linear lamp comprises a co-extruded component, the co-extruded component comprising an elongate lens and a layer of photoluminescent material. The elongate lens is for shaping light emitted from the lamp and comprises an elongate interior cavity. The layer of a photoluminescent material is located on an interior wall of the elongate interior cavity. The lamp further comprises an array of solid-state light emitters configured to emit light into the elongate interior cavity. | 11-07-2013 |
20140306599 | SOLID-STATE LINEAR LIGHTING ARRANGEMENTS INCLUDING LIGHT EMITTING PHOSPHOR - A solid-state linear lamp comprises a co-extruded component, the co-extruded component comprising a photoluminescent portion and a support body, where the photoluminescent portion is integrally formed with the support body. The co-extruded component is formed to comprise an interior cavity for receiving insertion of a substrate having one or more light emitters. The array of solid-state light emitters is configured to emit light into the elongate interior cavity. | 10-16-2014 |
Patent application number | Description | Published |
20120286669 | TUNING OF EMITTER WITH MULTIPLE LEDS TO A SINGLE COLOR BIN - The color of an LED-based lamp can be tuned to a desired color or color temperature. The lamp can include two or more independently addressable groups of LEDs associated with different colors or color temperatures and a total-internal-reflection (TIR) color-mixing lens to produce light of a uniform color by mixing the light from the different groups of LEDs. The color of the output light is tuned by controllably dividing an input current among the groups of LEDs. Tuning can be performed once, e.g., during manufacture, and the lamp does not require active feedback components for maintaining color temperature. | 11-15-2012 |
20120286699 | APPARATUS FOR TUNING OF EMITTER WITH MULTIPLE LEDS TO A SINGLE COLOR BIN - An apparatus is used to tune the color produced by an LED-based lamp to a desired color or color temperature. To support tuning, the lamp can include two or more independently addressable groups of LEDs. Color or color temperature is tuned by controllably dividing an input current among the groups of LEDs. The apparatus determines an optimal division of the input current based on a linear interpolation between measured values of color or color temperature produced by at least two different divisions of the input current. | 11-15-2012 |
20130075769 | SELECTION OF PHOSPHORS AND LEDS IN A MULTI-CHIP EMITTER FOR A SINGLE WHITE COLOR BIN - An emitter for an LED-based lighting device has multiple groups of LEDs that are independently addressable, allowing the emitter to be tuned to a desired color bin (e.g., a specific white color) by adjusting the relative current supplied to different groups. The LED dies for the groups and a phosphor chip for each LED die are individually selected such that each LED-die/phosphor-chip combination produces light in a desired source region associated with the group to which the LED belongs. Robotic pick-and-place systems can be used to automate assembly of the emitters by selecting LED dies from a bin based on based on spectral characteristics and phosphor chips from a number of distinct phosphor chip types. | 03-28-2013 |
20130229125 | TUNABLE MULTI-LED EMITTER MODULE - A light-emitting diode (LED) emitter module includes a substrate having a plurality of base layers of an electrically insulating material, a plurality of electrical contacts disposed on a top one of the base layer, and a plurality of electrical paths coupled to the electrical contacts, wherein at least a portion of the plurality of electrical paths is disposed between the base layers. The emitter module also includes two or more groups of light-emitting diodes (LEDs), each group having one or more LEDs, and each of the LEDs is coupled to an electrical contact. The electrical paths are configured for feeding separate electrical currents to the groups of LEDs. The emitter module also includes a memory device containing information associating a plurality of output light colors with a corresponding plurality of combinations of electrical currents, each combination specifying an electric current for each of the two or more groups of LEDs. | 09-05-2013 |
20140084796 | TUNING OF EMITTER WITH MULTIPLE LEDS TO A SINGLE COLOR BIN - The color of an LED-based lamp can be tuned to a desired color or color temperature. The lamp can include two or more independently addressable groups of LEDs associated with different colors or color temperatures and a total-internal-reflection (TIR) color-mixing lens to produce light of a uniform color by mixing the light from the different groups of LEDs. The color of the output light is tuned by controllably dividing an input current among the groups of LEDs. Tuning can be performed once, e.g., during manufacture, and the lamp does not require active feedback components for maintaining color temperature. | 03-27-2014 |
20140300283 | COLOR TUNABLE LIGHT SOURCE MODULE WITH BRIGHTNESS CONTROL - LED-based light source modules can incorporate color tunability and brightness control, allowing a user to select a desired color temperature and/or brightness and to change either or both dynamically. An emitter can include multiple independently addressable groups of LEDs, each emitting light of a different color. By controlling the relative operating current provided to each group, a desired color temperature can be achieved, and by controlling the absolute operating currents, the brightness of the output light can be controlled. Pulse width modulation (PWM) can be used to control the relative and absolute operating currents. Smooth, gradual transitions between brightness and/or color temperature settings in response to changes can be provided. | 10-09-2014 |
20140300284 | COLOR TUNABLE LIGHT SOURCE MODULE WITH BRIGHTNESS AND DIMMING CONTROL - LED-based light source modules can incorporate color tunability and brightness control, allowing a user to select a desired color temperature and/or brightness and to change either or both dynamically. An emitter can include multiple independently addressable groups of LEDs, each emitting light of a different color. By controlling the relative operating current provided to each group, a desired color temperature can be achieved, and by controlling the absolute operating currents, the brightness of the output light can be controlled. Pulse width modulation (PWM) can be used to control the relative and absolute operating currents. Smooth, gradual transitions between brightness and/or color temperature settings in response to changes can be provided. | 10-09-2014 |
20150039114 | SELECTION OF PHOSPHORS AND LEDS IN A MULTI-CHIP EMITTER FOR A SINGLE WHITE COLOR BIN - An emitter for an LED-based lighting device has multiple groups of LEDs that are independently addressable, allowing the emitter to be tuned to a desired color bin (e.g., a specific white color) by adjusting the relative current supplied to different groups. The LED dies for the groups and a phosphor chip for each LED die are individually selected such that each LED-die/phosphor-chip combination produces light in a desired source region associated with the group to which the LED belongs. Robotic pick-and-place systems can be used to automate assembly of the emitters by selecting LED dies from a bin based on based on spectral characteristics and phosphor chips from a number of distinct phosphor chip types. | 02-05-2015 |
20150061508 | TUNING OF EMITTER WITH MULTIPLE LEDS TO A SINGLE COLOR BIN - The color of an LED-based lamp can be tuned to a desired color or color temperature. The lamp can include two or more independently addressable groups of LEDs associated with different colors or color temperatures and a total-internal-reflection (TIR) color-mixing lens to produce light of a uniform color by mixing the light from the different groups of LEDs. The color of the output light is tuned by controllably dividing an input current among the groups of LEDs. Tuning can be performed once, e.g., during manufacture, and the lamp does not require active feedback components for maintaining color temperature. | 03-05-2015 |
Patent application number | Description | Published |
20090135518 | DISCRETE TRACK MAGNETIC MEDIA WITH DOMAIN WALL PINNING SITES - A magnetic recording medium with domain wall pinning sites including a substrate, a soft magnetic underlayer, and a magnetic recording layer overlying the soft magnetic underlayer. In one embodiment the magnetic recording layer has at least two grooves providing a track having first and second sidewalls formed by the grooves. The sidewalls provide a plurality of pinning sites formed between the sidewalls for pinning magnetic domain walls in the track. At least one of the pinning sites includes a first indentation in the first sidewall and a paired second indentation in the second sidewall. In one embodiment data can be stored within the magnetic recording layer by positioning a write head adjacent the track and inducing at least two magnetic domains defining a domain wall. The domain wall migrates to one of the pinning sites in the track. | 05-28-2009 |
20100039727 | E-BEAM WRITE FOR HIGH-PRECISION DOT PLACEMENT - A recording system for magnetic storage devices, including a beam column for generating a beam, a platform for moving a magnetic storage medium relative to the beam, and a signal generator for sequentially, or in a continuously alternating manner, deflecting the beam. In turn, the beam is directed according to displacement of dots on the extent of the magnetic storage medium such that dots of a plurality of dot groupings can be written to on the extent during a single pass of the beam column above the extent. | 02-18-2010 |
20100107402 | Methods Of Making Magnetic Write Heads With Use Of A Resist Channel Shrinking Solution Having Corrosion Inhibitors - One preferred method for use in making a device structure with use of the resist channel shrinking solution includes the steps of forming a first pedestal portion within a channel of a patterned resist; applying a resist channel shrinking solution comprising a resist channel shrinking film and corrosion inhibitors within the channel of the patterned resist; baking the resist channel shrinking solution over the patterned resist to thereby reduce a width of the channel of the patterned resist; removing the resist channel shrinking solution; and forming a second pedestal portion within the reduced-width channel of the patterned resist. Advantageously, the oxide layer and the corrosion inhibitors of the resist channel shrinking solution reduce corrosion in the pedestal during the act of baking the resist channel shrinking solution. | 05-06-2010 |
20100221581 | PROCESS FOR FABRICATING PATTERNED MAGNETIC RECORDING MEDIA - A method of fabricating a patterned magnetic recording medium, comprises steps of: (a) providing a layer stack including an uppermost non-magnetic interlayer; (b) forming a resist layer on the interlayer; (c) forming a first pattern comprising a first group of recesses extending through the resist layer and exposing a first group of spaced apart surface portions of the interlayer; (d) filling the first group of recesses with a layer of a hard mask material; (e) selectively removing the resist layer to form a second pattern comprising a second group of recesses extending through the hard mask layer and exposing a second group of spaced apart surface portions of the interlayer; and (f) filling the second group of recesses with a layer of a magnetically hard material forming a magnetic recording layer. | 09-02-2010 |
20140193538 | Dual-imprint pattern for apparatus - Provided herein is an apparatus, including an imprint template including a dual-imprint pattern, wherein the dual-imprint pattern is characteristic of imprinting a first pattern on the template with a first template and a second pattern on the template with a second template, and wherein the first pattern and the second pattern at least partially overlap to form the dual-imprint pattern. | 07-10-2014 |
20150016774 | METHOD FOR REGULATING PATTERNED PLASMONIC UNDERLAYER - The embodiments disclose a stack feature of a stack configured to confine optical fields within and to a patterned plasmonic underlayer in the stack configured to guide light from a light source to regulate optical coupling. | 01-15-2015 |
20150017481 | BIT PATTERNED GROWTH GUIDING MECHANISM - The embodiments disclose a structure, including a first layer selectively etched on a substrate with a seedlayer deposited thereon, a first layer bit patterned growth guiding mechanism on the seedlayer, and a plurality of bit patterned magnetic recording features grown on the seedlayer guided by the growth guiding mechanism. | 01-15-2015 |
20150017482 | METHOD FOR FABRICATING PLASMONIC CLADDING - The embodiments disclose a plasmonic cladding structure including at least one conformal plasmonic cladding structure wrapped around plural stack features of a recording device, wherein the conformal plasmonic cladding structure is configured to create a near-field transducer in close proximity to a recording head of the recording device, at least one conformal plasmonic cladding structure with substantially removed top surfaces of the stack features with exposed magnetic layer materials and a thermally insulating filler configured to be located between the stack features. | 01-15-2015 |
Patent application number | Description | Published |
20100053809 | EMBEDDED SERVO ON TRACK FOR BIT-PATTERNED MEDIA (BPM) - A method of making a disc for a computer disc drive and a disc made in accordance with the same. The disc includes a deposited magnetic layer of a thin film medium over a disc-shaped substrate. A master pattern having a plurality of tracks is recorded on the disc. Each track on the disc includes a plurality of magnetic islands, each having a size and magnetic properties. The size and/or magnetic properties of one or more of the magnetic islands of each track are modulated such that each track has a modulation frequency, so as to imprint a magnetic topology on the disc. The modulation frequency of each track is either a fundamental frequency or an overtone of the fundamental frequency. | 03-04-2010 |
20100062282 | BIT PATTERNED MEDIA - The invention relates to bit patterned recording media having a stop layer for chemical mechanical polishing. One embodiment of the present invention is a method of manufacturing a magnetic recording medium comprising the step of planarizing by chemical mechanical polishing until the stop layer is reached. The present invention also provides a magnetic recording medium having a stop layer. | 03-11-2010 |
20100119778 | ULTRA THIN ALIGNMENT WALLS FOR DI-BLOCK COPOLYMER - Methods comprising providing a pre-patterned substrate having an array of thick walls, depositing a conforming layer on the pre-patterned substrate, etching the conforming layer from the top of the thick walls and the space between the walls, and etching the thick walls while leaving thin walls of conforming layer. | 05-13-2010 |
20100276390 | METHOD OF MASTERING PRECISE DOT ARRAY FOR BIT-PATTERNED MEDIA - A method of producing bit-patterned media master is provided whereby down-track and cross-track deflection plates are used to position an electronic beam at two (or more) adjacent tracks during the same revolution. Adjacent tracks of a bit-patterned media can be mastered simultaneously in the present invention by keeping the electronic beam ON during the entire time that the master is being created and the deflection plates are used to quickly ping-pong the electronic beam between the two (or more) adjacent tracks. | 11-04-2010 |
20110027407 | PROFILE CONTROL UTILIZING A RECESSED IMPRINT TEMPLATE - An imprint template is provided with a shallower field bordering the patterned region. The shallower field can be formed with additional lithography/etch steps after (or before) the formation of the features in the patterned region. The template is used to establish a thin film pattern with a field thickness that is shallower than the pattern. A shallower field bordering the patterned region alleviates sidewall re-deposition during ion mill. In a planarization/etch-back process, a thinner field helps to achieve a flat top surface by compensating for the thickness variation caused by different filling ratios. Fabrication of the recessed field template comprises a multi-step patterning process. The initial patterns are formed using a convention fabrication process. A second patterning step is used to reduce the height of the field region, which can be applied by coating the “half-finished” template with a suitable resist pattern and patterning the resist using a second lithography step that is aligned to the original pattern. Template material in the field region is then etched with the resist as a mask, forming a template with a recessed field region after the remaining resist is removed. It should be appreciated that the order of these etch steps can be reversed to obtain the same result. | 02-03-2011 |
20110038082 | COMBINED CMP AND ETCH PLANARIZATION - A magnetic device having a magnetic feature, the magnetic feature including magnetic portions, a stop layer portion on each magnetic portion, and a region of non-magnetic material adjacent to the magnetic portions and the stop layer portions, where the stop layer portions define planar upper boundaries for the magnetic portions and an endpoint in planarization of the magnetic feature. | 02-17-2011 |
20110128647 | METHOD OF DISK ALIGNMENT USING PRINTED ALIGNMENT MARKS - Processes include aligning a disc with a template at a location so that the pattern from the template is transferred to the disc in a relative orientation. The relative orientation provides that when the disc with the transferred pattern is finally assembled into a hard disc drive, an inner diameter of the spindle hole of the disc may be abutted against an outer diameter of the disc drive spindle, and the data-containing patterns on the discs will be aligned concentrically with a center of the disc drive spindle. While the data-containing patterns are aligned concentrically with the disc drive spindle, the substrate itself is allowed to be non-concentric. Still other aspects include a disc having eccentric formations including PIM and one or more of bit patterns and servo information formed on a disc surface, the eccentricity of the formations is determined based on an expected difference between the radius of the spindle hole of the disc and the radius of the spindle on which the disc will be placed during assembly, with the PIM used to determine the angular alignment of the disc with the spindle. | 06-02-2011 |
20110132867 | METHOD AND SYSTEM FOR IMPRINT LITHOGRAPHY - A method and apparatus of imprint lithography wherein the method includes depositing a material on a patterned surface of a conductive substrate, and pressing a transparent substrate and the conductive substrate together, wherein the pressing causes the material to conform to the patterned surface. Energy is applied to the material to form patterned material from the material. The transparent substrate and the conductive substrate are separated, wherein the patterned material adheres to the transparent substrate. | 06-09-2011 |
20120025426 | METHOD AND SYSTEM FOR THERMAL IMPRINT LITHOGRAPHY - A method and apparatus of thermal imprint lithography includes moving an imprinter against a surface to be imprinted, supplying energy to a layer of heating material, and forming features in the surface to be imprinted. The imprinter comprises a main body and the layer of heating material under the main body. In an embodiment the layer of heating material is electrically heated. In alternate embodiments, the layer of heating material is optically heated. | 02-02-2012 |
20120135159 | SYSTEM AND METHOD FOR IMPRINT-GUIDED BLOCK COPOLYMER NANO-PATTERNING - This disclosure describes a method for nano-patterning by incorporating one or more block copolymers and one or more nano-imprinting steps in the fabrication process. The block copolymers may be comprised of organic or organic components, and may be lamellar, spherical or cylindrical. As a result, a patterned medium may be formed having one-dimensional or two-dimensional patterns with a feature pitch of 5-100 nm and/or a bit density of at least 1 Tdpsi. | 05-31-2012 |
20120164389 | IMPRINT TEMPLATE FABRICATION AND REPAIR BASED ON DIRECTED BLOCK COPOLYMER ASSEMBLY - Imprinted apparatuses, such as Bit-Patterned Media (BPM) templates, Discrete Track Recording (DTR) templates, semiconductors, and photonic devices are disclosed. Methods of fabricating imprinted apparatuses using a combination of patterning and block copolymer (BCP) self-assembly techniques are also disclosed. | 06-28-2012 |
20120196089 | CHEMICALLY-MODIFIED PILLAR SURFACE TO GUIDE CYLINDER-FORMING P(S-b-MMA) BLOCK COPOLYMER ASSEMBLY - A method of self-assembling density multiplied block copolymers (BCP) structures includes applying a block copolymer (BCP) to a feature-imprinted resist layer. The BCP is thermally annealed to laterally segregate the BCP into self-assembled columns of a first polymer block surrounded by a second polymer block. | 08-02-2012 |
20120273999 | METHOD FOR PATTERNING A STACK - The embodiments disclose a method for patterning a stack, including embedding servo patterns within a final template and creating positions of plural cross-tracked shifted position error signal (PES) fields incrementally from the embedded servo patterns on the final template. | 11-01-2012 |
20120308783 | METHOD OF CREATING TWO-SIDED TEMPLATE FROM A SINGLE RECORDED MASTER - The embodiments disclose a method of creating two-sided template from a single recorded master, including fabricating a first template using a single recorded master, wherein the first template has a changed duty cycle and an unchanged servo arc orientation, creating a replicate of the first template, wherein the replicate has a mirrored servo arc orientation and a changed duty cycle and fabricating a second template using the replicate to produce a predetermined mirrored servo arc orientation and a predetermined duty cycle for imprinting on a second side of a patterned stack. | 12-06-2012 |
20130004763 | METHOD OF PATTERNING A STACK - The embodiments disclose a method of fabricating a stack, including replacing a metal layer of a stack imprint structure with an oxide layer, patterning the oxide layer stack using chemical etch processes to transfer the pattern image and cleaning etch residue from the stack imprint structure to substantially prevent contamination of the metal layers. | 01-03-2013 |
20130208378 | BIT PATTERNED MEDIA - The invention relates to bit patterned recording media having a stop layer for chemical mechanical polishing. One embodiment of the present invention is a method of manufacturing a magnetic recording medium comprising the step of planarizing by chemical mechanical polishing until the stop layer is reached. The present invention also provides a magnetic recording medium having a stop layer. | 08-15-2013 |
20140099478 | BLOCK COPOLYMER ASSEMBLY - The embodiments disclose a block copolymer assembly structure, including a first pattern and second pattern with a first density of patterned features integrated in data and servo zones, a silicon substrate with thin film layers deposited thereon and patterned using the first density of first pattern and second pattern features and a template fabrication pattern with a second density greater than the first density created using ordered block copolymer periodic structures across a portion of the substrate. | 04-10-2014 |
20140113064 | METHOD AND SYSTEM FOR OPTICAL CALIBRATION - A system and method of calibrating optical measuring equipment includes optically measuring discrete objects of a first known predictable pattern from a calibration apparatus, wherein the first known predictable pattern is a bit pattern. A recording surface optical reader is calibrated based on the optically measuring. Using the first known predictable pattern, contamination is filtered from the results of the optically measuring. | 04-24-2014 |
Patent application number | Description | Published |
20140053246 | SELF-CONFIGURING WIRELESS NETWORK - Methods, systems, and apparatus, are provided for wireless networking In some implementations, a self-configuring wireless system includes at least one wireless network device; and an access point device; wherein the access point device and the at least one wireless network device are preconfigured with a common key so as to enable the access point device to establish a secure wireless network with the at least one network device using the common key upon powering up the access point device and the at least one wireless network device at a user site. | 02-20-2014 |
20140204727 | REDUNDANT CONTROL OF SELF-CONFIGURING WIRELESS NETWORK - Methods, systems, and apparatus, are provided for wireless networking. In some implementations, a self-configuring wireless system includes one or more wireless network devices; a primary access point device; and a secondary access point device; wherein the primary access point device and the at least one wireless network device are preconfigured with a respective key so as to enable the primary access point device to establish a secure wireless network with the at least one network device using the respective keys, and wherein the secondary access point device is configured assume coordination for the self-configuring wireless system if a fault associated with the primary access point device occurs. | 07-24-2014 |
20140247941 | SELF-CONFIGURING WIRELESS NETWORK - Methods, systems, and apparatus, are provided for wireless networking. In some implementations, a self-configuring wireless system includes one or more wireless network devices; and an access point device, wherein the one or more wireless network devices are each preconfigured with a respective key, and wherein the access point device is configured to obtain the respective keys so as to enable the access point device to establish a secure wireless network with the one or more network devices using the respective keys upon powering up the access point device and the one or more wireless network devices at a user location. | 09-04-2014 |
20140266767 | SECURITY SYSTEM POWER MANAGEMENT - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for power management. One of the methods includes determining that there is a loss in electricity to a security system management device; entering low power state; receiving a wireless sensor alert while in the low power state; in response to the alert: returning to normal power state to transmit an alarm to a service provider system, and returning to low power state after transmitting the alarm; and returning to normal power state when electricity is restored. | 09-18-2014 |
20150077250 | SECURITY SYSTEM COMMUNICATIONS MANAGEMENT - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for managing communications. One of the systems includes a plurality of security systems, each security system including a secure network coupling a plurality of security devices; a plurality of user devices authorized to send and receive communications associated with a respective security system of the plurality of security systems; and a service provider system configured to manage communications for each of the plurality of security systems with respective user devices, wherein, the service provider system or the user devices are configured to communicate with a push service to send push notifications. | 03-19-2015 |
Patent application number | Description | Published |
20120226644 | Accurate and Fast Neural network Training for Library-Based Critical Dimension (CD) Metrology - Approaches for accurate neural network training for library-based critical dimension (CD) metrology are described. Approaches for fast neural network training for library-based CD metrology are also described. | 09-06-2012 |
20130158957 | LIBRARY GENERATION WITH DERIVATIVES IN OPTICAL METROLOGY - Methods of library generation with derivatives for optical metrology are described. For example, a method of generating a library for optical metrology includes determining a function of a parameter data set for one or more repeating structures on a semiconductor substrate or wafer. The method also includes determining a first derivative of the function of the parameter data set. The method also includes providing a spectral library based on both the function and the first derivative of the function. | 06-20-2013 |
20130262044 | MODEL OPTIMIZATION APPROACH BASED ON SPECTRAL SENSITIVITY - Model optimization approaches based on spectral sensitivity is described. For example, a method includes determining a first model of a structure. The first model is based on a first set of parameters. A set of spectral sensitivity variations data is determined for the structure. Spectral sensitivity is determined by derivatives of the spectra with respect to the first set of parameters. The first model of the structure is modified to provide a second model of the structure based on the set of spectral sensitivity variations data. The second model of the structure is based on a second set of parameters different from the first set of parameters. A simulated spectrum derived from the second model of the structure is then provided. | 10-03-2013 |
20140032463 | ACCURATE AND FAST NEURAL NETWORK TRAINING FOR LIBRARY-BASED CRITICAL DIMENSION (CD) METROLOGY - Approaches for accurate neural network training for library-based critical dimension (CD) metrology are described. Approaches for fast neural network training for library-based CD metrology are also described. | 01-30-2014 |
20140358485 | AUTOMATIC WAVELENGTH OR ANGLE PRUNING FOR OPTICAL METROLOGY - Automatic wavelength or angle pruning for optical metrology is described. An embodiment of a method for automatic wavelength or angle pruning for optical metrology includes determining a model of a structure including a plurality of parameters; designing and computing a dataset of wavelength-dependent or angle-dependent data for the model; storing the dataset in a computer memory; performing with a processor an analysis of the dataset for the model including applying an outlier detection technology on the dataset, and identifying any data outliers, each data outlier being a wavelength or angle; and, if any data outliers are identified in the analysis of the dataset of the model, removing the wavelengths or angles corresponding to the data outliers from the dataset to generate a modified dataset, and storing the modified dataset in the computer memory. | 12-04-2014 |
20140358488 | DYNAMIC REMOVAL OF CORRELATION OF HIGHLY CORRELATED PARAMETERS FOR OPTICAL METROLOGY - Dynamic removal of correlation of highly-correlated parameters for optical metrology is described. An embodiment of a method includes determining a model of a structure, the model including a set of parameters; performing optical metrology measurement of the structure, including collecting spectra data on a hardware element; during the measurement of the structure, dynamically removing correlation of two or more parameters of the set of parameters, an iteration of the dynamic removal of correlation including: generating a Jacobian matrix of the set of parameters, applying a singular value decomposition of the Jacobian matrix, selecting a subset of the set of parameters, and computing a direction of the parameter search based on the subset of parameters. If the model does not converge, performing one or more additional iterations of the dynamic removal of correlation until the model converges; and if the model does converge, reporting the results of the measurement. | 12-04-2014 |
Patent application number | Description | Published |
20130221314 | Memory Device Having An Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 08-29-2013 |
20130224928 | MEMORY DEVICE HAVING AN INTEGRATED TWO-TERMINAL CURRENT LIMITING RESISTOR - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 08-29-2013 |
20140051223 | Memory Device Having An Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 02-20-2014 |
20140109030 | Method of Determining Electromigration (EM) Lifetimes and Lifetime Criteria - Methods are described for performing detailed Technology Computer Aided Design (TCAD) simulations of electromigration (EM) failure in a standard test structure suitable for the simulation of integrated circuit (IC) conductive interconnects. Methods are described for performing these simulation so as to extract from the results of these simulations criteria substantially underlying the EM lifetime of interconnects, thereby permitting rapid diagnosis of potential sites of EM failure early in the IC design and fabrication process, and thereby allowing more rapid development of reliable ICs robust against EM failure. Specific results for EM failure criteria in Cu interconnects are also presented. | 04-17-2014 |
20140166107 | Back-Contact Electron Reflectors Enhancing Thin Film Solar Cell Efficiency - Methods for improving the efficiency of solar cells are disclosed. A solar cell consistent with the present disclosure includes a back contact metal layer disposed on a substrate. The solar cell also includes an electron reflector material(s) layer formed on the back contact metal layer and an absorber material(s) layer disposed on the electron reflector material(s) layer. In addition, the solar cell includes a buffer material(s) layer formed on the absorber material(s) layer wherein the electron reflector material(s) layer, absorber material(s) layer, and buffer material(s) layer form a pn junction within the solar cell. Furthermore, a TCO material(s) layer is formed on the buffer material(s) layer. In addition, the front contact layer is formed on the TCO material(s) layer. | 06-19-2014 |
20140169062 | Methods of Manufacturing Embedded Bipolar Switching Resistive Memory - Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density. | 06-19-2014 |
20140183737 | Diffusion Barriers - Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(C | 07-03-2014 |
20140185357 | Barrier Design for Steering Elements - Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element. | 07-03-2014 |
20140264492 | COUNTER-DOPED LOW-POWER FINFET - FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally doped region of counter-doped semiconductor is formed on the fin using methods such as monolayer doping, sacrificial oxide doping, or low energy plasma doping. Halo-doped regions are formed by angled ion implantation. The halo-doped regions are disposed in the lower portion of the source and drain and adjacent to the fin. Energy band barrier regions can be formed at the edges of the halo-doped regions by angled ion implantation. | 09-18-2014 |
20140264507 | Fluorine Passivation in CMOS Image Sensors - CMOS imaging sensors having fluorine-passivated structures to reduce dark current are disclosed together with methods of making thereof. The CIS comprises an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors. Methods of preparing a CIS comprise providing a source of fluorine (F) atoms, and annealing in the presence of the source of F atoms. After the annealing, at least one silicon-containing surface or region in the CIS comprises Si—F bonds and is fluorine passivated. | 09-18-2014 |
20140264634 | FINFET FOR RF AND ANALOG INTEGRATED CIRCUITS - Methods for making a FinFET having reduced device mismatch and low-frequency noise are disclosed for RF/analog IC designs. A semiconductor fin is formed having a height between 2 and 6 times its width, atomically smooth sidewalls, and rounded active corners to minimize device variability. The fin is operable as a channel between a source and a drain. A first layer of SiO | 09-18-2014 |
20140264871 | Method to Increase Interconnect Reliability - Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material. | 09-18-2014 |
20140273427 | Electrode for Low-Leakage Devices - A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer. | 09-18-2014 |
20140299834 | Memory Device Having An Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 10-09-2014 |
20150079727 | Amorphous IGZO Devices and Methods for Forming the Same - Embodiments described herein provide improvements to indium-gallium-zinc oxide devices, such as amorphous IGZO thin film transistors, and methods for forming such devices. A relatively thin a-IGZO channel may be utilized. A plasma treatment chemical precursor passivation may be provided to the front-side a-IGZO interface. High-k dielectric materials may be used in the etch-stop layer at the back-side a-IGZO interface. A barrier layer may be formed above the gate electrode before the gate dielectric layer is deposited. The conventional etch-stop layer, typically formed before the source and drain regions are defined, may be replaced by a pre-passivation layer that is formed after the source and drain regions are defined and may include multiple sub-layers. | 03-19-2015 |
Patent application number | Description | Published |
20080202425 | TEMPERATURE CONTROLLED LID ASSEMBLY FOR TUNGSTEN NITRIDE DEPOSITION - Embodiments of the invention provide apparatuses for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a processing chamber is provided which includes a lid assembly containing a lid plate, a showerhead, a mixing cavity, a distribution cavity, and a resistive heating element contained within the lid plate. In one example, the resistive heating element is configured to provide the lid plate at a temperature within a range from about 120° C. to about 180° C., preferably, from about 140° C. to about 160° C., more preferably, from about 145° C. to about 155° C. The mixing cavity may be in fluid communication with a tungsten precursor source containing tungsten hexafluoride and a nitrogen precursor source containing ammonia. In some embodiments, a single processing chamber may be used to deposit metallic tungsten and tungsten nitride materials by CVD processes. | 08-28-2008 |
20080206987 | PROCESS FOR TUNGSTEN NITRIDE DEPOSITION BY A TEMPERATURE CONTROLLED LID ASSEMBLY - Embodiments of the invention provide processes for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a method for forming a tungsten-containing material is provided which includes positioning a substrate within a processing chamber containing a lid plate, heating the lid plate to a temperature within a range from about 120° C. to about 180° C., exposing the substrate to a reducing gas during a pre-nucleation soak process, and depositing a first tungsten nucleation layer on the substrate during a first atomic layer deposition process within the processing chamber. The method further provides depositing a tungsten nitride layer on the first tungsten nucleation layer during a vapor deposition process, depositing a second tungsten nucleation layer on the tungsten nitride layer during a second atomic layer deposition process within the processing chamber, and exposing the substrate to another reducing gas during a post-nucleation soak process. | 08-28-2008 |
20090081866 | VAPOR DEPOSITION OF TUNGSTEN MATERIALS - Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the production level throughput. In one embodiment, a method is provided which includes depositing a tungsten silicide layer on the substrate by exposing the substrate to a continuous flow of a silicon precursor while also exposing the substrate to intermittent pulses of a tungsten precursor. The method further provides that the substrate is exposed to the silicon and tungsten precursors which have a silicon/tungsten precursor flow rate ratio of greater than 1, for example, about 2, about 3, or greater. Subsequently, the method provides depositing a tungsten nitride layer on the tungsten suicide layer, depositing a tungsten nucleation layer on the tungsten nitride layer, and depositing a tungsten bulk layer on the tungsten nucleation layer. | 03-26-2009 |
20110233778 | FORMATION OF LINER AND BARRIER FOR TUNGSTEN AS GATE ELECTRODE AND AS CONTACT PLUG TO REDUCE RESISTANCE AND ENHANCE DEVICE PERFORMANCE - The invention provides a method of forming a film stack on a substrate, comprising depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer without depositing a tungsten nucleation layer on the tungsten nitride layer as a growth site for tungsten. | 09-29-2011 |
20110298062 | METAL GATE STRUCTURES AND METHODS FOR FORMING THEREOF - Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode. | 12-08-2011 |
20110312148 | CHEMICAL VAPOR DEPOSITION OF RUTHENIUM FILMS CONTAINING OXYGEN OR CARBON - Methods for depositing ruthenium-containing films are provided herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing film to an oxygen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the oxygen-containing gas exposed ruthenium-containing film may be annealed in a hydrogen-containing gas to remove at least some oxygen from the ruthenium-containing film. In some embodiments, the deposition, exposure, and annealing may be repeated to deposit the ruthenium-containing film to a desired thickness. | 12-22-2011 |
20120012465 | METHODS FOR FORMING BARRIER/SEED LAYERS FOR COPPER INTERCONNECT STRUCTURES - Methods for forming barrier/seed layers for interconnect structures are provided herein. In some embodiments, a method of processing a substrate having an opening formed in a first surface of the substrate, the opening having a sidewall and a bottom surface, the method may include forming a layer comprising manganese (Mn) and at least one of ruthenium (Ru) or cobalt (Co) on the sidewall and bottom surface of the opening; and depositing a conductive material on the layer to fill the opening. In some embodiments, one of ruthenium (Ru) or cobalt (Co) is deposited on the sidewall and bottom surface of the opening. The materials may be deposited by chemical vapor deposition (CVD) or by physical vapor deposition (PVD). | 01-19-2012 |
20130109172 | HIGH TEMPERATURE TUNGSTEN METALLIZATION PROCESS | 05-02-2013 |
20130146468 | CHEMICAL VAPOR DEPOSITION (CVD) OF RUTHENIUM FILMS AND APPLICATIONS FOR SAME - Methods for depositing ruthenium-containing films are disclosed herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing layer to a hydrogen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the hydrogen-containing gas exposed ruthenium-containing film may be subsequently exposed to an oxygen-containing gas to at least one of remove at least some carbon from or add oxygen to the ruthenium-containing film. In some embodiments, the deposition and exposure to the hydrogen-containing gas and optionally, the oxygen-containing gas may be repeated to deposit the ruthenium-containing film to a desired thickness. | 06-13-2013 |
20130168864 | METHOD FOR PRODUCING ULTRA-THIN TUNGSTEN LAYERS WITH IMPROVED STEP COVERAGE - A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole. | 07-04-2013 |
20140106083 | TUNGSTEN GROWTH MODULATION BY CONTROLLING SURFACE COMPOSITION - A method for selectively controlling deposition rate of a catalytic material during a catalytic bulk CVD deposition is disclosed herein. The method can include positioning a substrate in a processing chamber including both surface regions and gap regions, depositing a first nucleation layer comprising tungsten conformally over an exposed surface of the substrate, treating at least a portion of the first nucleation layer with activated nitrogen, wherein the activated nitrogen is deposited preferentially on the surface regions, reacting a first deposition gas comprising tungsten halide and hydrogen-containing gas to deposit a tungsten fill layer preferentially in gap regions of the substrate, reacting a nucleation gas comprising a tungsten halide to form a second nucleation layer, and reacting a second deposition gas comprising tungsten halide and a hydrogen-containing gas to deposit a tungsten field layer. | 04-17-2014 |
20140187038 | HIGH TEMPERATURE TUNGSTEN METALLIZATION PROCESS - Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700° C. to less than 1,000° C.). Subsequently, the method includes optionally forming a nucleation layer on the tungsten barrier layer, optionally exposing the tungsten barrier layer and/or the nucleation layer to a reducing agent during soak processes, and forming a tungsten bulk layer on or over the tungsten barrier layer and/or the nucleation layer. | 07-03-2014 |
20150075432 | APPARATUS TO IMPROVE SUBSTRATE TEMPERATURE UNIFORMITY - Apparatus for improving substrate temperature uniformity in a substrate processing chamber are provided herein. In some embodiments, a substrate support processing chamber may include a chamber body having a bottom portion and a sidewall having a slit valve opening to load and unload substrates, a pin lift mechanism, disposed in a pin lift mechanism opening formed in the bottom portion of the chamber body, having a plurality of substrate support pins coupled to the pin lift mechanism, a movable substrate support heater having substrate support portion and a shaft, and a cover plate disposed about the shaft of the movable substrate support, wherein the cover plate covers the pin lift mechanism and pin lift mechanism opening. | 03-19-2015 |
Patent application number | Description | Published |
20100046118 | TIME-SHIFTED BITS FOR WRITE SYNCHRONIZATION CORRECTION - Systems and methods are provided for correcting write synchronization of a magnetic storage device with respect to magnetic storage media and its corresponding writable magnetic bits, or dots. In particular, these systems and methods involve using time-shifting principles to calibrate the magnetic storage devices to correct slow drifts of reader-writer timing. It is to be appreciated that time-shifting techniques can be applied in a variety of manners. For example, the very dots on the media can be positioned in time-shifted fashion. In another example, the writing to the dots can be time-shifted. | 02-25-2010 |
20110044147 | WRITEALE OPTICAL RECORDING OF MULTI-LEVEL ORIENTED NANO-STRUCTURE DISCS - A method of performing writable optical recording of a medium to form multilevel oriented nano-structures therein, comprises steps of providing a disc-shaped, writable recording medium having a planar surface; and encoding data/information in the medium by forming a plurality of multilevel nano-structured pits in the surface by scanning with a focused spot of optical energy to form at least one data track therein, including scanning the optical spot in a cross-track direction while rotating the disc about a central axis. | 02-24-2011 |
20110292546 | TIMING TRACK FOR MASTER TEMPLATE SUBSTRATE - A patterned recording media is formed from a master template that includes a data area and a timing track area having a final timing track. In order to form the final timing track, a first timing track is etched into master template and tested for accuracy by comparing the angular position of the master template to the timing track. If errors are detected in the timing track, the errors are used to create additional timing tracks which are etched into the master template. This process of improving the timing track is repeated until a final timing track is formed that has errors below a predetermined level. The timing tracks formed prior to the final timing track are removed and the master template is used to make stampers which are used to make patterned media disks. | 12-01-2011 |
20140193538 | Dual-imprint pattern for apparatus - Provided herein is an apparatus, including an imprint template including a dual-imprint pattern, wherein the dual-imprint pattern is characteristic of imprinting a first pattern on the template with a first template and a second pattern on the template with a second template, and wherein the first pattern and the second pattern at least partially overlap to form the dual-imprint pattern. | 07-10-2014 |
Patent application number | Description | Published |
20080252889 | SYSTEMS AND METHODS FOR MEASUREMENT OF A SPECIMEN WITH VACUUM ULTRAVIOLET LIGHT - Various systems for measurement of a specimen are provided. One system includes an optical subsystem configured to perform measurements of a specimen using vacuum ultraviolet light and non-vacuum ultraviolet light. This system also includes a purging subsystem that is configured to maintain a purged environment around the optical subsystem during the measurements. Another system includes a cleaning subsystem configured to remove contaminants from a specimen prior to measurement. In one embodiment, the cleaning subsystem may be a laser-based cleaning subsystem that is configured to remove contaminants from a localized area on the specimen. The system also includes an optical subsystem that is configured to perform measurements of the specimen using vacuum ultraviolet light. The optical subsystem is disposed within a purged environment. In some embodiments, the system may include a differential purging subsystem that is configured to provide the purged environment for the optical subsystem. | 10-16-2008 |
20090279088 | SYSTEMS AND METHODS FOR MEASUREMENT OF A SPECIMEN WITH VACUUM ULTRAVIOLET LIGHT - Various systems for measurement of a specimen are provided. One system includes a first optical subsystem, which is disposed within a purged environment. The purged environment may be provided by a differential purging subsystem. The first optical subsystem performs measurements using vacuum ultraviolet light. This system also includes a second optical subsystem, which is disposed within a non-purged environment. The second optical subsystem performs measurements using non-vacuum ultraviolet light. Another system includes two or more optical subsystems configured to perform measurements of a specimen using vacuum ultraviolet light. The system also includes a purging subsystem configured to maintain a purged environment around the two or more optical subsystems. The purging subsystem is also configured to maintain the same level of purging in both optical subsystems. Some systems also include a cleaning subsystem configured to remove contaminants from a portion of a specimen prior to measurements at vacuum ultraviolet wavelengths. | 11-12-2009 |
20110317527 | METHOD AND SYSTEM FOR PROVIDING THERMAL MANAGEMENT IN AN ENERGY ASSISTED MAGNETIC RECORDING HEAD - A method and system for providing energy assisted magnetic recording (EAMR) heads are described. The method and system include providing a substrate, at least one EAMR transducer, an overcoat layer and at least one laser. The substrate has a leading edge and a substrate trailing edge. The EAMR transducer(s) reside in a device layer and on the substrate trailing edge. The overcoat layer includes a plurality of contacts. The device layer is between the overcoat layer and the substrate trailing edge. The laser(s) provide energy to the EAMR transducer. The overcoat layer is between the substrate trailing edge and the laser(s). The laser(s) are electrically coupled to at least a first portion of the contacts. The contacts provide thermal connection through the overcoat layer and the device layer. At least a second portion of the contacts is electrically insulated from the substrate. | 12-29-2011 |
20120163137 | METHOD AND SYSTEM FOR OPTICALLY COUPLING A LASER WITH A TRANSDUCER IN AN ENERGY ASSISTED MAGNETIC RECORDING DISK DRIVE - A method and system for providing an energy assisted magnetic recording (EAMR) head are described. The EAMR head includes a laser, a slider, and an EAMR transducer. The laser has a main emitter and at least one alignment emitter. The slider includes at least one alignment waveguide, at least one output device, and an air-bearing surface (ABS). The alignment waveguide(s) are aligned with the alignment emitter(s). The EAMR transducer is coupled with the slider and includes a waveguide aligned with main emitter. The waveguide is for directing energy from the main emitter toward the ABS. | 06-28-2012 |
Patent application number | Description | Published |
20130133036 | REMOTE CONTROL OF DIALYSIS MACHINES - This disclosure relates to remote control of dialysis machines. In certain aspects, a method includes receiving a request for a network connection from a dialysis machine and establishing the network connection with the dialysis machine. The method also includes receiving, from a client device, a request to access the dialysis machine, authorizing the client device to access the dialysis machine, receiving, from the dialysis machine, information pertaining to an operation of the dialysis machine, and providing, to the client device, the received information. | 05-23-2013 |
20140091022 | METHODS OF MAKING MEDICAL SOLUTIONS AND RELATED SYSTEMS - This disclosure relates to making medical solutions. In certain aspects, a method is performed by a data processing apparatus. The method includes introducing liquid into a container that contains a dissolvable solid concentrate in a manner so that a layer of solution above the solid concentrate is maintained at a depth that allows the liquid introduced into the container to agitate the solution adjacent to the solid concentrate to cause mixing of the solid concentrate with the solution. | 04-03-2014 |
20140289812 | REMOTE CONTROL OF DIALYSIS MACHINES - This disclosure relates to remote control of dialysis machines. In certain aspects, a method includes receiving a request for a network connection from a dialysis machine and establishing the network connection with the dialysis machine. The method also includes receiving, from a client device, a request to access the dialysis machine, authorizing the client device to access the dialysis machine, receiving, from the dialysis machine, information pertaining to an operation of the dialysis machine, and providing, to the client device, the received information. | 09-25-2014 |
Patent application number | Description | Published |
20090150480 | Publishing Assets Of Dynamic Nature In UPnP Networks - System and computer program products for allowing a renderer in a UPnP network the capability of being able to render general Internet content, which the renderer was not designed to render in the contents original data format and file type. The system queries all devices on the local network, queries specific remote servers over the Internet, and retrieves data feeds from remote sources. The queried and retrieved data that is not in a format and file type that can be rendered by the renderer is loaded into a template and turned into a format and file type acceptable by the renderer. The queried and retrieved data in the proper format and file type is organized in a custom format and made available for rendering to the renderer. The system has the capability of transmitting content or the metadata of the content within the devices on the local network to a hosting service over the Internet. Additionally, a second local network has the capability of accessing the content stored on the first local network. | 06-11-2009 |
20090150481 | Organizing And Publishing Assets In UPnP Networks - System and computer program products for allowing a renderer in a UPnP network the capability of being able to render general Internet content of static or dynamic nature, which the renderer was not designed to render in the contents original data format and file type. The system queries all devices on the local network, queries specific remote servers over the Internet, and retrieves data feeds from remote sources. The queried and retrieved data that is not in a format and file type that can be rendered by the renderer is loaded into a template and turned into a format and file type acceptable by the renderer. The queried and retrieved data in the proper format and file type is organized in a custom format and made available for rendering to the renderer. The system has the capability of transmitting content or the metadata of the content within the devices on the local network to a hosting service over the Internet. Additionally, a second local network has the capability of accessing the content stored on the first local network. | 06-11-2009 |
20090150570 | Sharing Assets Between UPnP Networks - Systems and computer program products for allowing a renderer in a UPnP network the capability of being able to render general Internet content of static or dynamic nature, which the renderer was not designed to render in the contents original data format and file type. The system queries all devices on the local network, queries specific remote servers over the Internet, and retrieves data feeds from remote sources. The queried and retrieved data that is not in a format and file type that can be rendered by the renderer is loaded into a template and turned into a format and file type acceptable by the renderer. The queried and retrieved data in the proper format and file type is organized in a custom format and made available for rendering to the renderer. The system has the capability of transmitting content or the metadata of the content within the devices on the local network to a hosting service over the Internet. Additionally, a second local network has the capability of accessing the content stored on the first local network. | 06-11-2009 |
20130060855 | Publishing Assets of Dynamic Nature in UPnP Networks - System and computer program products for allowing a renderer in a UPnP network the capability of being able to render general Internet content, which the renderer was not designed to render in the contents original data format and file type. The system queries all devices on the local network, queries specific remote servers over the Internet, and retrieves data feeds from remote sources. The queried and retrieved data that is not in a format and file type that can be rendered by the renderer is loaded into a template and turned into a format and file type acceptable by the renderer. The queried and retrieved data in the proper format and file type is organized in a custom format and made available for rendering to the renderer. | 03-07-2013 |
Patent application number | Description | Published |
20100194994 | Dual Mode DP and HDMI Transmitter - A system and method for dual mode DP and HDMI transmission are provided. Briefly described, one embodiment of a dual mode DP and HDMI transmitter, among others, can be implemented as follows. The dual mode DP and HDMI transmitter comprises a driver circuit controlled by a data signal. The dual mode DP and HDMI transmitter also comprises a control circuit coupled to the driver circuit. The control circuit is configurable to transmit the data signal in a DP mode or a HDMI mode according to a mode signal. One embodiment of a method, among others, comprises: receiving a mode signal; determining whether to configure the dual mode DP and HDMI transmitter for transmitting in a DP mode or an HDMI mode based on the received mode signal; and configuring a dual mode DP and HDMI transmitter in accordance with the determination. | 08-05-2010 |
20100231176 | Battery Charging System and Method - Methods, devices, and systems for charging a battery in a mobile device are provided. For example, in one embodiment, among others, a battery charging system includes a monitoring circuit configured to monitor a battery and generate a sense current. The battery charging system further includes a comparing circuit configured to compare a reference current and the generated sense current. The comparing circuit is further configured to generate a comparison signal. Also, the battery charging system further includes a control circuit configured to control a level of a charging current applied to the battery based on the comparison signal. | 09-16-2010 |
20110302331 | Dual Mode DP and HDMI Transmitter - A system and method for dual mode DP and HDMI transmission are provided. Briefly described, one embodiment of a dual mode DP and HDMI transmitter, among others, can be implemented as follows. The dual mode DP and HDMI transmitter comprises a driver circuit controlled by a data signal. The dual mode DP and HDMI transmitter also comprises a control circuit coupled to the driver circuit. The control circuit is configurable to transmit the data signal in a DP mode or a HDMI mode according to a mode signal. One embodiment of a method, among others, comprises: receiving a mode signal; determining whether to configure the dual mode DP and HDMI transmitter for transmitting in a DP mode or an HDMI mode based on the received mode signal; and configuring a dual mode DP and HDMI transmitter in accordance with the determination. | 12-08-2011 |
20120151099 | Dual Mode DP and HDMI Transmitter - A system and method for dual mode DP and HDMI transmission are provided. Briefly described, one embodiment of a dual mode DP and HDMI transmitter, among others, can be implemented as follows. The dual mode DP and HDMI transmitter comprises a driver circuit controlled by a data signal. The dual mode DP and HDMI transmitter also comprises a control circuit coupled to the driver circuit. The control circuit is configurable to transmit the data signal in a DP mode or a HDMI mode according to a mode signal. One embodiment of a method, among others, comprises: receiving a mode signal; determining whether to configure the dual mode DP and HDMI transmitter for transmitting in a DP mode or an HDMI mode based on the received mode signal; and configuring a dual mode DP and HDMI transmitter in accordance with the determination. | 06-14-2012 |
20120161886 | VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator including a control signal adjuster and ring-connected delay cells is disclosed. The control signal adjuster receives a first control signal to generate a second control signal boosted from the first control signal when the first control signal is lower than a transistor threshold voltage. The ring-connected delay cells are controlled by the first and second control signals both to generate an oscillation signal. Each of the delay cells has a first set of current generation transistors and a second set of current generation transistors. Each transistor of the first set of current generation transistors has a control terminal receiving the first control signal while each transistor of the second set of current generation transistors has a control terminal receiving the second control signal. The first and second sets of current generation transistors collectively output an oscillation signal with unchanged frequency of associated input signal. | 06-28-2012 |
20120169395 | LEVEL SHIFTER - A level shifter, converting an input signal into an output signal for level shifting, including a leakage blocking circuit having cascaded P-channel transistors and one N-channel transistor. The P-channel transistor at a beginning stage provides a gate for receiving the input signal and a source coupled to a gate of the P-channel transistor at a secondary stage. At intermediate stages, each P-channel transistor provides a source coupled to a gate of the subsequently cascaded P-channel transistor. At a final stage, the P-channel transistor provides a source coupled to a voltage source and a drain coupled to an output terminal of the leakage blocking circuit for the outputting of the output signal. The N-channel transistor has a gate which is coupled to receive the input signal as well, a source coupled to a common voltage, and a drain coupled to the output terminal of the leakage blocking circuit. | 07-05-2012 |
20120217999 | Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter - A low voltage differential signal (LVDS) driving circuit and a digital signal transmitter with the LVDS driving circuit are provided. The LVDS driving circuit includes a positive differential output terminal and a negative differential output terminal and a transition accelerator. A differential output signal is provided by the positive and negative differential output terminals. When the differential output signal transits from low to high, the transition accelerator couples the positive differential output terminal to a high voltage source and couples the negative differential output terminal to a low voltage source. When the differential output signal transits from high to low, the transition accelerator couples the positive differential output terminal to the low voltage source and couples the positive output terminal to the high voltage source. | 08-30-2012 |
20130064322 | FREQUENCY-CONTROL CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit is arranged to charge/discharge a voltage-control node according to a comparison result signal. The voltage-controlled delay line is arranged to generate a control signal according to the comparison result signal and a control voltage of the voltage-control node to control the output signal. A frequency of the control signal is modulated by the voltage-controlled delay line according to the control voltage of the voltage-control node. The comparison result signal is generated according to a difference between a reference voltage and a voltage level of the output signal. | 03-14-2013 |
20130076404 | LOW VOLTAGE DIFFERENTIAL SIGNAL DRIVING CIRCUIT AND ELECTRONIC DEVICE COMPATIBLE WITH WIRED TRANSMISSION - A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal). In accordance with the low-high (or high-low) transition acceleration control signal, the transition accelerator couples the positive (or negative) differential output terminal to a high voltage source and couples the negative (or positive) differential output terminal to a low voltage source to accelerate transition of the differential output signal. | 03-28-2013 |
20130099840 | DUTY ADJUSTMENT CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal. | 04-25-2013 |
20130222020 | FREQUENCY-CONTROL CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops. | 08-29-2013 |
20130300511 | VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator generating an oscillation signal according to a first control signal without a silent region. The voltage controlled oscillator includes a control signal adjuster and a plurality of delay cells. The control signal adjuster receives the first control signal and generates a second and a third control signal according to the first control signal. The voltage level of the third control signal is higher than that of the second control signal and the voltage level of the second control signal is higher than that of the first control signal. The plurality of delay cells are ring-connected and controlled by the first, the second, and the third control signals to generate the oscillation signal. Each delay cell includes three sets of current generation transistors. The three sets of current generation transistors are separately controlled by the three different control signals. | 11-14-2013 |
20140203865 | OUTPUT BUFFERS - An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage. | 07-24-2014 |
20140361835 | Current Mirror - Some embodiments of the system comprise a current mirror with two switches (a first switch and a second switch) and two compensation circuits (a first compensation circuit and a second compensation circuit). In one embodiment, the first compensation circuit adjusts a drain voltage of the second switch based on a drain voltage of the first switch, and the second compensation circuit adjusts a current through the first switch based on the drain voltage of the second switch. | 12-11-2014 |
20150049839 | Common Mode Modulation with Current Compensation - The present disclosure provides systems and methods for compensating channel modulation effects. Some embodiments comprise a differential switching circuit, a common mode modulation circuit, and a current compensation circuit. The current compensation circuit compensates for channel modulation effects. | 02-19-2015 |