Patent application number | Description | Published |
20150243563 | INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES - In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack. | 08-27-2015 |
20150243652 | INTEGRATION METHOD FOR FABRICATION OF METAL GATE BASED MULTIPLE THRESHOLD VOLTAGE DEVICES AND CIRCUITS - In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage. | 08-27-2015 |
20150303057 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FLUORINE INCORPORATION - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer. | 10-22-2015 |
20150325681 | METHODS OF FABRICATING INTEGRATED CIRCUITS - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench. | 11-12-2015 |
20160005657 | SEMICONDUCTOR STRUCTURE WITH INCREASED SPACE AND VOLUME BETWEEN SHAPED EPITAXIAL STRUCTURES - A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxial material is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxial material on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume. | 01-07-2016 |
Patent application number | Description | Published |
20130015711 | SYSTEM AND METHOD FOR USING CAPACITORS IN REMOTE OPERATIONS - A battery-free device is provided with one or more series or parallel capacitive networks. One or more solar panels are used to charge the capacitive networks and one or more charging circuits are used to control the charging of the capacitive networks. One or more DC-DC converters maybe used to provide a voltage to the device, a remote monitoring or controlling function, and, optionally, a user interface. In those instances when it is desired that the monitoring or controlling function remain powered at all times, the control circuitry is preferentially preserved at the expense of the other features of the device such that if, for any reason, the capacitive network is drained after running the other features, there will still be sufficient power stored in capacitive network to maintain the monitoring or controlling function. | 01-17-2013 |
20130015807 | System and Method for Using Capacitors in Wireless Networks - A battery-free wireless network is provided with one or more series or parallel capacitive networks. One or more solar panels are used to charge the capacitive networks and one or more charging circuits are used to control the charging of the capacitive networks. One or more DC-DC converters maybe used to provide a voltage to a wireless router, switch or other network device, the timer/clock circuitry, and a user interface. In those instances when it is desired that the timer/clock circuitry remain powered at all times, the timer/clock circuitry is preferentially preserved at the expense of the network device such that if, for any reason, the capacitive network is drained after running the network device, there will still be sufficient power stored in the capacitive network to maintain the timer/clock circuitry. | 01-17-2013 |
20130016212 | System and Method for Using Capacitors in Security Devices - A battery-free security system is provided with one or more series or parallel capacitive networks. One or more solar panels are used to charge the capacitive networks and one or more charging circuits are used to control the charging of the capacitive networks. One or more DC-DC converters may be used to provide a voltage to a load, the timer/clock circuitry, and a user interface. In those instances when it is desired that the timer/clock circuitry remain powered at all times, the timer/clock circuitry is preferentially preserved at the expense of the load such that if, for any reason, the capacitive network is drained after running the load, there will still be sufficient power stored in the capacitive network to maintain the timer/clock circuitry. | 01-17-2013 |
20150102677 | System and Method for Using Capacitors in Remote Operations - A battery-free device is provided with one or more series or parallel capacitive networks. One or more solar panels are used to charge the capacitive networks and one or more charging circuits are used to control the charging of the capacitive networks. One or more DC-DC converters maybe used to provide a voltage to the device, a remote monitoring or controlling function, and, optionally, a user interface. In those instances when it is desired that the monitoring or controlling function remain powered at all times, the control circuitry is preferentially preserved at the expense of the other features of the device such that if, for any reason, the capacitive network is drained after running the other features, there will still be sufficient power stored in capacitive network to maintain the monitoring or controlling function. | 04-16-2015 |
20150102761 | System and Method for Using Capacitors in Wireless Networks - A battery-free wireless network is provided with one or more series or parallel capacitive networks. One or more solar panels are used to charge the capacitive networks and one or more charging circuits are used to control the charging of the capacitive networks. One or more DC-DC converters maybe used to provide a voltage to a wireless router, switch or other network device, the timer/clock circuitry, and a user interface. In those instances when it is desired that the timer/clock circuitry remain powered at all times, the timer/clock circuitry is preferentially preserved at the expense of the network device such that if, for any reason, the capacitive network is drained after running the network device, there will still be sufficient power stored in the capacitive network to maintain the timer/clock circuitry. | 04-16-2015 |
20150124090 | Systems and Method for Using Capacitors in Security Devices - A battery-free security system is provided with one or more series or parallel capacitive networks. One or more solar panels are used to charge the capacitive networks and one or more charging circuits are used to control the charging of the capacitive networks. One or more DC-DC converters maybe used to provide a voltage to a load, the timer/clock circuitry, and a user interface. In those instances when it is desired that the timer/clock circuitry remain powered at all times, the timer/clock circuitry is preferentially preserved at the expense of the load such that if, for any reason, the capacitive network is drained after running the load, there will still be sufficient power stored in the capacitive network to maintain the timer/clock circuitry. | 05-07-2015 |
Patent application number | Description | Published |
20080251814 | HETERO-BONDED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH AN UNPINNING DIELECTRIC LAYER - A hetero-bonded SOI substrate comprises a stack of a semiconductor handle substrate, an isolation insulator layer, a depinning dielectric layer, and a top non-silicon semiconductor layer. The depinning layer abuts both the top non-silicon semiconductor layer and the isolation insulator layer and relaxes Fermi level pinning in the top non-silicon semiconductor layer. The top non-silicon semiconductor layer may be a III-V compound semiconductor layer such as GaAs and the depinning dielectric layer may be a (Gd | 10-16-2008 |
20090294867 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 12-03-2009 |
20120256270 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 10-11-2012 |
Patent application number | Description | Published |
20150179467 | Methods of Forming Patterns - Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material. | 06-25-2015 |
20150185607 | PHOTORESIST OVERCOAT COMPOSITIONS - Photoresist overcoat compositions comprise: a quenching polymer wherein the quenching polymer comprises: a first unit having a basic moiety; and a second unit formed from a monomer of the following general formula (I): | 07-02-2015 |
20150185615 | PHOTOLITHOGRAPHIC METHODS - Methods of forming an electronic device, comprising in sequence: (a) providing a semiconductor substrate comprising one or more layers to be patterned; (b) forming a photoresist layer over the one or more layers to be patterned, wherein the photoresist layer is formed from a composition that comprises: a matrix polymer comprising a unit having an acid labile group; a photoacid generator; and an organic solvent; (c) coating a photoresist overcoat composition over the photoresist layer, wherein the overcoat composition comprises a quenching polymer and an organic solvent, wherein the quenching polymer comprises a unit having a basic moiety effective to neutralize acid generated by the photoacid generator in a surface region of photoresist layer; (d) exposing the photoresist layer to activating radiation; (e) heating the substrate in a post-exposure bake process; and (f) developing the exposed film with an organic solvent developer. The methods have particular applicability in the semiconductor manufacturing industry. | 07-02-2015 |
20160027638 | Methods of Forming Patterns - Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material. | 01-28-2016 |
Patent application number | Description | Published |
20090102489 | Systems and methods for detecting electric discharge - A distributed sensing system for detecting partial electric discharge along the length of an extended object or objects. An optical fiber having a cladding integrated with luminescent material and a silica core of less than 500 micro-meters in diameter with a first reflective end deployed in proximity to test objects. A photo detector is positioned at the second end of the optical sensing fiber and receives and measures both a direct emission light from an electric partial discharge event and the reflected emission light from the reflection end of the optical sensing fiber. The measured signals and their arrival times are used to determine the location and magnitude of a partial electrical discharge. | 04-23-2009 |
20100103978 | PURE SILICA CORE MULTIMODE FIBER SENSOES FOR DTS APPICATIONS - A new step-index multimode pure silica core fiber for DTS (Distributed Temperature Sensing) system particularly useful for downhole environments is disclosed and described. The new sensor system provides optimum tradeoffs between coupling power, spatial resolution, and temperature resolution. | 04-29-2010 |
20100128756 | DUAL SOURCE AUTO-CORRECTION IN DISTRIBUTED TEMPERATURE SYSTEMS - An automatic and continuous method is presented to improve the accuracy of fiber optic distributed temperature measurements derived from Raman back scatterings utilizing two light sources with different wavelengths, by choosing the wavelengths of the two sources so the primary source's return anti-Stokes component overlaps with the incident wavelength of the secondary light source thereby canceling out the non-identical attenuations generated by the wavelength differences between Stokes and anti-Stokes bands. | 05-27-2010 |
20110231135 | Auto-correcting or self-calibrating DTS temperature sensing systems and methods - An automatic auto-correcting method is presented to improve the accuracy of fiber optic distributed temperature measurements derived from Raman back scatterings utilizing two light sources with different wavelengths, by appropriate choice of the wavelengths of the two sources, the use of single pulse modulating circuit for the two light sources, and use of one of the light sources as a primary measurement system and the second light source as an occasional correcting source. | 09-22-2011 |
20140233600 | METHOD AND APPARATUS FOR AUTO-CORRECTING THE DISTRIBUTED TEMPERATURE SENSING SYSTEM - System and method for correcting the potential errors occurring in a fiber optic temperature measurement system are disclosed. In one respect, a dual light sources configuration is provided. The primary light source may illuminate a sensing fiber, and an Anti-Stokes band may be detected. The secondary light source may illuminate a sensing fiber, and a Rayleigh band may be detected, where the Rayleigh band is substantially wide enough to cover the Anti-Stokes band of the primary light source. A ratio between these Anti-Stokes and the Rayleigh bands may be used to measure the temperature and undesired errors due to the perturbations falling on the sensing fiber is continuously corrected. | 08-21-2014 |
Patent application number | Description | Published |
20090242513 | Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models and Method for Using - The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures. | 10-01-2009 |
20100036514 | Creating Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures - The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes. | 02-11-2010 |
20100036518 | Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures - The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes. | 02-11-2010 |
Patent application number | Description | Published |
20130093497 | TUNNEL FIELD EFFECT TRANSISTOR (TFET) WITH LATERAL OXIDATION - A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials. | 04-18-2013 |
20150053929 | VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY - A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process. | 02-26-2015 |
20150060957 | THREE-DIMENSIONAL GATE-WRAP-AROUND FIELD-EFFECT TRANSISTOR - A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved. | 03-05-2015 |
20150364572 | VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY - A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process. | 12-17-2015 |
Patent application number | Description | Published |
20130051538 | METHODS AND APPARATUS TO PROVIDE MESSAGES TO TELEVISION USERS - Methods and apparatus to provide messages to television users are disclosed. An example method includes determining an identifier associated with a television device in response to detecting a request for a list of voicemail message information, querying a database to determine a voicemail mailbox associated with the identifier, initiating a terminal session in accordance with a remote desktop protocol for the television device, and sending the list of voicemail message information to the television device via the terminal session | 02-28-2013 |
20160100228 | METHODS AND APPARATUS TO PROVIDE MESSAGES TO TELEVISION USERS - Methods and apparatus to provide messages to consumer electronics devices are disclosed. In response to a request from a consumer electronics device for messaging information stored with at least one of a first message provider or a second message provider, determining, with a processor of a mediation system, an identifier associated with the consumer electronics device. Querying, with the processor, a database at the mediation system to determine first and second account identifiers associated with the identifier of the consumer electronics device. When the request is for the messaging information stored with the first message provider, sending, with the processor, a first command to cause the first message provider to forward the messaging information associated with the first message account identifier to the mediation system. When the request is for the messaging information stored with the second message provider, sending, with the processor, a second command to cause the second message provider to forward the messaging information associated with the second message account identifier to the mediation system. Sending, with the processor, the messaging information received from at least one of the first message provider or the second message provider to the consumer electronics device. | 04-07-2016 |
Patent application number | Description | Published |
20080270963 | SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL - A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers. | 10-30-2008 |
20100002525 | Array Data Input Latch and Data Clocking Scheme - A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues. | 01-07-2010 |
20100027361 | Information Handling System with SRAM Precharge Power Conservation - An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation. | 02-04-2010 |
20100164586 | PROGAMABLE CONTROL CLOCK CIRCUIT FOR ARRAYS - A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output. | 07-01-2010 |
20130141992 | VOLATILE MEMORY ACCESS VIA SHARED BITLINES - A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation. | 06-06-2013 |
20130141997 | SINGLE-ENDED VOLATILE MEMORY ACCESS - A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that terminates without an evaluation gate to conserve energy. | 06-06-2013 |
20140098590 | VOLATILE MEMORY ACCESS VIA SHARED BITLINES - A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation. | 04-10-2014 |
20140098597 | SINGLE-ENDED VOLATILE MEMORY ACCESS - A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that terminates without an evaluation gate to conserve energy. | 04-10-2014 |
Patent application number | Description | Published |
20140183597 | METAL ALLOY WITH AN ABRUPT INTERFACE TO III-V SEMICONDUCTOR - Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed. | 07-03-2014 |
Patent application number | Description | Published |
20110029681 | WEB CLIENT DATA CONVERSION FOR SYNTHETIC ENVIRONMENT INTERACTION - Web client data conversion for synthetic environment interaction is described, including receiving a message at a synthetic environment server indicating occurrence of an event on a web client by a web application server configured to generate a transformed message from a first protocol format to a second protocol format, sending the transformed message from the web application server to a message bus using the second protocol format, translating the transformed message into a translated message, the transformed message being translated from the second protocol to a third protocol using a property class, sending the translated message from the message bus to the synthetic environment server according to the property class, and updating the synthetic environment using data included in the translated message, wherein the synthetic environment is updated in substantially real-time. In some embodiments, a method can include an implementing an application programming interface associated with a transactional server. | 02-03-2011 |
20120295716 | WEB CLIENT DATA CONVERSION FOR SYNTHETIC ENVIRONMENT INTERACTION - Web client data conversion for synthetic environment interaction is described, including receiving a message at a synthetic environment server indicating occurrence of an event on a web client by a web application server configured to generate a transformed message from a first protocol format to a second protocol format, sending the transformed message from the web application server to a message bus using the second protocol format, translating the transformed message into a translated message, the transformed message being translated from the second protocol to a third protocol using a property class, sending the translated message from the message bus to the synthetic environment server according to the property class, and updating the synthetic environment using data included in the translated message, wherein the synthetic environment is updated in substantially real-time. In some embodiments, a method can include an implementing an application programming interface associated with a transactional server. | 11-22-2012 |