Patent application number | Description | Published |
20090032781 | Nanorice particles: hybrid plasmonic nanostructures - A new hybrid nanoparticle, i.e., a nanorice particle, which combines the intense local fields of nanorods with the highly tunable plasmon resonances of nanoshells, is described herein. This geometry possesses far greater structural tunability than previous nanoparticle geometries, along with much larger local field enhancements and far greater sensitivity as a surface plasmon resonance (SPR) nanosensor than presently known dielectric-conductive material nanostructures. In an embodiment, a nanoparticle comprises a prolate spheroid-shaped core having a first aspect ratio. The nanoparticle also comprises at least one conductive shell surrounding said prolate spheroid-shaped core. The nanoparticle has a surface plasmon resonance sensitivity of at least 600 nm RIU | 02-05-2009 |
20100022020 | Compositions for surface enhanced infrared absorption spectra and methods of using same - A composition comprising a substrate and at least one adsorbate associated with the substrate wherein the composition has an enhanced infrared absorption spectra. A method comprising tuning a nanoparticle to display a plasmon resonance in the infrared, associating an adsorbate with the nanoparticle to form an adsorbate associated nanoparticle, and aggregating the adsorbate associated nanoparticle. A method of preparing a SERS-SEIRA composition comprising fabricating a nanoparticle substrate, functionalizing the nanoparticle substrate to form a functionalized substrate, dispersing the functionalized substrate in solution to form a dispersed functionalized substrate, and associating the dispersed functionalized substrate with a medium. | 01-28-2010 |
20130013210 | ELECTRICAL IMAGER OPERATING IN OIL-BASED MUD AND LOW RESISTIVE FORMATION - This disclosure relates to apparatuses and methods for reducing current leakage between a measure electrode and a logging tool body during borehole investigations in an earth formation involving electric current and non-conductive drilling fluid. The apparatus may include one or more transmitters disposed on a pad body, configured to inject an electric current into the earth formation, and coupled to the mandrel and one or more measure electrodes. The measure electrodes may be configured to receive current from the formation and coupled to a back plate of the pad body. The apparatus may be configured to maintain a selected ratio between pad body to logging tool body impedance and transmitters to logging tool body impedance sufficient to reduce current leakage between the earth formation and the logging tool body. The transmitter/mandrel and measure electrode/back plate may be electrically isolated from one another. The method may include using the apparatus. | 01-10-2013 |
20130043884 | METHOD AND APPARATUS FOR CALIBRATING DEEP-READING MULTI-COMPONENT INDUCTION TOOLS WITH MINIMAL GROUND EFFECTS - An apparatus and method for calibrating a multi-component induction logging tool. The method may include orienting a Z-transmitter coil to be substantially orthogonal to at least one Z-receiver coil, positioning an X-transmitter coil disposed on the logging tool so that the X-transmitter coil is substantially parallel to a conducting surface; encompassing the Z-transmitter coil, the X-transmitter coil, and at least one Z-receiver coil of the logging tool with at least one conducting loop of a calibrator; and calibrating the logging tool using the calibrator. The apparatus may include a calibrator configured to receive the logging tool. The Z-transmitter coil and the Z-receiver coil may be located on separate subs that are detachable from one another. | 02-21-2013 |
20130057287 | Method and Apparatus for Well-Bore Proximity Measurement While Drilling - An apparatus for determining a distance between a first borehole and a second borehole is provided that in one embodiment includes a rotating magnet on a tool configured for placement in the second borehole for inducing magnetization in a magnetic object in the first borehole, a first coil and a second coil placed radially symmetrically with respect to an axis of the tool, the first coil providing a first signal and second coil providing a second signal responsive to a magnetic flux resulting from the magnetization in the magnetic object in the first borehole, and a controller configured to combine the first signal and the second signal and determining distance between the first borehole and the second borehole using the combined signal. | 03-07-2013 |
20140151031 | Reducing Rotational Vibration in Rotational Measurements - An apparatus for mitigation of torsional noise effects on borehole measurements. The apparatus may include a conveyance device; a sleeve having a sensor section, the sleeve rotatably disposed on the conveyance device; a sensor having at least one component disposed on the sensor section; and a driver coupled to the conveyance device and configured to rotate at least the sleeve sensor section. The driver may rotate the sleeve sensor section independent of the conveyance device. The driver may rotate the sleeve sensor section at a preset substantially constant rotational speed. The sleeve may include at least one arm configured to selectively lock the sleeve to a surface in the borehole. The driver may rotate the sleeve sensor section during measurement by the sensor. The driver may selectively couple the sleeve. | 06-05-2014 |
20150160367 | Determination and Display of Apparent Resistivity of Downhole Transient Electromagnetic Data - Systems, devices, and methods for evaluating an earth formation. Methods may include inducing a current in the formation; measuring a time-dependent transient electromagnetic (TEM) signal induced by the formation responsive to the current; and estimating apparent resistivity values for each of a plurality of samples derived from the TEM measurement, wherein each sample corresponds to a discrete time window of the TEM measurement. Estimating the apparent resistivity values for each of the samples includes determining for each sample a simulated homogeneous formation that provides a best fit for the sample. The apparent resistivity values may be used to estimate distance to an interface. The apparent resistivity values or the estimated distance may be logged and the log displayed. The apparent resistivity values, the estimated distance, or the log may be used to conduct further operations in a borehole, including geosteering. | 06-11-2015 |
Patent application number | Description | Published |
20090024346 | IMPORTATION OF VIRTUAL SIGNALS INTO ELECTRONIC TEST EQUIPMENT TO FACILITATE TESTING OF AN ELECTRONIC COMPONENT - Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data. | 01-22-2009 |
20100100786 | SERIAL TEST MODE OF AN INTEGRATED CIRCUIT (IC) - A methodology to perform testing of integrated circuits (IC) wherein a reduced number of Input/Output (IO) pins may used to load testing patterns and capture test results from test structures after an IC has been installed in its intended application is provided. This methodology utilizes a software engine that receives and translates a parallel test pattern into serial data patterns operable to be provided on the reduced number of I/O pins. A serial process loader then loads the serial data patterns to the test structures within the IC. The IC receives the serial patterns and in turn translates them into parallel test patterns in order to apply the test patterns to the appropriate test structures. The results are captured and then translated into a serial format for communication from the IC to a test unit for analysis. | 04-22-2010 |
20100235584 | Lateral Castout (LCO) Of Victim Cache Line In Data-Invalid State - A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state. | 09-16-2010 |
20130205087 | FORWARD PROGRESS MECHANISM FOR STORES IN THE PRESENCE OF LOAD CONTENTION IN A SYSTEM FAVORING LOADS - A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address. | 08-08-2013 |
20130205096 | FORWARD PROGRESS MECHANISM FOR STORES IN THE PRESENCE OF LOAD CONTENTION IN A SYSTEM FAVORING LOADS BY STATE ALTERATION - A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected. | 08-08-2013 |
20130205098 | FORWARD PROGRESS MECHANISM FOR STORES IN THE PRESENCE OF LOAD CONTENTION IN A SYSTEM FAVORING LOADS - A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address. | 08-08-2013 |
20130205099 | FORWARD PROGRESS MECHANISM FOR STORES IN THE PRESENCE OF LOAD CONTENTION IN A SYSTEM FAVORING LOADS BY STATE ALTERATION - A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected. | 08-08-2013 |
20150227464 | ADAPTIVELY ENABLING AND DISABLING SNOOPING FASTPATH COMMANDS - Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache. | 08-13-2015 |
20150269076 | ADAPTIVELY ENABLING AND DISABLING SNOOPING FASTPATH COMMANDS - Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache. | 09-24-2015 |
20160062891 | CACHE BACKING STORE FOR TRANSACTIONAL MEMORY - In response to a transactional store request, the higher level cache transmits, to the lower level cache, a backup copy of an unaltered target cache line in response to a target real address hitting in the higher level cache, updates the target cache line with store data to obtain an updated target cache line, and records the target real address as belonging to a transaction footprint of the memory transaction. In response to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signals failure of the memory transaction to the processor core, invalidates the updated target cache line in the higher level cache, and causes the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line. | 03-03-2016 |
20160062892 | CACHE BACKING STORE FOR TRANSACTIONAL MEMORY - In response to a transactional store request, the higher level cache transmits, to the lower level cache, a backup copy of an unaltered target cache line in response to a target real address hitting in the higher level cache, updates the target cache line with store data to obtain an updated target cache line, and records the target real address as belonging to a transaction footprint of the memory transaction. In response to a conflicting access to the transaction footprint prior to completion of the memory transaction, the higher level cache signals failure of the memory transaction to the processor core, invalidates the updated target cache line in the higher level cache, and causes the backup copy of the target cache line in the lower level cache to be restored as a current version of the target cache line. | 03-03-2016 |
Patent application number | Description | Published |
20090094496 | System and Method for Improved LBIST Power and Run Time - A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. | 04-09-2009 |
20090164731 | SYSTEM AND METHOD FOR OPTIMIZING NEIGHBORING CACHE USAGE IN A MULTIPROCESSOR ENVIRONMENT - A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response. And, in the event the first PU determines to transmit the castout cache line to the second PU, the first PU transmits the castout cache line to the second PU. | 06-25-2009 |
20090164735 | System and Method for Cache Coherency In A Multiprocessor System - A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU. | 06-25-2009 |
20090164736 | System and Method for Cache Line Replacement Selection in a Multiprocessor Environment - A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block. | 06-25-2009 |
20090210566 | MULTI-CHIP DIGITAL SYSTEM SIGNAL IDENTIFICATION APPARATUS - The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers. | 08-20-2009 |
20150100731 | Techniques for Moving Checkpoint-Based High-Availability Log and Data Directly From a Producer Cache to a Consumer Cache - A technique of operating a data processing system, includes logging addresses for cache lines modified by a producer core in a data array of a producer cache to create a high-availability (HA) log for the producer core. The technique also includes moving the HA log directly from the producer cache to a consumer cache of a consumer core and moving HA data associated with the addresses of the HA log directly from the producer cache to the consumer cache. The HA log corresponds to a cache line that includes multiple of the addresses. Finally, the technique includes processing, by the consumer core, the HA log and the HA data for the data processing system. | 04-09-2015 |
20150100732 | Moving Checkpoint-Based High-Availability Log and Data Directly From a Producer Cache to a Consumer Cache - A technique of operating a data processing system, includes logging addresses for cache lines modified by a producer core in a data array of a producer cache to create a high-availability (HA) log for the producer core. The technique also includes moving the HA log directly from the producer cache to a consumer cache of a consumer core and moving HA data associated with the addresses of the HA log directly from the producer cache to the consumer cache. The HA log corresponds to a cache line that includes multiple of the addresses. Finally, the technique includes processing, by the consumer core, the HA log and the HA data for the data processing system. | 04-09-2015 |
20150127906 | Techniques for Logging Addresses of High-Availability Data - A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated. | 05-07-2015 |
20150127908 | Logging Addresses of High-Availability Data Via a Non-Blocking Channel - A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel. | 05-07-2015 |
20150127909 | Logging Addresses of High-Availability Data - A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated. | 05-07-2015 |
20150127910 | Techniques for Logging Addresses of High-Availability Data Via a Non-Blocking Channel - A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel. | 05-07-2015 |
20150363316 | PRESERVING AN INVALID GLOBAL DOMAIN INDICATION WHEN INSTALLING A SHARED CACHE LINE IN A CACHE - A technique for operating a memory system for a node includes interrogating, by a cache, an associated cache directory to determine whether a shared cache line to be installed in the cache is associated with an invalid global state in the cache. The invalid global state specifies that a version of the shared cache line has been intervened off-node. In response to the shared cache line being in the invalid global state the cache spawns a castout invalid global command for the shared cache line. The shared cache line is installed in the cache. A coherence state for the shared cache line is updated in the associated cache directory to indicate the shared cache line is shared. | 12-17-2015 |
20150363317 | TECHNIQUES FOR PRESERVING AN INVALID GLOBAL DOMAIN INDICATION WHEN INSTALLING A SHARED CACHE LINE IN A CACHE - A technique for operating a memory system for a node includes interrogating, by a cache, an associated cache directory to determine whether a shared cache line to be installed in the cache is associated with an invalid global state in the cache. The invalid global state specifies that a version of the shared cache line has been intervened off-node. In response to the shared cache line being in the invalid global state the cache spawns a castout invalid global command for the shared cache line. The shared cache line is installed in the cache. A coherence state for the shared cache line is updated in the associated cache directory to indicate the shared cache line is shared. | 12-17-2015 |
Patent application number | Description | Published |
20080229068 | ADAPTIVE FETCH GATING IN MULTITHREADED PROCESSORS, FETCH CONTROL AND METHOD OF CONTROLLING FETCHES - A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches. | 09-18-2008 |
20080263321 | Universal Register Rename Mechanism for Targets of Different Instruction Types in a Microprocessor - A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types. | 10-23-2008 |
20080263331 | Universal Register Rename Mechanism for Instructions with Multiple Targets in a Microprocessor - A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance. | 10-23-2008 |
20080313422 | Enhanced Single Threaded Execution in a Simultaneous Multithreaded Microprocessor - A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. The processing unit dispatches a first set of instructions in order from a first buffer for execution. The processing unit receives updated results from the execution of the first set of instructions. The processing unit updates, in a first register, at least one register entry associated with each instruction in the first set of instructions, with the updated results. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to the completed execution of the first set of instructions from the first buffer, the processing unit copies the set of entries from the first register to a second register. | 12-18-2008 |
20080313425 | Enhanced Load Lookahead Prefetch in Single Threaded Mode for a Simultaneous Multithreaded Microprocessor - A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if a long-latency miss associated with a load instruction has been encountered. Responsive to a long-latency miss, the processing unit enters a load lookahead mode. Responsive to entering the load lookahead mode, the processing unit dispatches each instruction from a first set of instructions from a first buffer with an associated vector. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to completed execution of the first set of instructions from the first buffer, the processing unit copies the set of vectors from a first vector array to a second vector array. Then the processing unit dispatches a second set of instructions from a second buffer with an associated vector from the second vector array. | 12-18-2008 |
20090106534 | System and Method for Implementing a Software-Supported Thread Assist Mechanism for a Microprocessor - A system and computer-implementable method for implementing software-supported thread assist within a data processing system, wherein the data processing system supports processing instructions within at least a first thread and a second thread. An instruction dispatch unit (IDU) places the first thread into a sleep mode. The IDU separates an instruction stream for the second thread into at least a first independent instruction stream and a second independent instruction stream. The first independent instruction stream is processed utilizing facilities allocated to the first thread and the second independent instruction stream is processed utilizing facilities allocated to the second thread. In response to determining a result of the processing in the first independent instruction stream requires write back to registers allocated to the second thread, the IDU sets at least one selection bit to enable selective copying of content within registers allocated to the first thread to registers allocated to the second thread. | 04-23-2009 |
20090106538 | System and Method for Implementing a Hardware-Supported Thread Assist Under Load Lookahead Mechanism for a Microprocessor - The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread. | 04-23-2009 |
20110283095 | Hardware Assist Thread for Increasing Code Parallelism - Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread. | 11-17-2011 |
20110283096 | REGISTER FILE SUPPORTING TRANSACTIONAL PROCESSING - A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, the mapper moves a first register value of the logical register to the second level register file, places the second register value in the first level register file, marks the second register value as speculative, and replaces a first mapping for the logical register with a second mapping. Responsive to unsuccessful termination of the transactional code section, the mapper designates the second register value in the first level register file as invalid so that the first register value in the second level register file becomes the working value. | 11-17-2011 |
20110296148 | Transactional Memory System Supporting Unbroken Suspended Execution - Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued. | 12-01-2011 |
20110302392 | INSTRUCTION TRACKING SYSTEM FOR PROCESSORS - A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group. | 12-08-2011 |
20120072700 | MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS - A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution. | 03-22-2012 |
20120204009 | MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS - A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution. | 08-09-2012 |
20120216004 | THREAD TRANSITION MANAGEMENT - Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination. | 08-23-2012 |
20120239904 | SEAMLESS INTERFACE FOR MULTI-THREADED CORE ACCELERATORS - A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator. | 09-20-2012 |
20120254594 | Hardware Assist Thread for Increasing Code Parallelism - Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread. | 10-04-2012 |
20120284720 | HARDWARE ASSISTED SCHEDULING IN COMPUTER SYSTEM - Apparatus and methods for hardware assisted scheduling of software tasks in a computer system are disclosed. For example, a computer system comprises a first pool for maintaining a set of executable software threads, a first scheduler, a second pool for maintaining a set of active software threads, and a second scheduler. The first scheduler assigns a subset of the set of executable software threads to the set of active software threads and the second scheduler dispatches one or more threads from the set of active software threads to a set of hardware threads for execution. In one embodiment, the first scheduler is implemented as part of the operating system of the computer system, and the second scheduler is implemented in hardware. | 11-08-2012 |
20130013899 | Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions - Mechanisms are provided for performing escape actions within transactions. These mechanisms execute a transaction comprising a transactional section and an escape action. The transactional section is comprised of one or more instructions that are to be executed in an atomic manner as part of the transaction. The escape action is comprised of one or more instructions to be executed in a non-transactional manner. These mechanisms further populate at least one actions list data structure, associated with a thread of the data processing system that is executing the transaction, with one or more actions associated with the escape action. Moreover, these mechanisms execute one or more actions in the actions list data structure based upon whether the transaction commits successfully or is aborted. | 01-10-2013 |
20130305022 | Speeding Up Younger Store Instruction Execution after a Sync Instruction - Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction. | 11-14-2013 |
20130346731 | INSTRUCTION TRACKING SYSTEM FOR PROCESSORS - Instructions are tracked in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group. | 12-26-2013 |
20140075131 | METHOD AND APPARATUS FOR DETERMINING FAILURE CONTEXT IN HARDWARE TRANSACTIONAL MEMORIES - A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions in to the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions. | 03-13-2014 |
20140075132 | METHOD AND APPARATUS FOR DETERMINING FAILURE CONTEXT IN HARDWARE TRANSACTIONAL MEMORIES - A method for diagnosing an aborted transaction from a plurality of transactions is executed by a processor core with a transactional memory, that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions in to the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions. | 03-13-2014 |
20140075151 | DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS - There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages. | 03-13-2014 |
20140075441 | METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES - A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction. | 03-13-2014 |
20140081936 | METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES - A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction. | 03-20-2014 |
20140115297 | DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS - There is provided a system and a computer program product for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages. | 04-24-2014 |
20140115590 | METHOD AND APPARATUS FOR CONDITIONAL TRANSACTION ABORT AND PRECISE ABORT HANDLING - A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for comparing multiple parameters, and aborting the transaction by the transactional-memory system based upon a comparison of the multiple parameters. | 04-24-2014 |
20140258691 | THREAD TRANSITION MANAGEMENT - Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination. | 09-11-2014 |
20150143083 | Techniques for Increasing Vector Processing Utilization and Efficiency Through Vector Lane Predication Prediction - Techniques for increasing vector processing utilization and efficiency through use of unmasked lanes of predicated vector instructions for executing non-conflicting instructions are provided. In one aspect, a method of vector lane predication for a processor is provided which includes the steps of: fetching predicated vector instructions from a memory; decoding the predicated vector instructions; determining if a mask value of the predicated vector instructions is available and, if the mask value of the predicated vector instructions is not available, predicting the mask value of the predicated vector instructions; and dispatching the predicated vector instructions to only masked vector lanes. | 05-21-2015 |
20160092231 | INDEPENDENT MAPPING OF THREADS - Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads. | 03-31-2016 |
20160092276 | INDEPENDENT MAPPING OF THREADS - Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads. | 03-31-2016 |
Patent application number | Description | Published |
20100101441 | Offset Printing Transfer Cylinder Base Cover with Alignment Stripes for Precision Installation of a Flexible Jacket Cover also with Alignment Stripes - In a printing unit having a transfer cylinder for transferring a freshly printed substrate, a flexible jacket having at least one horizontally disposed first means for visual alignment is disclosed and a cylinder base cover having at least one horizontally disposed second means for visual alignment is disclosed, wherein the first means for visual alignment and the second means for visual alignment are used in combination during at least one of attaching the flexible jacket to the transfer cylinder over the cylinder base cover and adjusting the free play of the flexible jacket, wherein the flexible jacket is movable relative to the cylinder base cover. | 04-29-2010 |
20100154665 | Anti-marking Jackets Comprised of Fluoropolymer and Methods of Using in Offset Printing - In a printing press having a transfer cylinder for transferring a freshly printed substrate, an anti-marking device is provided. The anti-marking device comprises a flexible jacket comprised of fluoropolymer to engage the freshly printed substrate as it is transferred over the transfer cylinder, the anti-marking device removably attached with free play to the transfer cylinder. In an embodiment, a base cover is installed on the transfer cylinder between the anti-marking device and the transfer cylinder. | 06-24-2010 |
20100154667 | Multiple Layer Anti-marking Jackets and Methods of Using in Offset Printing - In a printing press having a transfer cylinder for transferring a freshly printed substrate, an anti-marking device is provided. The anti-marking device comprises an assembly of at least two flexible jackets, the assembly removably attached with free play to the transfer cylinder, wherein an outermost flexible jacket supports the freshly printed substrate as it passes over the transfer cylinder and wherein the outermost flexible jacket is removable from the assembly while the assembly remains attached to the transfer cylinder. In an embodiment, a base cover is attached to the transfer cylinder, and the assembly is removably attached with free play to the transfer cylinder over the base cover. | 06-24-2010 |
20120152138 | Hook to Fabric Fastener Closure Tool - In a printing press having a transfer cylinder for transferring a freshly printed substrate, a method of preparing the printing press for printing. The method comprises placing a first edge of an assembly of flexible jackets over a hook type attachment structure coupled to a first edge of the transfer cylinder and pressing the assembly of flexible jackets into contact with the hook type attachment structure, wherein the pressing is performed by rolling surface contact between the assembly of flexible jackets and an attachment tool comprising a handle and a cylinder coupled to the handle, wherein the outer surface of the cylinder is irregular in texture. | 06-21-2012 |
20120192739 | Reversible Anti-Marking Jackets and Methods of Using - In a printing press having a transfer cylinder for transferring a freshly printed substrate, an anti-marking device is provided. The anti-marking device comprises a flexible jacket having a first surface and a second surface, each surface having projections projecting from the surface. When the flexible jacket is installed over the transfer cylinder with the second surface positioned facing towards the transfer cylinder the first surface is positioned to engage the freshly printed substrate as it is transferred over the transfer cylinder, and when the flexible jacket is installed over the transfer cylinder with the first surface positioned facing towards the transfer cylinder the second surface is positioned to engage the freshly printed substrate as it is transferred over the transfer cylinder. The anti-marking device is removably attached to the transfer cylinder. | 08-02-2012 |
20120192743 | Reversible Anti-marking Jackets and Method of Using - A method of operating a printing press comprising installing an anti-marking jacket over a cylinder of the press, wherein the jacket comprises a first structure coupled to a gripper edge of the jacket, a second structure coupled to the jacket about one inch away from the first structure towards a tail edge of the jacket, and a third structure coupled to the tail edge of the jacket, wherein installing the jacket comprises attaching the first structure to a fourth structure coupled to an inner lip of the cylinder at a gripper edge of the cylinder, attaching the second structure to a fifth structure coupled to an outer lip of the cylinder at the gripper edge of the cylinder, and attaching the third structure to a sixth structure. The method further comprises, after installing the jacket over the cylinder, printing a plurality of substrates. | 08-02-2012 |
20120325100 | ANTI-MARKING JACKETS COMPRISED OF FLUOROPOLYMER AND METHODS OF USING IN OFFSET PRINTING - In a printing press having a transfer cylinder for transferring a freshly printed substrate, an anti-marking device is provided. The anti-marking device comprises a flexible jacket comprised of fluoropolymer to engage the freshly printed substrate as it is transferred over the transfer cylinder, the anti-marking device removably attached with free play to the transfer cylinder. In an embodiment, a base cover is installed on the transfer cylinder between the anti-marking device and the transfer cylinder. | 12-27-2012 |
20130152810 | Anti-marking Jackets Comprised of Fluoropolymer and Methods of Using in Offset Printing - In a printing press having a transfer cylinder for transferring a freshly printed substrate, an anti-marking device is provided. The anti-marking device comprises a flexible jacket comprised of fluoropolymer to engage the freshly printed substrate as it is transferred over the transfer cylinder, the anti-marking device removably attached with free play to the transfer cylinder. In an embodiment, a base cover is installed on the transfer cylinder between the anti-marking device and the transfer cylinder. | 06-20-2013 |
20140096694 | Anti-marking Jackets Comprised of Fluoropolymer and Methods of Using in Offset Printing - In a printing press having a blanket for transferring a print image to a substrate, a blanket cleaning device. The device comprises a feed cylinder, a continuous tape having an adhesive on one surface initially stored on the feed cylinder, a take-up cylinder configured to take-up consumed continuous tape, and a drive mechanism synchronized to the rotation of a blanket cylinder that rotates the feed cylinder and the take-up cylinder, whereby the continuous tape removes surfactants from the blanket. | 04-10-2014 |
20150101501 | BEADED PARTIALLY COATED ANTI-MARKING JACKETS - A removable flexible jacket for use in a printing press having a transfer cylinder for transferring a freshly printed substrate comprises a sheet of woven fabric, a beaded film sheet coupled to the sheet of woven fabric, and an image disposed between the sheet of woven fabric and the beaded film sheet. The image is visible through the beaded film sheet, and wherein the image divides at least a portion of a surface of the beaded film sheet into a plurality of zones. | 04-16-2015 |
Patent application number | Description | Published |
20080205281 | Scheduling synchronization techniques for wireless networks - Various embodiments are described relating to scheduling synchronization techniques for wireless networks. According to an example embodiment, a technique may include receiving a first bandwidth grant from a first wireless node, estimating a time of receipt for a second bandwidth grant from the first wireless node based on the receiving of the first bandwidth grant from the first wireless node, and issuing a third bandwidth grant to a second wireless node before the estimated time of receipt for the second bandwidth grant from the first wireless node. Other embodiments are provided as well. | 08-28-2008 |
20120215851 | On The Managed Peer-To-Peer Sharing In Cellular Networks - A method, system and apparatus are provided for performing peer-to-peer (P2P) data sharing operations between user equipment (UE) devices in a wireless-enabled communications environment. A first client node comprises content data and operates in a server peer mode to provide content data. A second client node submits a request to a P2P application server (P2P AS) for the content data. In response, the P2P AS provides the address of the first client node to the second client node. The second client node then uses the provided address to submit a request to the first client node to provide the content data. The first client node accepts the request and then provides the content data to the second client node. | 08-23-2012 |
20120226802 | Controlling Network Device Behavior - A sender device is able to send packets over a network destined to a receiver device, and the sender device receives response information that is responsive to the packets. A behavior of the sender device with respect to data transmission on plural subflows of a connection is controlled based on the response information. | 09-06-2012 |
20120257566 | ROUTING DIFFERENT SUBSETS OF AN INTERNET PROTOCOL FLOW OVER DIFFERENT POINTS OF ATTACHMENT - An IP flow is received by an Internet Protocol (IP) mobility anchor point, where the IP mobility anchor point is to anchor traffic of a mobile node. The IP mobility anchor point routes different subsets of the packets of the IP flow to corresponding different points of attachment of the mobile node. | 10-11-2012 |
20130235728 | ESTIMATION OF ACCESS QUALITY IN MOBILE COMMUNICATION SYSTEMS - Communicating between a first node in a network and a second node includes determining, by a third node in the network that is in communication with the first node, a value of an additive path quality metric for a path segment between the third node and a fourth node, and a value of the additive path quality metric for a path segment between the third node and a fifth node. Path quality is estimated for each of multiple different paths between the first node and the second node based at least in part on the values of the additive path quality metric determined by the third node. At least two of the multiple different paths include at least one path segment in common. | 09-12-2013 |
20130235747 | ESTIMATION OF ACCESS QUALITY IN MOBILE COMMUNICATION SYSTEMS - Communicating in a network over a path that includes a first node includes: receiving from the first node, at a second node on the path, a packet addressed to a destination; forwarding the packet from the second node to the destination; determining, at the second node, a first time associated with forwarding the packet to the destination; receiving, at the second node, an acknowledgement of the packet from the destination; determining, at the second node, a second time associated with receiving the acknowledgement at the second node; and forwarding the acknowledgment from the second node to the first node. The acknowledgment includes timing information based on the first time and second time. | 09-12-2013 |
20130288673 | COLLABORATIVE SCHEME FOR SELECTION OF OPTIMAL ACCESSES AND SEAMLESS TRANSITION BETWEEN ACCESSES - Devices and methods are disclosed for selecting an optimal access network in a wireless communications environment, such as when offloading mobile data traffic. In various embodiments disclosed herein, a contributing device comprises processing logic configured to generate set of communication environment identification data corresponding to the location of the communication device, to generate a set of observed AN availability and communication performance data corresponding to the location of the communication device and, and to transmit the set of communication environment identification data and the set of observed communication performance data to a server. In some embodiments, the contributing device is location-aware and in some embodiments, the contributing device is location-unaware. | 10-31-2013 |
20150282148 | SCHEDULING SYSTEMS AND METHODS FOR WIRELESS NETWORKS - In one embodiment, a method is performed by a base station in a wireless network. The method includes receiving from a user device a request to reconfigure already-active uplink semi-persistent scheduling (SPS). The already-active uplink SPS grants the user device a resource block allocation (RBA) and a modulation and coding scheme (MCS) for periodic uplink transmissions. The already-active uplink SPS includes a time-interval parameter, the time-interval parameter specifying a time interval between the periodic uplink transmissions. The request includes information related to a proposed adjustment of the time-interval parameter. The method further includes reconfiguring the already-active uplink SPS. The reconfiguring includes modifying the time-interval parameter based, at least in part, on the information. | 10-01-2015 |
Patent application number | Description | Published |
20080291116 | CELLULAR ANTENNAS AND COMMUNICATIONS METHODS - An antenna includes a main controller for communicating with an external system, a plurality of peripheral devices and a number of sub-controllers. The peripheral devices are associated with sub-controllers. The main controller communicates with the peripheral devices over a hybrid communications bus, addressing both bus-addressable devices and serial addressable devices. | 11-27-2008 |
20090040106 | Cellular Antennas and Communications Methods - An antenna includes a number of controllers and a number of peripheral devices. A first controller is configured to communicate commands and/or data between the antenna and a device outside of the antenna, such as a remote controller. The controllers are configured to communicate commands and/or data and to control the peripheral devices. | 02-12-2009 |
20110003507 | Multi-shot Connector Assembly and Method of Manufacture - A coaxial cable connector formed via multi-shot injection molding has a body formed by multiple injection molding layers of different injection moldable materials about a central inner contact to form an integral connector body. The connector body is provided with a coaxial dielectric spacer of dielectric polymer surrounding the inner contact; a coaxial inner body of injection molded metal composition surrounding an outer diameter of the dielectric spacer; and an outer body of polymer surrounding the inner body. Interlock features provide axial and/or rotational interlock between the layers of the connector. | 01-06-2011 |
20110241954 | RF TILT SENSING USING MEMS ACCELEROMETERS - A physical angle of a portion of a variable element, such as a phase shifter, is used to determine a desired antenna beam attribute, such as beam downtilt. In one example, a variable element includes a stationary circuit board and a rotatable circuit board. The stationary circuit board has at least one transmission line having a first output and a second output. The rotatable circuit board includes an input and a coupling section, the coupling section located to capacitively couple an input signal to the at least one transmission line between the first output and the second output, and the accelerometer being oriented such that it provides a signal indicative of a physical angle of the rotatable circuit board with respect to vertical. | 10-06-2011 |
20110267231 | Cellular Antenna Phase Shifter Positioning Using Motorized Torque Lever - An actuator providing improved torque, control, and reduced motor and actuator size is provided. An actuator according to one example may include a base plate, a stationary ring gear on the base plate, the ring gear having an arc of substantially less than a conventional full circle ring gear, a pivot assembly and a drive shaft. In one example, the ring gear is approximately half a circle. The pivot assembly may be pivotally mounted on the base plate. The pivot assembly may also have a control board, a stepper motor and a drive gear coupled to an output shaft of the stepper motor, the drive gear mounted on the pivot assembly such that the drive gear engages the stationary ring gear. In one example, the stepper motor is coupled to the drive gear via a worm gear, spur gear, and a shaft. In another example, the drive gear is mounted directly on the output shaft of the stepper motor. The actuator also includes a drive shaft having an axis parallel to a pivot of the pivot assembly. | 11-03-2011 |
20130252478 | Integrated AISG Connector Assembly - A connector assembly is provided. In one example, the connector assembly includes a connector plate, a connector bracket, and a wiring set. The connector plate has a male connector shell and a female connector shell. The connector bracket has a male connector core and a female connector core. The connector bracket is dimensioned to be mounted on the connector plate with the male connector core disposed within the male connector shell and the female connector core disposed within the female connector shell. The wiring set is coupled to the male connector core and to the female connector core, and is further provides a pigtail connection. | 09-26-2013 |
Patent application number | Description | Published |
20080302524 | APPARATUS FOR WELLBORE COMMUNICATION - Methods and apparatus for communicating between surface equipment and downhole equipment. One embodiment of the invention provides a wellhead assembly that allows electrical power and signals to pass into and out of the well during drilling operations, without removing the valve structure above the wellhead. Another embodiment of the invention provides an electromagnetic casing antenna system for two-way communication with downhole tools. Another embodiment of the invention provides an antenna module for a resistivity sub that effectively controls and seals the primary/secondary interface gap. | 12-11-2008 |
20100126776 | Subsea Drilling With Casing - A method of forming a wellbore includes providing a drilling assembly comprising one or more lengths of casing and an axially retracting assembly having a first tubular; a second tubular at least partially disposed in the first tubular and axially fixed thereto; and a support member disposed in the second tubular and movable from a first axial position to a second axial position relative to the second tubular, wherein, in the first axial position, the support member maintains the second tubular axially fixed to the first tubular, and in the second axial position, allows the second tubular to move relative to the first tubular; and an earth removal member disposed below the axially retracting assembly. The method also includes rotating the earth removal member to form the wellbore; moving the support member to the second axial position; and reducing a length of the axially retracting assembly. | 05-27-2010 |
20110011646 | APPARATUS AND METHODS FOR DRILLING A WELLBORE USING CASING - Apparatus and methods for drilling with casing. In an embodiment, methods and apparatus for deflecting casing using a diverter apparatus are disclosed. In another embodiment, the apparatus comprises a motor operating system disposed in a motor system housing, a shaft operatively connected to the motor operating system, the shaft having a passageway, and a divert assembly disposed to direct fluid flow selectively to the motor operating system and the passageway in the shaft. In another aspect, methods and apparatus for directionally drilling a casing into the formation are disclosed. Methods and apparatus for measuring the trajectory of a wellbore while directionally drilling a casing into the formation are also described. | 01-20-2011 |
20110174483 | APPARATUS FOR GRIPPING A TUBULAR ON A DRILLING RIG - Methods and apparatus are provided for running tubulars into and out of a wellbore. A tubular handling system having a tubular gripping apparatus having a gripping mechanism and a sensor adapted to track movement of the gripping mechanism, wherein the sensor sends a signal to a controller when the gripping apparatus is in a position that corresponds to the gripping apparatus being engaged with the tubular | 07-21-2011 |
20120138298 | METHODS AND APPARATUS FOR WELLBORE CONSTRUCTION AND COMPLETION - The present invention relates methods and apparatus for lining a wellbore. In one aspect, a drilling assembly having an earth removal member and a wellbore lining conduit is manipulated to advance into the earth. The drilling assembly includes a first fluid flow path and a second fluid flow path. Fluid is flowed through the first fluid flow path, and at least a portion of which may return through the second fluid flow path. In one embodiment, the drilling assembly is provided with a third fluid flow path. After drilling has been completed, wellbore lining conduit may be cemented in the wellbore. | 06-07-2012 |
20120168228 | APPARATUS AND METHODS FOR DRILLING A WELLBORE USING CASING - Apparatus and methods for drilling with casing. In an embodiment, methods and apparatus for deflecting casing using a diverter apparatus are disclosed. In another embodiment, the apparatus comprises a motor operating system disposed in a motor system housing, a shaft operatively connected to the motor operating system, the shaft having a passageway, and a divert assembly disposed to direct fluid flow selectively to the motor operating system and the passageway in the shaft. In another aspect, methods and apparatus for directionally drilling a casing into the formation are disclosed. Methods and apparatus for measuring the trajectory of a wellbore while directionally drilling a casing into the formation are also described. | 07-05-2012 |
20140006227 | SERIALIZATION AND DATABASE METHODS FOR TUBULARS AND OILFIELD EQUIPMENT | 01-02-2014 |
20140116686 | APPARATUS FOR GRIPPING A TUBULAR ON A DRILLING RIG - Methods and apparatus are provided for running tubulars into and out of a wellbore. A tubular handling system having a tubular gripping apparatus having a gripping mechanism and a sensor adapted to track movement of the gripping mechanism, wherein the sensor sends a signal to a controller when the gripping apparatus is in a position that corresponds to the gripping apparatus being engaged with the tubular | 05-01-2014 |
20140196900 | METHOD AND APPARATUS FOR SEALING TUBULARS - A method of controlling fluid flow between two tubulars includes disposing a sealing member in an annular area between two tubulars, wherein the two tubulars partially overlap; moving the sealing member to a lower position where it is not in contact with one of the tubulars, thereby allowing fluid flow through the annular area; and moving the sealing member to an upper position where it is in contact with both of the tubulars, thereby preventing fluid flow through the annular area. | 07-17-2014 |
20140196910 | APPARATUS AND METHODS OF RUNNING CASING - In one embodiment, the first casing string is releasably coupled to a second casing string using a latch assembly. The second casing string is released from the conductor after the first casing string is properly positioned in the wellbore. The latch assembly is configured to release the coupling by manipulating the second casing string relative to the first casing string. | 07-17-2014 |
20140326454 | METHODS AND APPARATUS FOR WELLBORE CONSTRUCTION AND COMPLETION - The present invention relates methods and apparatus for lining a wellbore. In one aspect, a drilling assembly having an earth removal member and a wellbore lining conduit is manipulated to advance into the earth. The drilling assembly includes a first fluid flow path and a second fluid flow path. Fluid is flowed through the first fluid flow path, and at least a portion of which may return through the second fluid flow path. In one embodiment, the drilling assembly is provided with a third fluid flow path. After drilling has been completed, wellbore lining conduit may be cemented in the wellbore. | 11-06-2014 |
20150060078 | SUBSEA DRILLING WITH CASING - A method of forming a wellbore includes providing a drilling assembly comprising one or more lengths of casing and an axially retracting assembly having a first tubular; a second tubular at least partially disposed in the first tubular and axially fixed thereto; and a support member disposed in the second tubular and movable from a first axial position to a second axial position relative to the second tubular, wherein, in the first axial position, the support member maintains the second tubular axially fixed to the first tubular, and in the second axial position, allows the second tubular to move relative to the first tubular; and an earth removal member disposed below the axially retracting assembly. The method also includes rotating the earth removal member to form the wellbore; moving the support member to the second axial position; and reducing a length of the axially retracting assembly. | 03-05-2015 |
20150184461 | SUBSEA DRILLING WITH CASING - A method of forming a wellbore includes providing a drilling assembly comprising one or more lengths of casing and an axially retracting assembly having a first tubular; a second tubular at least partially disposed in the first tubular and axially fixed thereto; and a support member disposed in the second tubular and movable from a first axial position to a second axial position relative to the second tubular, wherein, in the first axial position, the support member maintains the second tubular axially fixed to the first tubular, and in the second axial position, allows the second tubular to move relative to the first tubular; and an earth removal member disposed below the axially retracting assembly. The method also includes rotating the earth removal member to form the wellbore; moving the support member to the second axial position; and reducing a length of the axially retracting assembly. | 07-02-2015 |