Patent application number | Description | Published |
20080315403 | APPARATUS AND METHODS FOR COOLING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES - Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers. | 12-25-2008 |
20090008129 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A structure. The structure includes a substrate and an interposer. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N≧2). The interposer includes N continuous interposer channels coupled to the N substrate channels to form M continuous loops (1≦M≦N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink. | 01-08-2009 |
20090008130 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A structure. The structure includes an interposer adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink. | 01-08-2009 |
20090011546 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A method of forming structure. A substrate and an interposer are provided. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N≧2). N interposer channels are coupled to the N substrate channels so as to form M continuous loops (1≦M≦N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink. | 01-08-2009 |
20090011547 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A method of forming a structure. An interposer is provided. The interposer is adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink. | 01-08-2009 |
20090184264 | LASER ANNEALING FOR 3-D CHIP INTEGRATION - A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously. | 07-23-2009 |
20090259713 | NOVEL MASSIVELY PARALLEL SUPERCOMPUTER - A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources. | 10-15-2009 |
20100117209 | MULTIPLE CHIPS ON A SEMICONDUCTOR CHIP WITH COOLING MEANS - The present invention is directed to a method of packaging multiple semiconductor chips on a second semiconductor chips with a built-in efficient cooling means. One embodiment is to place two multiple chip stacks on opposing sides of a vapor chamber for transferring heat away from the semiconductor chips. Another embodiment is to construct a vapor chamber with a substrate such that at least one multiple chip stack is embedded inside the vapor chamber. | 05-13-2010 |
20110201199 | LASER ANNEALING FOR 3-D CHIP INTEGRATION - A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously. | 08-18-2011 |
20120170221 | COMPLIANT VAPOR CHAMBER CHIP PACKAGING - An arrangement for improving the cooling efficiency of semiconductor chips. One embodiment is to construct a vapor chamber with one compliant surface for improving the efficiency of transferring heat from a semiconductor chip to the vapor chamber, and another embodiment is to construct a vapor chamber with the chip substrate such that the chips are embedded inside the vapor chamber. One surface of the vapor chamber has a flexible structure to enable the surface of the vapor chamber to be compliant with the surface of a chip or a heat sink device. | 07-05-2012 |
20120311299 | NOVEL MASSIVELY PARALLEL SUPERCOMPUTER - A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. | 12-06-2012 |
20120328789 | METAL-GRAPHITE FOAM COMPOSITE AND A COOLING APPARATUS FOR USING THE SAME - A method of producing a metal-graphite foam composite, and particularly, the utilization thereof in connection with a cooling apparatus. Also provided is a cooling apparatus, such as a liquid cooler or alternatively, a heat sink for electronic heat-generating components, which employ the metal-graphite foam composite. | 12-27-2012 |