Patent application number | Description | Published |
20090162657 | METHOD FOR MANUFACTURING METAL CHIPS BY PLASMA FROM A LAYER COMPRISING SEVERAL ELEMENTS - The invention relates to a method for manufacturing chips composed of at least one electrically conductive material. Such a method comprises the following steps:
| 06-25-2009 |
20110150024 | HYBRID LASER COUPLED TO A WAVEGUIDE - A method for introducing light into a waveguide formed on the upper surface of a microelectronics substrate, by means of a distributed feedback laser device formed by the association of an SOI-type structure having a portion forming said waveguide, of a stack of III-V semiconductor gain materials partially covering the waveguide, and of an optical grating, wherein the grating step is selected so that the optical power of the laser beam circulates in a loop from the III-V stack to the waveguide. | 06-23-2011 |
20110180776 | OPTOELECTRONIC DEVICE BASED ON NANOWIRES AND CORRESPONDING PROCESSES - The invention relates to a method for making optoelectronic devices comprising nanowire semiconductors, in which: the nanowires ( | 07-28-2011 |
20120063717 | METHOD OF PRODUCING A PHOTONIC DEVICE AND CORRESPONDING PHOTONIC DEVICE - Method of producing a photonic device including at least one light source and at least one photodetector on a structure including a waveguide layer, this method comprising the following steps: a) growing successively on a substrate ( | 03-15-2012 |
20120187488 | FIELD EFFECT DEVICE PROVIDED WITH A THINNED COUNTER-ELECTRODE AND METHOD FOR FABRICATING - A field effect device comprises a substrate of semiconductor on insulator type successively provided with a support substrate, an electrically insulating layer and a semiconductor material film. First and second source/drain electrodes are formed in the semiconductor material layer. A conduction channel is formed in the semiconductor material layer and separates the first and second source/drain electrodes. A counter-electrode is formed in the support substrate and faces the first and second source/drain electrodes and the conduction channel. The counter-electrode is formed by a doped area of the support substrate having a first doping impurity concentration which decreases from an interface between the electrically insulating layer and the support substrate. | 07-26-2012 |
20120187489 | FIELD EFFECT DEVICE PROVIDED WITH A LOCALIZED DOPANT DIFFUSION BARRIER AREA AND FABRICATION METHOD - The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes. | 07-26-2012 |
20120190214 | METHOD FOR FABRICATING A FIELD EFFECT DEVICE WITH WEAK JUNCTION CAPACITANCE - The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes. | 07-26-2012 |
20120256262 | FIELD EFFECT TRANSISTOR WITH OFFSET COUNTER-ELECTRODE CONTACT - The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode. | 10-11-2012 |
20130109191 | METHOD TO PREPARE SEMI-CONDUCTOR DEVICE COMPRISING A SELECTIVE ETCHING OF A SILICIUM-GERMANIUM LAYER | 05-02-2013 |
20130113004 | LIGHT-EMITTING DEVICE WITH HEAD-TO-TAIL P-TYPE AND N-TYPE TRANSISTORS - A light-emitting microelectronic device including a first N-type transistor (T | 05-09-2013 |
20130113066 | UTBB CMOS IMAGER - An image sensor device comprising at least one transistor lying on a semiconductor-on-insulator substrate, the substrate comprising a thin semi-conducting layer wherein a channel area of said transistor is made, an insulating layer separating the thin semi-conducting layer with a semi-conducting support layer, the device being characterized in that the semi-conducting support layer comprises at least one photosensitive area including at least one P-doped region and at least one N-doped region forming a junction provided facing the channel area of said transistor. | 05-09-2013 |
20130161746 | TRANSISTOR AND METHOD OF FABRICATION - A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned toward an upper face of the active layer and a source and a drain disposed on both sides of the gate. At least one among the source and the drain extends at least partly through the active layer and into the insulating layer. | 06-27-2013 |
20130189825 | METHOD OF PRODUCING INSULATION TRENCHES IN A SEMICONDUCTOR ON INSULATOR SUBSTRATE - A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of:
| 07-25-2013 |
20130302955 | METHOD FOR PRODUCING A TRANSISTOR STRUCTURE WITH SUPERIMPOSED NANOWIRES AND WITH A SURROUNDING GATE - The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. | 11-14-2013 |
20130309449 | METHOD FOR TREATING THE SURFACE OF A SILICON SUBSTRATE - The present invention relates to a method for chemically treating the surface condition of a silicon substrate for the roughness contrast characterized in that it comprises at least two successive treatment cycles, with each treatment cycle comprising a first step including placing in contact the silicon substrate with a first solution containing water diluted hydrofluoric (HF) acid and then a second step carried out at a temperature of less than 40° C., comprising placing in contact the silicon layer with a second solution containing water (H | 11-21-2013 |
20140061798 | MICROELECTRONIC DEVICE WITH ISOLATION TRENCHES EXTENDING UNDER AN ACTIVE AREA - A microelectronic device including:
| 03-06-2014 |
20140087524 | METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION THROUGH THE SPACERS - The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free. | 03-27-2014 |
20140127871 | METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH A SiGe CHANNEL BY ION IMPLANTATION - The semiconductor-on-insulator substrate includes a support, an electrically insulating film, a crystalline film made from semiconductor material, and a protection layer. Germanium ions are implanted in the semiconductor material film through the protection layer so as to form an amorphized area in contact with the protection layer and a crystalline area in contact with the electrically insulating film. The semiconductor material film is annealed so as to recrystallize the amorphized area from the crystalline area. | 05-08-2014 |
20140302661 | CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES - A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material. | 10-09-2014 |
20140312461 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 10-23-2014 |