Patent application number | Description | Published |
20090206867 | Self-Test Method for Interface Circuit - An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal. | 08-20-2009 |
20090240968 | METHOD FOR CALIBRATING READ OPERATIONS IN A MEMORY SYSTEM - A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations. Each of the read operations performs a read of pre-specified data stored in at least one memory component while using different ones of delayed enable signals. Data read from respective dummy read operations is compared to identify successful read operations while the timing information from successful read operations is compared to identify a suitable delayed enable signal. | 09-24-2009 |
20090278565 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 11-12-2009 |
20100259295 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 10-14-2010 |
20110193591 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 08-11-2011 |
20120170389 | MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS - A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit comprises an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal. | 07-05-2012 |
20130021056 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 01-24-2013 |
20140254294 | MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS - An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal. | 09-11-2014 |
Patent application number | Description | Published |
20100312991 | Microprocessor with Compact Instruction Set Architecture - A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions, and the re-encoded ISA can maintain assembly-level compatibility with the ISA from which it is derived. In addition, the re-encoded ISA can have new and different types of additional instructions, including instructions with encoded arguments determined by statistical analysis and instructions that have the effect of combinations of instructions. | 12-09-2010 |
20120030392 | System and Method for Automatic Hardware Interrupt Handling - A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented | 02-02-2012 |
20120323552 | Apparatus and Method for Hardware Initiation of Emulated Instructions - A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register. | 12-20-2012 |
20120324164 | Programmable Memory Address - A method includes storing defined memory address segments and defined memory address segment attributes for a processor. The processor is operated in accordance with the defined memory address segments and defined memory address segment attributes. | 12-20-2012 |
20130191426 | Merged Floating Point Operation Using a Modebit - A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output. | 07-25-2013 |
20150121044 | MERGED FLOATING POINT OPERATION USING A MODEBIT - A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output. | 04-30-2015 |
Patent application number | Description | Published |
20090193134 | Guide based content services - Systems are described for a guide of audio, video, multimedia transmission, receiving and playback with advertising and bi-directional fulfillment of goods and services over the Internet. A method of streaming content distribution includes creating data on streaming content; creating data on network locations of streaming content; creating data on access characteristics; locating a source of streaming content with a with a streaming content guide; and starting playback of streaming content from the source of streaming content. A streaming content distribution system includes a streaming content guide through which a user locates a source of streaming content and starts playback of streaming content; data on streaming content; data on network locations of streaming content; and data on access characteristics. | 07-30-2009 |
20130191210 | GUIDE BASED CONTENT SERVICES - Systems are described for a guide of audio, video, multimedia transmission, receiving and playback with advertising and bi-directional fulfillment of goods and services over the Internet. A method of streaming content distribution includes creating data on streaming content; creating data on network locations of streaming content; creating data on access characteristics; locating a source of streaming content with a with a streaming content guide; and starting playback of streaming content from the source of streaming content. A streaming content distribution system includes a streaming content guide through which a user locates a source of streaming content and starts playback of streaming content; data on streaming content; data on network locations of streaming content; and data on access characteristics. | 07-25-2013 |
20130191748 | GUIDE BASED CONTENT SERVICES - Systems are described for a guide of audio, video, multimedia transmission, receiving and playback with advertising and bi-directional fulfillment of goods and services over the Internet. A method of streaming content distribution includes creating data on streaming content; creating data on network locations of streaming content; creating data on access characteristics; locating a source of streaming content with a with a streaming content guide; and starting playback of streaming content from the source of streaming content. A streaming content distribution system includes a streaming content guide through which a user locates a source of streaming content and starts playback of streaming content; data on streaming content; data on network locations of streaming content; and data on access characteristics. | 07-25-2013 |
Patent application number | Description | Published |
20090321897 | METHOD AND APPARATUS OF POWER RING POSITIONING TO MINIMIZE CROSSTALK - A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire. | 12-31-2009 |
20100276816 | SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT - Disclosed are a system and method of separate probe and bond regions of an integrated circuit (IC). An IC, an I/O region adjacent to the core region to enable the core region, and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area outside the I/O region of the IC are disclosed. The die metal interconnect may have a length that is greater than the bond pad area length and/or the probe pad area length, and a width that is less than the bond pad area width and/or the probe pad area width. An in-front staggering technique may be used at a die corner of the IC to maintain the bond pad area in the I/O region, and a side staggering technique may be used at the die corner of the IC to maintain the bond pad area in the I/O region. | 11-04-2010 |
20140312475 | DIE REUSE IN ELECTRICAL CIRCUITS - A die having multiple sets of contact pads, with each such set having two or more contact pads distributed over the die and electrically interconnected using a respective electrical intra-die path to enable die reuse in a manner that causes electrical inter-die buses to be relatively short in length. Each electrical intra-die path can optionally include one or more respective buffer circuits configured to reduce degradation of the various signals that are being shared by the reused dies. In some embodiments, multiple reused dies can be arranged in a linear or two-dimensional array on an interposer or on the package substrate and packaged together with one or more non-reused dies in a single integrated-circuit package. | 10-23-2014 |
Patent application number | Description | Published |
20090160411 | FAST VOLTAGE REGULATORS FOR CHARGE PUMPS - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 06-25-2009 |
20100188138 | Fast Start Charge Pump for Voltage Regulators - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 07-29-2010 |
20110121799 | Fast Voltage Regulators For Charge Pumps - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 05-26-2011 |
20120074923 | Fast Voltage Regulators For Charge Pumps - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 03-29-2012 |