Patent application number | Description | Published |
20090294757 | Semiconductor Nanowire Vertical Device Architecture - The present invention relates to nanoscaled electronic devices with a vertical nanowire as a functional part. Contacts are arranged on the nanowire at different parts of the nanowire, for example drain and source contacts. In connection to the nanowire contacts are external electrodes, that connect at different levels, as seen from the substrate, of the device. The external electrodes are elongated, and typically and preferably stripe-like. According to the invention a first external electrode, or contacts, associated with contact(s) at a first part of the nanowire, and a second external electrode, associated with contact(s) at a second part of the nanowire are arranged in a cross-bar configuration. The cross-bar configuration minimizes the overlay of the external electrodes, hence, parasitic capacitances and current leakage can be reduced, and the performance of the device improved. | 12-03-2009 |
20090321716 | Semiconductor Nanowire Transistor - A nanowire wrap-gate transistor is realised in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits. | 12-31-2009 |
20100102380 | METHOD OF PRODUCING PRECISION VERTICAL AND HORIZONTAL LAYERS IN A VERTICAL SEMICONDUCTOR STRUCTURE - The present invention relates to providing layers of different thickness on vertical and horizontal surfaces ( | 04-29-2010 |
20100155702 | NANOWIRE CIRCUIT ARCHITECTURE - A nanowire circuit architecture is presented. The technology comprises of nanowire transistors ( | 06-24-2010 |
20100176459 | ASSEMBLY OF NANOSCALED FIELD EFFECT TRANSISTORS - The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic. | 07-15-2010 |
20110089477 | NANOSTRUCTURED MOS CAPACITOR - The present invention provides nanostructured MOS capacitor that comprises a nanowire (2) at least partly enclosed by a dielectric layer (5) and a gate electrode (4) that encloses at least a portion of the dielectric layer (5). Preferably the nanowire (2) protrudes from a substrate (12). The gate electrode (4) defines a gated portion (7) of the nanowire (2), which is allowed to be fully depleted when a first predetermined voltage is applied to the gate electrode (4). A method for providing a variable capacitance in an electronic circuit by using such an nanostructured MOS capacitor is also provided. Thanks to the invention it is possible to provide a MOS capacitor having an increased capacitance modulation range. It is a further advantage of the invention to provide a MOS capacitor which has relatively low depletion capacitance compared to prior art MOS capacitances. | 04-21-2011 |
20120211727 | Method of Producing Precision Vertical and Horizontal Layers in a Vertical Semiconductor Structure - The present invention relates to providing layers of different thickness on vertical and horizontal surfaces ( | 08-23-2012 |
20140048851 | SUBSTRATE COMPRISING SI-BASE AND INAS-LAYER - The present invention relates to a substrate ( | 02-20-2014 |
20140098845 | TRANSCEIVER MODULE - A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver. | 04-10-2014 |
20140103423 | METHOD OF PRODUCING PRECISION VERTICAL AND HORIZONTAL LAYERS IN A VERTICAL SEMICONDUCTOR STRUCTURE - The present invention relates to providing layers of different thickness on vertical and horizontal surfaces ( | 04-17-2014 |
20140106553 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND AN INTERMEDIATE PRODUCT FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE - According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer ( | 04-17-2014 |