Patent application number | Description | Published |
20100161907 | POSTING WEAKLY ORDERED TRANSACTIONS - A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system. | 06-24-2010 |
20130262826 | APPARATUS AND METHOD FOR DYNAMICALLY MANAGING MEMORY ACCESS BANDWIDTH IN MULTI-CORE PROCESSOR - An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature. | 10-03-2013 |
20130318292 | CACHE MEMORY STAGED REOPEN - An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state | 11-28-2013 |
20140122811 | Method And Apparatus For Error Correction In A Cache - A processor includes a core to execute instructions and a cache memory coupled to the core and having a plurality of entries. Each entry of the cache memory may include a data storage including a plurality of data storage portions, each data storage portion to store a corresponding data portion. Each entry may also include a metadata storage to store a plurality of portion modification indicators, each portion modification indicator corresponding to one of the data storage portions. Each portion modification indicator is to indicate whether the data portion stored in the corresponding data storage portion has been modified, independently of cache coherency state information of the entry. Other embodiments are described as claimed. | 05-01-2014 |
20140192069 | APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTION - An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU. | 07-10-2014 |
20140208031 | APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTIONS - An apparatus and method are described for efficiently transferring data from a producer core to a consumer core within a central processing unit (CPU). For example, one embodiment of a method comprises: A method for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising: writing data to a buffer within the producer core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core; and upon the consumer core detecting that data is available in the cache, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core. | 07-24-2014 |
20140208035 | CACHE CIRCUIT HAVING A TAG ARRAY WITH SMALLER LATENCY THAN A DATA ARRAY - A method is described that includes alternating cache requests sent to a tag array between data requests and dataless requests. | 07-24-2014 |
20140258618 | MULTI LATENCY CONFIGURABLE CACHE - Described herein are technologies for optimizing different cache configurations of a size-configurable cache. One configuration includes a base cache portion and a removable cache portion, each with different latencies. The latency of the base cache portion is modified to correspond to the latency of the removable portion. | 09-11-2014 |
20140281239 | ADAPTIVE HIERARCHICAL CACHE POLICY IN A MICROPROCESSOR - A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy. | 09-18-2014 |
20140298140 | APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY - An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. | 10-02-2014 |
20140359330 | REDUCED POWER MODE OF A CACHE UNIT - In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed. | 12-04-2014 |
20140380081 | Restricting Clock Signal Delivery In A Processor - In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed. | 12-25-2014 |