Patent application number | Description | Published |
20130138876 | COMPUTER SYSTEM WITH MEMORY AGING FOR HIGH PERFORMANCE - A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided. | 05-30-2013 |
20140181577 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 06-26-2014 |
20140281305 | Memory Image Capture via Memory Write from a Running System - Techniques for memory image capture via memory write from a running system are described. In at least some embodiments, a request is received for an image of a portion of memory. Images of memory can be used for a variety of purposes, such as diagnosing and repairing error conditions for hardware and/or software, detecting unwanted and/or malicious processes (e.g., malware), general systems maintenance, and so forth. According to one or more embodiments, various techniques can be implemented to capture an image of a portion of memory. For example, an intermediate write to memory can be employed to write the image of the portion of memory to a memory buffer. Alternatively or additionally, an image of a portion of memory can be captured directly to storage. | 09-18-2014 |
20140331019 | INSTRUCTION SET SPECIFIC EXECUTION ISOLATION - A system on a chip (SoC) or other integrated system can include a first processor and at least one additional processor sharing a page table. The shared page table can include permission bits including a first permission indicator supporting the processor and a second permission indicator supporting at least one of the at least one additional processor. In one implementation, that page table can include at least one additional bit to accommodate encodings that support the at least one additional processor. When one of the processors accesses memory, a method is performed in which a shared page table is accessed and a value of the permission indicator(s) is read from the page table to determine permissions for performing certain actions including executing a page; read/write of the page; or kernel mode with respect to the page. | 11-06-2014 |
20140359203 | STORAGE SYSTEMS AND ALIASED MEMORY - Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein. | 12-04-2014 |
20140372715 | PAGE-BASED COMPRESSED STORAGE MANAGEMENT - A memory is made up of multiple pages, and different pages can have different priority levels. A set of memory pages having at least similar priority levels are identified and compressed into an additional set of memory pages having at least similar priority levels. The additional set of memory pages are classified as being the same type of page as the set of memory pages that was compressed (e.g., as memory pages that can be repurposed). Thus, a particular set of memory pages can be compressed into a different set of memory pages of the same type and corresponding to at least similar priority levels. However, due to the compression, the quantity of memory pages into which the set of memory pages is compressed is reduced, thus increasing the amount of data that can be stored in the memory. | 12-18-2014 |
20150100738 | DYNAMICALLY DETERMINING A TRANSLATION LOOKASIDE BUFFER FLUSH PROMOTION THRESHOLD VALUE - A translation lookaside buffer (TLB) of a computing device is a cache of virtual to physical memory address translations. A TLB flush promotion threshold value indicates when all entries of the TLB are to be flushed rather than individual entries of the TLB. The TLB flush promotion threshold value is determined dynamically by the computing device by determining an amount of time it takes to flush and repopulate all entries of the TLB. A determination is then made as to the number of TLB entries that can be individually flushed and repopulated in that same amount of time. The threshold value is set based on (e.g., equal to) the number of TLB entries that can be individually flushed and repopulated in that amount of time. | 04-09-2015 |
20150242432 | Modified Memory Compression - A set of memory pages from a working set of a program process, such as at least some of the memory pages that have been modified, are compressed into a compressed store prior to being written to a page file, after which the memory pages can be repurposed by a memory manager. The compressed store is made up of multiple memory pages, and the compressed store memory pages can be repurposed by the memory manager after being written to the page file. Subsequent requests from the memory manager for memory pages that have been compressed into a compressed store are satisfied by accessing the compressed store memory pages (including retrieving the compressed store memory pages from the page file if written to the page file), decompressing the requested memory pages, and returning the requested memory pages to the memory manager. | 08-27-2015 |
20150243372 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 08-27-2015 |